ing register writes (Matt)
- Update the subject to reflect that fbc can be enabled only in
the first three planes (Matt)
v3:
- use icl_is_hdr_plane(), use wrapper macro for plane binding
register access, comments update and patch split (Ville)
Bspec: 69560
Signed-off-by: Vinod Govindapil
FBC can be supported in first three planes in lnl
Vinod Govindapillai (2):
drm/i915/lnl: possibility to enable FBC on first three planes
drm/i915/lnl: FBC is supported with per pixel alpha
drivers/gpu/drm/i915/display/intel_fbc.c | 6 +-
drivers/gpu/drm/i915/display
.
Vinod Govindapillai (1):
drm/i915/lnl: possibility to enable FBC on first three planes
drivers/gpu/drm/i915/display/intel_fbc.c | 7 ++-
drivers/gpu/drm/i915/display/skl_universal_plane.c | 5 -
drivers/gpu/drm/i915/i915_reg.h| 1 +
3 files changed, 11
in intel_fbc_check_plane (Ville)
- simplify plane binding register writes (Matt)
- Update the subject to reflect that fbc can be enabled only in
the first three planes (Matt)
Bspec: 69560
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_fbc.c | 7 ++-
drivers/
in intel_fbc_check_plane (Ville)
- simplify plane binding register writes (Matt)
- Update the subject to reflect that fbc can be enabled only in
the first three planes (Matt)
Bspec: 69560
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_fbc.c | 7 ++-
drivers/
.
Vinod Govindapillai (1):
drm/i915/lnl: possibility to enable FBC on first three planes
drivers/gpu/drm/i915/display/intel_fbc.c | 7 ++-
drivers/gpu/drm/i915/display/skl_universal_plane.c | 5 -
drivers/gpu/drm/i915/i915_reg.h| 1 +
3 files changed, 11
For LNL onwards, FBC can be supported on planes with per
pixel alpha
Bspec: 69560
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_fbc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/drivers/gpu/drm
In LNL onwards, FBC can be associated to the first three planes.
The FBC will be enabled for first FBC capable visible plane
until the userspace can select one of these FBC capable plane
explicitly
Bspec: 69560
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_fbc.c
In future platforms, FBC can be supported on planes other than
the primary plane. So update the debugfs entry for FBC status
to have the plane ID included.
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_fbc.c | 14 +++---
1 file changed, 11 insertions(+), 3
FBC restriction with PSR2 can be removed from LNL onwards
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_fbc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/drivers/gpu/drm/i915/display/intel_fbc.c
In LNL, FBC can be supported in planes other than the primary planes.
Vinod Govindapillai (4):
drm/i915/lnl: FBC can be enabled with PSR2
drm/i915/lnl: update FBC debugfs to include plane information
drm/i915/lnl: support FBC on any plane
drm/i915/lnl: FBC is supported with per pixel
Extend the SDP split audio config for DP-MST
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
drivers/gpu/drm/i915/display/intel_dp.h | 3 +++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 21 -
3 files changed, 8 insertions
Modify intel_dp_has_audio to handle DP-MST as well.
v1: fix the wrong port comparison (Jani Nikula)
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_dp.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display
SDP split config for DP-MST
v1: Fix wrong port comparison (Jani Nikula)
Vinod Govindapillai (2):
drm/i915/display: update intel_dp_has_audio to support MST
drm/i915/display: configure SDP split for DP-MST
drivers/gpu/drm/i915/display/intel_dp.c | 12 +++-
drivers/gpu/drm/i915
Extend the SDP split audio config for DP-MST
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
drivers/gpu/drm/i915/display/intel_dp.h | 3 +++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 21 -
3 files changed, 8 insertions
Modify intel_dp_has_audio to handle DP-MST as well.
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_dp.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
Combine all DP audio configs into a single function
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_dp.c | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
The needed functionality can be performed using crtc_state here.
Signed-off-by: Vinod Govindapillai
Reviewed-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_audio.c | 6 +++---
drivers/gpu/drm/i915/display/intel_audio.h | 3 +--
drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
3 files
SDP split config for DP-MST
v2: Style changes and patch splits (Jani Nikula)
v3: More style changes and reorder patches (Jani Nikula)
v4: call sdp split register update before enable trancoder in MST
Vinod Govindapillai (4):
drm/i915/display: remove redundant parameter from sdp split update
Extend the SDP split audio config for DP-MST
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
drivers/gpu/drm/i915/display/intel_dp.h | 3 +++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 19 ++-
3 files changed, 6 insertions
Modify intel_dp_has_audio to handle DP-MST as well.
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_dp.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
Combine all DP audio configs into a single function
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_dp.c | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
The needed functionality can be performed using crtc_state here.
Signed-off-by: Vinod Govindapillai
Reviewed-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_audio.c | 6 +++---
drivers/gpu/drm/i915/display/intel_audio.h | 3 +--
drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
3 files
SDP split config for DP-MST
v2: Style changes and patch splits (Jani Nikula)
v3: More style changes and reorder patches (Jani Nikula)
Vinod Govindapillai (4):
drm/i915/display: remove redundant parameter from sdp split update
drm/i915/display: combine DP audio compute config steps
drm
Extend the SDP split audio config for DP-MST
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
drivers/gpu/drm/i915/display/intel_dp.h | 4
drivers/gpu/drm/i915/display/intel_dp_mst.c | 7 +++
3 files changed, 8 insertions(+), 5 deletions
Combine all DP audio configs into a single function
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_dp.c | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
Combine has_audio check for both DP and DP-MST into a single
function.
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_dp.c | 18 +-
drivers/gpu/drm/i915/display/intel_dp.h | 3 +++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 15
The needed functionality can be performed using crtc_state here.
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_audio.c | 6 +++---
drivers/gpu/drm/i915/display/intel_audio.h | 3 +--
drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
3 files changed, 5 insertions
SDP split config for DP-MST
v2: Style changes and patch splits (Jani Nikula)
Vinod Govindapillai (4):
drm/i915/display: remove redundant parameter from sdp split update
drm/i915/display: combine has_audio check for DP and DP-MST
drm/i915/display: combine DP audio compute config steps
drm
Extend the SDP split configuration for the DP-MST
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display
Add DP2.0 SDP split support for DP-MST
Vinod Govindapillai (2):
drm/i915/display: streamline the dp audio config steps
drm/i915/display: configure SDP split for DP MST
drivers/gpu/drm/i915/display/intel_audio.c | 6 ++---
drivers/gpu/drm/i915/display/intel_audio.h | 3 +--
drivers/gpu
Combine dp audio config steps in to single a place from where
intel_audio_compute_config is checked and SDP split decision
is done.
v2: combine different audio compute calls into one (Jani Nikula)
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_audio.c | 6
Extend the DP2.0 SDP split for DP-MST configurations
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index
Optimize DP 2 SDP split config update so that DP-MST code
path can be supported as well.
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_audio.c | 6 +++---
drivers/gpu/drm/i915/display/intel_audio.h | 3 +--
drivers/gpu/drm/i915/display/intel_ddi.c | 3
Support DP2.0 sdp split for DP-MST
Vinod Govindapillai (2):
drm/i915/display: optimize DP 2.0 sdp split update config
drm/i915/display: support DP2.0 SDP split for DP-MST
drivers/gpu/drm/i915/display/intel_audio.c | 6 +++---
drivers/gpu/drm/i915/display/intel_audio.h | 3
: Vinod Govindapillai
Reviewed-by: Stanislav Lisovskiy #v4
Acked-by: Gustavo Sousa #v11
Reviewed-by: Imre Deak
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 14 +
.../gpu/drm/i915/display/intel_display_core.h | 9 +
.../drm/i915/display
Cc: Lucas De Marchi
Cc: Gustavo Sousa
Signed-off-by: José Roberto de Souza
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Gustavo Sousa
Signed-off-by: Mika Kahola
Signed-off-by: Vinod Govindapillai
Reviewed-by: Stanislav Lisovskiy
Acked-by: Gustavo Sousa
---
drivers/gpu/drm/i915
hat (Imre)
Bspec: 64636
Reported-by: kernel test robot
Closes: https://lore.kernel.org/r/202305280253.ab8brv2w-...@intel.com/
Reported-by: Dan Carpenter
Closes: https://lore.kernel.org/r/202305280253.ab8brv2w-...@intel.com/
Signed-off-by: Vinod Govindapillai
Reviewed-by: Stanislav Lisovs
by max_bw_index functions
v3: return UINT_MAX in icl_max_bw_index in case no match found
v3: check idx >= ARRAY_SIZE
Signed-off-by: Vinod Govindapillai
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_bw.c | 27 -
1 file changed, 17 inserti
Extract intel_bw_check_qgv_points() from intel_bw_atomic_check
to facilitate future platform variations in handling SAGV
configurations.
Signed-off-by: Vinod Govindapillai
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_bw.c | 235 +---
1 file
In MTL onwards, pcode locks the GV point based on the peak BW
of a QGV point. So store the peak BW of all the QGV points.
v2: use DIV_ROUND_CLOSEST() for the peakBW calculation
Bspec: 64636
Signed-off-by: Vinod Govindapillai
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display
nly DIV_ROUN_CLOSEST and remove divisor / 2 again
Bspec: 64636
Signed-off-by: Vinod Govindapillai
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_bw.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/
Follow the values from bspec for the percentage overhead for
efficiency in MTL BW calculations.
Bspec: 64631
Signed-off-by: Vinod Govindapillai
Reviewed-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_bw.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu
x27;s comments to handle non serialize cases,
updates tp phys mask during sanitize calls after HW readout
v14: check display version before accessig pmdemand functions
Mika Kahola (1):
drm/i915/mtl: Add support for PM DEMAND
Vinod Govindapillai (6):
drm/i915: fix the derating percentage fo
Roberto de Souza
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Gustavo Sousa
Signed-off-by: Mika Kahola
Signed-off-by: Vinod Govindapillai
Reviewed-by: Stanislav Lisovskiy
Acked-by: Gustavo Sousa
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/display
hat (Imre)
Bspec: 64636
Reported-by: kernel test robot
Closes: https://lore.kernel.org/r/202305280253.ab8brv2w-...@intel.com/
Reported-by: Dan Carpenter
Closes: https://lore.kernel.org/r/202305280253.ab8brv2w-...@intel.com/
Signed-off-by: Vinod Govindapillai
Reviewed-by: Stanislav Lisovs
by max_bw_index functions
v3: return UINT_MAX in icl_max_bw_index in case no match found
v3: check idx >= ARRAY_SIZE
Signed-off-by: Vinod Govindapillai
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_bw.c | 27 -
1 file changed, 17 inserti
Extract intel_bw_check_qgv_points() from intel_bw_atomic_check
to facilitate future platform variations in handling SAGV
configurations.
Signed-off-by: Vinod Govindapillai
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_bw.c | 235 +---
1 file
In MTL onwards, pcode locks the GV point based on the peak BW
of a QGV point. So store the peak BW of all the QGV points.
v2: use DIV_ROUND_CLOSEST() for the peakBW calculation
Bspec: 64636
Signed-off-by: Vinod Govindapillai
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display
nly DIV_ROUN_CLOSEST and remove divisor / 2 again
Bspec: 64636
Signed-off-by: Vinod Govindapillai
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_bw.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/
Follow the values from bspec for the percentage overhead for
efficiency in MTL BW calculations.
Bspec: 64631
Signed-off-by: Vinod Govindapillai
Reviewed-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_bw.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu
x27;s comments to handle non serialize cases,
updates tp phys mask during sanitize calls after HW readout
Mika Kahola (1):
drm/i915/mtl: Add support for PM DEMAND
Vinod Govindapillai (6):
drm/i915: fix the derating percentage for MTL
drm/i915: update the QGV point frequency calculations
/mtl: Add support for PM DEMAND
Vinod Govindapillai (6):
drm/i915: fix the derating percentage for MTL
drm/i915: update the QGV point frequency calculations
drm/i915: store the peak bw per QGV point
drm/i915: extract intel_bw_check_qgv_points()
drm/i915: modify max_bw to return index to
: Matt Roper
Cc: Lucas De Marchi
Cc: Gustavo Sousa
Signed-off-by: José Roberto de Souza
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Gustavo Sousa
Signed-off-by: Mika Kahola
Signed-off-by: Vinod Govindapillai
Reviewed-by: Stanislav Lisovskiy
Acked-by: Gustavo Sousa
---
drivers/gpu/drm
by max_bw_index functions
v3: return UINT_MAX in icl_max_bw_index in case no match found
v3: check idx >= ARRAY_SIZE
Signed-off-by: Vinod Govindapillai
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_bw.c | 27 -
1 file changed, 17 inserti
g/r/202305280253.ab8brv2w-...@intel.com/
Reported-by: Dan Carpenter
Closes: https://lore.kernel.org/r/202305280253.ab8brv2w-...@intel.com/
Signed-off-by: Vinod Govindapillai
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_bw.c | 87 -
drivers/gpu/
Extract intel_bw_check_qgv_points() from intel_bw_atomic_check
to facilitate future platform variations in handling SAGV
configurations.
Signed-off-by: Vinod Govindapillai
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_bw.c | 235 +---
1 file
In MTL onwards, pcode locks the GV point based on the peak BW
of a QGV point. So store the peak BW of all the QGV points.
v2: use DIV_ROUND_CLOSEST() for the peakBW calculation
Bspec: 64636
Signed-off-by: Vinod Govindapillai
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display
nly DIV_ROUN_CLOSEST and remove divisor / 2 again
Bspec: 64636
Signed-off-by: Vinod Govindapillai
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_bw.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/
Follow the values from bspec for the percentage overhead for
efficiency in MTL BW calculations.
Bspec: 64631
Signed-off-by: Vinod Govindapillai
Reviewed-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_bw.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu
Sripada
Signed-off-by: Gustavo Sousa
Signed-off-by: Mika Kahola
Signed-off-by: Vinod Govindapillai
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 14 +
.../gpu/drm/i915/display/intel_display_core.h
g/r/202305280253.ab8brv2w-...@intel.com/
Reported-by: Dan Carpenter
Closes: https://lore.kernel.org/r/202305280253.ab8brv2w-...@intel.com/
Signed-off-by: Vinod Govindapillai
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_bw.c | 87 -
drivers/gpu/
by max_bw_index functions
v3: return UINT_MAX in icl_max_bw_index in case no match found
v3: check idx >= ARRAY_SIZE
Signed-off-by: Vinod Govindapillai
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_bw.c | 27 -
1 file changed, 17 inserti
In MTL onwards, pcode locks the GV point based on the peak BW
of a QGV point. So store the peak BW of all the QGV points.
v2: use DIV_ROUND_CLOSEST() for the peakBW calculation
Bspec: 64636
Signed-off-by: Vinod Govindapillai
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display
Extract intel_bw_check_qgv_points() from intel_bw_atomic_check
to facilitate future platform variations in handling SAGV
configurations.
Signed-off-by: Vinod Govindapillai
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_bw.c | 235 +---
1 file
nly DIV_ROUN_CLOSEST and remove divisor / 2 again
Bspec: 64636
Signed-off-by: Vinod Govindapillai
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_bw.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/
Follow the values from bspec for the percentage overhead for
efficiency in MTL BW calculations.
Bspec: 64631
Signed-off-by: Vinod Govindapillai
Reviewed-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_bw.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu
DEMAND
Vinod Govindapillai (6):
drm/i915: fix the derating percentage for MTL
drm/i915: update the QGV point frequency calculations
drm/i915: store the peak bw per QGV point
drm/i915: extract intel_bw_check_qgv_points()
drm/i915: modify max_bw to return index to intel_bw_info
drm/i915/mtl
Sousa
Signed-off-by: Mika Kahola
Signed-off-by: Vinod Govindapillai
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 14 +
.../gpu/drm/i915/display/intel_display_core.h | 9 +
.../drm/i915/display
g/r/202305280253.ab8brv2w-...@intel.com/
Reported-by: Dan Carpenter
Closes: https://lore.kernel.org/r/202305280253.ab8brv2w-...@intel.com/
Signed-off-by: Vinod Govindapillai
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_bw.c | 87 -
drivers/gpu/
by max_bw_index functions
v3: return UINT_MAX in icl_max_bw_index in case no match found
v3: check idx >= ARRAY_SIZE
Signed-off-by: Vinod Govindapillai
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_bw.c | 27 -
1 file changed, 17 inserti
Extract intel_bw_check_qgv_points() from intel_bw_atomic_check
to facilitate future platform variations in handling SAGV
configurations.
Signed-off-by: Vinod Govindapillai
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_bw.c | 235 +---
1 file
In MTL onwards, pcode locks the GV point based on the peak BW
of a QGV point. So store the peak BW of all the QGV points.
v2: use DIV_ROUND_CLOSEST() for the peakBW calculation
Bspec: 64636
Signed-off-by: Vinod Govindapillai
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display
nly DIV_ROUN_CLOSEST and remove divisor / 2 again
Bspec: 64636
Signed-off-by: Vinod Govindapillai
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_bw.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/
Follow the values from bspec for the percentage overhead for
efficiency in MTL BW calculations.
Bspec: 64631
Signed-off-by: Vinod Govindapillai
Reviewed-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_bw.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu
max ddiclk and active phys calculations
v8: updates to active phys calcuations
v9: Address styling issues
v10: Updates to phys calculation, pmdemand state initialization during
HW readout / sanitization
Mika Kahola (1):
drm/i915/mtl: Add support for PM DEMAND
Vinod Govindapillai (6
: José Roberto de Souza
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Gustavo Sousa
Signed-off-by: Mika Kahola
Signed-off-by: Vinod Govindapillai
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 14
>From MTL onwards, we need to find the best QGV point based on
the required data rate and pass the peak BW of that point to
the punit to lock the corresponding QGV point.
Bspec: 64636
Signed-off-by: Vinod Govindapillai
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/disp
by max_bw_index functions
v3: return UINT_MAX in icl_max_bw_index in case no match found
Signed-off-by: Vinod Govindapillai
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_bw.c | 27 -
1 file changed, 17 insertions(+), 10 deletions(-)
diff --git
Extract intel_bw_check_qgv_points() from intel_bw_atomic_check
to facilitate future platform variations in handling SAGV
configurations.
Signed-off-by: Vinod Govindapillai
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_bw.c | 235 +---
1 file
In MTL onwards, pcode locks the GV point based on the peak BW
of a QGV point. So store the peak BW of all the QGV points.
v2: use DIV_ROUND_CLOSEST() for the peakBW calculation
Bspec: 64636
Signed-off-by: Vinod Govindapillai
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display
nly DIV_ROUN_CLOSEST and remove divisor / 2 again
Bspec: 64636
Signed-off-by: Vinod Govindapillai
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_bw.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/
Follow the values from bspec for the percentage overhead for
efficiency in MTL BW calculations.
Bspec: 64631
Signed-off-by: Vinod Govindapillai
Reviewed-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_bw.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu
max ddiclk and active phys calculations
v8: updates to active phys calcuations
v9: Address styling issues
Mika Kahola (1):
drm/i915/mtl: Add support for PM DEMAND
Vinod Govindapillai (6):
drm/i915: fix the derating percentage for MTL
drm/i915: update the QGV point frequency calculations
: Radhakrishna Sripada
Signed-off-by: Gustavo Sousa
Signed-off-by: Mika Kahola
Signed-off-by: Vinod Govindapillai
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 14 +
.../gpu/drm/i915/display
>From MTL onwards, we need to find the best QGV point based on
the required data rate and pass the peak BW of that point to
the punit to lock the corresponding QGV point.
Bspec: 64636
Signed-off-by: Vinod Govindapillai
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/disp
by max_bw_index functions
v3: return UINT_MAX in icl_max_bw_index in case no match found
Signed-off-by: Vinod Govindapillai
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_bw.c | 27 -
1 file changed, 17 insertions(+), 10 deletions(-)
diff --git
Extract intel_bw_check_qgv_points() from intel_bw_atomic_check
to facilitate future platform variations in handling SAGV
configurations.
Signed-off-by: Vinod Govindapillai
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_bw.c | 235 +---
1 file
from v5
v7: Rebased and updates to max ddiclk and active phys calculations
v8: updates to active phys calcuations
Mika Kahola (1):
drm/i915/mtl: Add support for PM DEMAND
Vinod Govindapillai (6):
drm/i915: fix the derating percentage for MTL
drm/i915: update the QGV point frequency
In MTL onwards, pcode locks the GV point based on the peak BW
of a QGV point. So store the peak BW of all the QGV points.
v2: use DIV_ROUND_CLOSEST() for the peakBW calculation
Bspec: 64636
Signed-off-by: Vinod Govindapillai
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display
nly DIV_ROUN_CLOSEST and remove divisor / 2 again
Bspec: 64636
Signed-off-by: Vinod Govindapillai
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_bw.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/
Follow the values from bspec for the percentage overhead for
efficiency in MTL BW calculations.
Bspec: 64631
Signed-off-by: Vinod Govindapillai
Reviewed-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_bw.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu
count method (Gustavo)
Bspec: 66451, 64636, 64602, 64603
Cc: Matt Atwood
Cc: Matt Roper
Cc: Lucas De Marchi
Cc: Gustavo Sousa
Signed-off-by: José Roberto de Souza
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Gustavo Sousa
Signed-off-by: Mika Kahola
Signed-off-by: Vinod Govindapillai
>From MTL onwards, we need to find the best QGV point based on
the required data rate and pass the peak BW of that point to
the punit to lock the corresponding QGV point.
Bspec: 64636
Signed-off-by: Vinod Govindapillai
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/disp
by max_bw_index functions
v3: return UINT_MAX in icl_max_bw_index in case no match found
Signed-off-by: Vinod Govindapillai
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_bw.c | 27 -
1 file changed, 17 insertions(+), 10 deletions(-)
diff --git
Extract intel_bw_check_qgv_points() from intel_bw_atomic_check
to facilitate future platform variations in handling SAGV
configurations.
Signed-off-by: Vinod Govindapillai
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_bw.c | 235 +---
1 file
In MTL onwards, pcode locks the GV point based on the peak BW
of a QGV point. So store the peak BW of all the QGV points.
v2: use DIV_ROUND_CLOSEST() for the peakBW calculation
Bspec: 64636
Signed-off-by: Vinod Govindapillai
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display
nly DIV_ROUN_CLOSEST and remove divisor / 2 again
Bspec: 64636
Signed-off-by: Vinod Govindapillai
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_bw.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/
Follow the values from bspec for the percentage overhead for
efficiency in MTL BW calculations.
Bspec: 64631
Signed-off-by: Vinod Govindapillai
Reviewed-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_bw.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu
from v5
v7: Rebased and updates to max ddiclk and acvit phys calculatoins
Mika Kahola (1):
drm/i915/mtl: Add support for PM DEMAND
Vinod Govindapillai (6):
drm/i915: fix the derating percentage for MTL
drm/i915: update the QGV point frequency calculations
drm/i915: store the peak bw per QGV
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