On 2010.09.02 16:56:19 +0200, Daniel Vetter wrote:
If I'm not completely mistaken, all these ringbuffer register have the
same offsets over a common base: 0x02000 for the render ring, 0x04000 for
bsd on gen5, 0x12000 for bsd on gen6.
yes, 0x22000 for blitter on gen6.
Can't we just store
On 2010.07.16 14:46:28 -0400, Adam Jackson wrote:
+ if (output_reg == DP_A || IS_PCH_eDP(dp_priv)) {
+ type = DRM_MODE_CONNECTOR_eDP;
+ intel_encoder-type = INTEL_OUTPUT_EDP;
+ } else {
+ type = DRM_MODE_CONNECTOR_DisplayPort;
+
Signed-off-by: Zhenyu Wang zhen...@linux.intel.com
---
drivers/char/agp/intel-agp.h |4
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/drivers/char/agp/intel-agp.h b/drivers/char/agp/intel-agp.h
index 08d4753..78124a8 100644
--- a/drivers/char/agp/intel-agp.h
+++ b
New intel gfx device requires new GTT controls. Add them
into under kernel include dir to be shared with drm/i915
driver.
Signed-off-by: Zhenyu Wang zhen...@linux.intel.com
---
include/linux/intel-gtt.h | 20
1 files changed, 20 insertions(+), 0 deletions(-)
create mode
Sandybridge GTT has new cache control bits in PTE, which controls
graphics page cache in LLC or LLC/MLC. This one trys to use new type
mask function for that. And this sets cache control to always LLC only
by default on Gen6.
Signed-off-by: Zhenyu Wang zhen...@linux.intel.com
---
drivers/char
Signed-off-by: Zhenyu Wang zhen...@linux.intel.com
---
drivers/char/agp/intel-agp.c | 24 +++-
1 files changed, 15 insertions(+), 9 deletions(-)
diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c
index ddf5def..ab19039 100644
--- a/drivers/char/agp
bits are internal to intel hw,
so I don't add new flags in agp_backend.h but add them only in
intel_gtt.c. So drm/i915 stuff needs to know these new flags too.
Signed-off-by: Zhenyu Wang zhen...@linux.intel.com
---
drivers/char/agp/intel-gtt.c| 57
Signed-off-by: Zhenyu Wang zhen...@linux.intel.com
---
drivers/char/agp/intel-agp.c|2 ++
drivers/char/agp/intel-agp.h|1 +
drivers/gpu/drm/i915/i915_drv.c |1 +
3 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp
On 2010.08.05 09:05:15 +0100, Chris Wilson wrote:
Please illuminate the poor ignorant fool (that's me) what the requirements
for eDP are. Even better in patch form. ;-)
Does eDP require panel fitting always?
yeah, you can see recently added panel fitting support for eDP, it
should be same
On 2010.08.05 11:25:26 +0100, Chris Wilson wrote:
v2: Hook in DP paths to keep FULLSCREEN panel fitting on eDP.
Looks fine to me.
Reviewed-by: Zhenyu Wang zhen...@linux.intel.com
--
Open Source Technology Center, Intel ltd.
$gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827
On 2010.08.04 15:04:01 +0100, Chris Wilson wrote:
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_drv.h |2 +
drivers/gpu/drm/i915/intel_display.c | 16 +++
drivers/gpu/drm/i915/intel_lvds.c| 70
--
3
On 2010.08.04 13:51:01 +1000, Dave Airlie wrote:
From: Dave Airlie airl...@redhat.com
In general unbounded while loops waiting on hardware are a bad plan,
nobody seems to have designed hardware that doesn't screw you at some
point. This might be due to race condition between threads, and
On 2010.07.14 15:40:56 -0700, Jesse Barnes wrote:
Fixes https://bugs.freedesktop.org/show_bug.cgi?id=28739. We need to
enable power to the panel with the AUX VDD bit in order to properly
detect the eDP attached panel, and we also need to turn the panel on in
case it was off when we started
On 2010.07.01 13:18:39 +1000, Dave Airlie wrote:
Has anyone seen and/or fixed:
https://bugs.freedesktop.org/show_bug.cgi?id=27471
Looks this timing is really a corner case in our PLL calculation,
which is not covered in current error range. So I tried to fallback
to the most close one.
On 2010.06.29 09:47:04 -0400, Adam Jackson wrote:
On Tue, 2010-06-29 at 16:44 +0800, Zhenyu Wang wrote:
On 2010.06.28 14:04:56 +0800, Zhenyu Wang wrote:
sorry, this is still broken on the 16x9 panel.
'intel_dp_link_required' is 107840*18/8 = 242640,
'intel_dp_max_data_rate
On 2010.06.14 18:19:46 -0700, Eric Anholt wrote:
On Sat, 12 Jun 2010 14:32:21 +0800, Zhenyu Wang zhen...@linux.intel.com
wrote:
From: Zhao Yakui yakui.z...@intel.com
This one adds support for eDP that connected on PCH DP-D port
instead of CPU DP-A port, and only DP-D port could be used
Eric, I've queued some patches on my 'for-anholt' branch of
drm-intel tree. The first and second ones are resent patch for
fixing eDP through PCH DP port. And following patches are
watermark fixes that recently investigated by Yakui.
The last one is FBC enabling patch for Ironlake, after Yakui
From: Zhao Yakui yakui.z...@intel.com
For self-refresh mode WM calculation's line time should use
mode's htotal instead of hdisplay. surface width is the hdisplay
for display plane and 64 for cursor plane.
Signed-off-by: Zhao Yakui yakui.z...@intel.com
Signed-off-by: Zhenyu Wang zhen
From: Zhao Yakui yakui.z...@intel.com
In SR mode cursor plane watermark calculation uses same formula
like display plane. This one fixes the case for 965G and G45.
Signed-off-by: Zhao Yakui yakui.z...@intel.com
Signed-off-by: Zhenyu Wang zhen...@linux.intel.com
---
drivers/gpu/drm/i915
-by: Zhenyu Wang zhen...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h |3 ++
drivers/gpu/drm/i915/intel_display.c | 56 --
2 files changed, 56 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
From: Zhao Yakui yakui.z...@intel.com
About 0.2W power can be saved on one HP laptop.
Signed-off-by: Zhao Yakui yakui.z...@intel.com
Signed-off-by: Zhenyu Wang zhen...@linux.intel.com
---
drivers/gpu/drm/i915/i915_dma.c |9 ++--
drivers/gpu/drm/i915/i915_drv.c |2 +-
drivers
yakui.z...@intel.com
Signed-off-by: Zhenyu wang zhen...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h |3 ++-
drivers/gpu/drm/i915/intel_display.c |4 ++--
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915
-by: Zhenyu Wang zhen...@linux.intel.com
---
drivers/gpu/drm/i915/intel_display.c | 12
1 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 7ffd51c..c757019 100644
--- a/drivers/gpu/drm/i915
...@jhz.name
Tested-by: Templar temp...@rshc.de
Signed-off-by: Zhenyu Wang zhen...@linux.intel.com
---
drivers/gpu/drm/i915/intel_display.c |2 +-
drivers/gpu/drm/i915/intel_dp.c | 71 +
drivers/gpu/drm/i915/intel_drv.h |1 +
3 files changed, 64
bits are internal to intel hw,
so I don't add new flags in agp_backend.h but add them only in
intel_gtt.c. So drm/i915 stuff needs to know these new flags too.
Signed-off-by: Zhenyu Wang zhen...@linux.intel.com
---
drivers/char/agp/intel-agp.c|4 +-
drivers/char/agp/intel-agp.h|6
On 2010.05.21 07:59:53 -0700, Jeffrey Baker wrote:
Just got a laptop in the mail and no existing Linux distribution that
I've tried works on it. It appears to be Xorg bug #27471 (ubuntu bug
#554569). Unfortunately it makes the laptop totally useless as the
internal panel is disabled on boot,
:
885a5fb5b120a5c7e0b3baad7b0feb5a89f76c18 is the first bad commit
commit 885a5fb5b120a5c7e0b3baad7b0feb5a89f76c18
Author: Zhenyu Wang zhen...@linux.intel.com
Date: Tue Jan 12 05:38:31 2010 +0800
drm/i915: fix pixel color depth setting on eDP
Original DP mode_valid check didn't take pixel
On 2010.05.14 10:53:50 +0800, Zhenyu Wang wrote:
I tried to test this with noop request and issue PIPE_CONTROL
command for each sequence and track notify interrupts, which
seems work fine. Hopefully we don't need workaround like on
Ironlake for Sandybridge.
oh, I've another patch which
On 2010.05.17 22:07:30 +0800, Li Peng wrote:
Pineview with DDR3 memory has different latencies to enable CxSR.
This patch updates CxSR latency table to add Pineview DDR3 latency
configuration. It also adds one flag is_ddr3 for checking DDR3
setting in MCHBAR.
This is not against
On 2010.05.15 03:46:35 +0200, Mikael Öhman wrote:
Hello.
I was wondering if it was possible to send audio over displayport using a Core
i5 661 (Clarkdale) IGP.
I have seen some charts indicating that the hardware actually supports it, but
I'm not even sure if I should ask here or perhaps to
interrupts, which
seems work fine. Hopefully we don't need workaround like on
Ironlake for Sandybridge.
Signed-off-by: Zhenyu Wang zhen...@linux.intel.com
---
drivers/gpu/drm/i915/i915_gem.c | 77 +++
drivers/gpu/drm/i915/i915_reg.h | 11 +-
2 files
On 2010.05.03 11:41:33 -0700, Carl Worth wrote:
On Thu, 29 Apr 2010 16:42:37 -0700, Eric Anholt e...@anholt.net wrote:
Since it's only in -next right now, do you have plans to look into why
this went wrong? I'm concerned that we're reverting a bugfix to
revisit later with no plan to
fengguang...@intel.com
Signed-off-by: Zhenyu Wang zhen...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h |3 +++
drivers/gpu/drm/i915/intel_hdmi.c |5 -
2 files changed, 7 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
Signed-off-by: Zhenyu Wang zhen...@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_chipset.h |4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_chipset.h
b/src/mesa/drivers/dri/intel/intel_chipset.h
index dbc08c8..cd614c5 100644
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