[Intel-gfx] [RFC] drm/i915: adding state checker for gamma lut values

From: Swati Sharma Added state checker to validate gamma_lut values. This reads hardware state, and compares the originally requested state to the state read from hardware. This implementation can be used for Gen9+ platforms, I haven't implemented it for legacy platforms. Just want to get feedba

[Intel-gfx] [PATCH 5/6] drm/i915/icl: Add Y2xx and Y4xx (xx:10/12/16) plane control definitions

From: Swati Sharma Added needed plane control flag definitions for Y2xx and Y4xx (10, 12 and 16 bits) Signed-off-by: Swati Sharma Signed-off-by: Vidya Srinivas Reviewed-by: Juha-Pekka Heikkila Reviewed-by: Maarten Lankhorst --- drivers/gpu/drm/i915/i915_reg.h | 6 ++ 1 file changed, 6 i

[Intel-gfx] [PATCH 6/6] drm/i915/icl: Enabling Y2xx and Y4xx (xx:10/12/16) formats for universal planes

From: Swati Sharma Signed-off-by: Swati Sharma Signed-off-by: Vidya Srinivas Reviewed-by: Juha-Pekka Heikkila Reviewed-by: Maarten Lankhorst --- drivers/gpu/drm/i915/intel_display.c | 30 ++ drivers/gpu/drm/i915/intel_sprite.c | 60 +++- 2 fil

[Intel-gfx] [PATCH 3/6] drm/i915: Enable P010, P012, P016 formats for primary and sprite planes

From: Juha-Pekka Heikkila Enabling of P010, P012 and P016 formats. These formats will extend NV12 for larger bit depths. Signed-off-by: Juha-Pekka Heikkila Signed-off-by: Swati Sharma Reviewed-by: Maarten Lankhorst --- drivers/gpu/drm/i915/intel_sprite.c | 28 ++-- 1

[Intel-gfx] [PATCH 1/6] drm/i915: Add P010, P012, P016 plane control definitions

From: Juha-Pekka Heikkila Add needed plane control flag definitions for P010, P012 and P016 formats. Signed-off-by: Juha-Pekka Heikkila Signed-off-by: Swati Sharma Reviewed-by: Maarten Lankhorst --- drivers/gpu/drm/i915/i915_reg.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/driver

[Intel-gfx] [PATCH 4/6] drm: Add Y2xx and Y4xx (xx:10/12/16) format definitions and fourcc

From: Swati Sharma The following pixel formats are packed format that follows 4:2:2 chroma sampling. For memory represenation each component is allocated 16 bits each. Thus each pixel occupies 32bit. Y210: For each component, valid data occupies MSB 10 bits. LSB 6 bits are filled with

[Intel-gfx] [PATCH 0/6] Enable P0xx (planar), Y2xx/Y4xx (packed) pixel formats

From: Swati Sharma This patch series is for enabling P0xx, Y2xx and Y4xx pixel formats for intel's i915 driver. In this patch series, Juha Pekka's patch series Gen10+ P0xx formats https://patchwork.freedesktop.org/series/56053/ is combined with Swati's https://patchwork.freedesktop.org/series/55

[Intel-gfx] [PATCH 2/6] drm/i915: Preparations for enabling P010, P012, P016 formats

From: Juha-Pekka Heikkila Preparations for enabling P010, P012 and P016 formats. These formats will extend NV12 for larger bit depths. Signed-off-by: Juha-Pekka Heikkila Signed-off-by: Swati Sharma Reviewed-by: Maarten Lankhorst --- drivers/gpu/drm/i915/intel_atomic_plane.c | 2 +- drivers/

[Intel-gfx] [PATCH 4/7] drm/i915: enable P010, P012, P016 formats for primary and sprite planes

From: Juha-Pekka Heikkila Enabling of P010, P012 and P016 formats. These formats will extend NV12 for larger bit depths. Signed-off-by: Juha-Pekka Heikkila --- drivers/gpu/drm/i915/intel_sprite.c | 28 ++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/

[Intel-gfx] [PATCH 1/7] drm: Add P010, P012, P016 format definitions and fourcc

From: Juha-Pekka Heikkila Add P010 definition, semi-planar yuv format where each component is 16 bits 10 msb containing color value. First come Y plane [10:6] followed by 2x2 subsampled Cr:Cb plane [10:6:10:6] Add P012 definition, semi-planar yuv format where each component is 16 bits 12 msb con

[Intel-gfx] [PATCH 0/7] Enable P0xx (planar), Y2xx and Y4xx (packed) pixel formats

From: Swati Sharma In this patch series, Juha Pekka's patch series for Gen10+ P0xx formats https://patchwork.freedesktop.org/series/56053/ is combined with Swati's https://patchwork.freedesktop.org/series/55035/ for Gen11+ pixel formats (Y2xx and Y4xx). P0xx pixel formats are enabled from GLK wh

[Intel-gfx] [PATCH 7/7] drm/i915/icl: Enabling Y2xx and Y4xx (xx:10/12/16) formats for universal planes

From: Swati Sharma In this patch, apart from enabling Y2xx and Y4xx pixel formats P0xx pixel formats are added too for ICL. Signed-off-by: Swati Sharma Reviewed-by: Juha-Pekka Heikkila --- drivers/gpu/drm/i915/intel_display.c | 30 ++ drivers/gpu/drm/i915/intel_sprite.c | 60

[Intel-gfx] [PATCH 6/7] drm/i915/icl: Add Y2xx and Y4xx (xx:10/12/16) plane control definitions

From: Swati Sharma Added needed plane control flag definitions for Y2xx and Y4xx (10, 12 and 16 bits) Signed-off-by: Swati Sharma Reviewed-by: Juha-Pekka Heikkila --- drivers/gpu/drm/i915/i915_reg.h | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/dr

[Intel-gfx] [PATCH 5/7] drm: Add Y2xx and Y4xx (xx:10/12/16) format definitions and fourcc

From: Swati Sharma The following pixel formats are packed format that follows 4:2:2 chroma sampling. For memory represenation each component is allocated 16 bits each. Thus each pixel occupies 32bit. Y210: For each component, valid data occupies MSB 10 bits. LSB 6 bits are filled with

[Intel-gfx] [PATCH 2/7] drm/i915: Add P010, P012, P016 plane control definitions

From: Juha-Pekka Heikkila Add needed plane control flag definitions for P010, P012 and P016 formats. Signed-off-by: Juha-Pekka Heikkila --- drivers/gpu/drm/i915/i915_reg.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h i

[Intel-gfx] [PATCH 3/7] drm/i915: preparations for enabling P010, P012, P016 formats

From: Juha-Pekka Heikkila Preparations for enabling P010, P012 and P016 formats. These formats will extend NV12 for larger bit depths. Signed-off-by: Juha-Pekka Heikkila --- drivers/gpu/drm/i915/intel_atomic_plane.c | 2 +- drivers/gpu/drm/i915/intel_display.c | 27 +-

[Intel-gfx] [PATCH 3/3] drm/i915/icl: Enabling Y2xx and Y4xx (xx:10/12/16) formats for universal planes

From: Swati Sharma Signed-off-by: Swati Sharma --- drivers/gpu/drm/i915/intel_display.c | 30 ++ drivers/gpu/drm/i915/intel_sprite.c | 61 ++-- 2 files changed, 89 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c

[Intel-gfx] [PATCH 1/3] drm: Add Y2xx and Y4xx (xx:10/12/16) format definitions and fourcc

From: Swati Sharma The following pixel formats are packed format that follows 4:2:2 chroma sampling. For memory represenation each component is allocated 16 bits each. Thus each pixel occupies 32bit. Y210: For each component, valid data occupies MSB 10 bits. LSB 6 bits are filled with

[Intel-gfx] [PATCH 2/3] drm/i915/icl: Add Y2xx and Y4xx (xx:10/12/16) plane control definitions

From: Swati Sharma Added needed plane control flag definitions for Y2xx and Y4xx (10, 12 and 16 bits) Signed-off-by: Swati Sharma --- drivers/gpu/drm/i915/i915_reg.h | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h inde

[Intel-gfx] [PATCH 0/3] Enable Y2xx and Y4xx (xx:10/12/16 bits) packed formats for ICL

From: Swati Sharma These patches enable packed format YUV422-Y210, Y212 and Y216 and YUV444-Y410, Y412, Y416 for 10, 12 and 16 bits for ICL+. IGT needs libraries for Pixman and Cairo to support more than 8bpc. Work going on from Maarten Lankhorst. Initial review for Y2xx done https://patchwork.