On Mon, 2016-10-17 at 11:33 +0300, Ville Syrjälä wrote:
> On Fri, Oct 14, 2016 at 08:33:37PM +, Pandiyan, Dhinakaran wrote:
> > On Thu, 2016-10-13 at 21:44 +0300, Ville Syrjälä wrote:
> > > On Thu, Oct 13, 2016 at 11:04:19AM -0700, Dhinakaran Pandiyan wrote:
> > > > According to BSpec, cdclk
On Mon, Oct 17, 2016 at 08:55:51AM +0200, Daniel Vetter wrote:
> On Fri, Oct 14, 2016 at 07:27:39PM +, Pandiyan, Dhinakaran wrote:
> > On Thu, 2016-10-13 at 11:30 -0700, Jim Bride wrote:
> > > On Thu, Oct 13, 2016 at 11:04:19AM -0700, Dhinakaran Pandiyan wrote:
> > > > According to BSpec,
On Fri, Oct 14, 2016 at 08:33:37PM +, Pandiyan, Dhinakaran wrote:
> On Thu, 2016-10-13 at 21:44 +0300, Ville Syrjälä wrote:
> > On Thu, Oct 13, 2016 at 11:04:19AM -0700, Dhinakaran Pandiyan wrote:
> > > According to BSpec, cdclk has to be not less than 432 MHz with DP audio
> > > enabled, port
On Fri, Oct 14, 2016 at 07:27:39PM +, Pandiyan, Dhinakaran wrote:
> On Thu, 2016-10-13 at 11:30 -0700, Jim Bride wrote:
> > On Thu, Oct 13, 2016 at 11:04:19AM -0700, Dhinakaran Pandiyan wrote:
> > > According to BSpec, cdclk has to be not less than 432 MHz with DP audio
> > > enabled, port
> -Original Message-
> From: Pandiyan, Dhinakaran
> Sent: Saturday, October 15, 2016 4:36 AM
> To: Yang, Libin
> Cc: intel-...@freedesktop.org; Nikula, Jani ; Kp, Jeeja
> ; libin.y...@linux.intel.com
> Subject: Re:
On Fri, 2016-10-14 at 03:09 +, Yang, Libin wrote:
> Tested-by: Libin Yang
>
> Regards,
> Libin
>
>
Thanks Libin. Can you confirm the max. BCLK frequency we set for the
audio controller?
-DK
> > -Original Message-
> > From: Intel-gfx
On Thu, 2016-10-13 at 21:44 +0300, Ville Syrjälä wrote:
> On Thu, Oct 13, 2016 at 11:04:19AM -0700, Dhinakaran Pandiyan wrote:
> > According to BSpec, cdclk has to be not less than 432 MHz with DP audio
> > enabled, port width x4, and link rate HBR2 (5.4 GHz)
> >
> > Having a lower cdclk triggers
On Fri, 2016-10-14 at 11:40 +0300, Jani Nikula wrote:
> On Thu, 13 Oct 2016, Dhinakaran Pandiyan
> wrote:
> > According to BSpec, cdclk has to be not less than 432 MHz with DP audio
> > enabled, port width x4, and link rate HBR2 (5.4 GHz)
> >
> > Having a lower
On Thu, 2016-10-13 at 11:30 -0700, Jim Bride wrote:
> On Thu, Oct 13, 2016 at 11:04:19AM -0700, Dhinakaran Pandiyan wrote:
> > According to BSpec, cdclk has to be not less than 432 MHz with DP audio
> > enabled, port width x4, and link rate HBR2 (5.4 GHz)
> >
> > Having a lower cdclk triggers
On Thu, 2016-10-13 at 15:28 -0300, Paulo Zanoni wrote:
> Em Qui, 2016-10-13 às 11:04 -0700, Dhinakaran Pandiyan escreveu:
> > According to BSpec, cdclk has to be not less than 432 MHz with DP
> > audio
> > enabled, port width x4, and link rate HBR2 (5.4 GHz)
>
> This is just for pre-production
On Thu, 13 Oct 2016, Dhinakaran Pandiyan wrote:
> According to BSpec, cdclk has to be not less than 432 MHz with DP audio
> enabled, port width x4, and link rate HBR2 (5.4 GHz)
>
> Having a lower cdclk triggers pipe underruns, which then lead to displays
>
Tested-by: Libin Yang
Regards,
Libin
> -Original Message-
> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
> Dhinakaran Pandiyan
> Sent: Friday, October 14, 2016 2:04 AM
> To: intel-...@freedesktop.org
> Cc: Nikula, Jani
On Thu, Oct 13, 2016 at 11:04:19AM -0700, Dhinakaran Pandiyan wrote:
> According to BSpec, cdclk has to be not less than 432 MHz with DP audio
> enabled, port width x4, and link rate HBR2 (5.4 GHz)
>
> Having a lower cdclk triggers pipe underruns, which then lead to displays
> continuously
On Thu, Oct 13, 2016 at 11:04:19AM -0700, Dhinakaran Pandiyan wrote:
> According to BSpec, cdclk has to be not less than 432 MHz with DP audio
> enabled, port width x4, and link rate HBR2 (5.4 GHz)
>
> Having a lower cdclk triggers pipe underruns, which then lead to displays
> continuously
Em Qui, 2016-10-13 às 11:04 -0700, Dhinakaran Pandiyan escreveu:
> According to BSpec, cdclk has to be not less than 432 MHz with DP
> audio
> enabled, port width x4, and link rate HBR2 (5.4 GHz)
This is just for pre-production hardware, and we don't implement
workarounds for pre-prod.
A quick
According to BSpec, cdclk has to be not less than 432 MHz with DP audio
enabled, port width x4, and link rate HBR2 (5.4 GHz)
Having a lower cdclk triggers pipe underruns, which then lead to displays
continuously cycling off and on. This is essential for DP MST audio as the
link is trained at HBR2
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