On Mon, 2014-03-24 at 18:47 +, Chris Wilson wrote:
> On Mon, Mar 24, 2014 at 08:32:30PM +0200, Ville Syrjälä wrote:
> > On Mon, Mar 24, 2014 at 11:20:40AM +, Gupta, Sourab wrote:
> > > On Mon, 2014-03-24 at 09:32 +, Chris Wilson wrote:
> > > > On Mon, Mar 24, 2014 at 12:19:19PM +0530, s
On Mon, Mar 24, 2014 at 08:32:30PM +0200, Ville Syrjälä wrote:
> On Mon, Mar 24, 2014 at 11:20:40AM +, Gupta, Sourab wrote:
> > On Mon, 2014-03-24 at 09:32 +, Chris Wilson wrote:
> > > On Mon, Mar 24, 2014 at 12:19:19PM +0530, sourab.gu...@intel.com wrote:
> > > > From: Akash Goel
> > > >
On Mon, Mar 24, 2014 at 11:20:40AM +, Gupta, Sourab wrote:
> On Mon, 2014-03-24 at 09:32 +, Chris Wilson wrote:
> > On Mon, Mar 24, 2014 at 12:19:19PM +0530, sourab.gu...@intel.com wrote:
> > > From: Akash Goel
> > >
> > > Added a new rendering specific Workaround
> > > 'WaTlbInvalidateS
On Mon, 2014-03-24 at 09:32 +, Chris Wilson wrote:
> On Mon, Mar 24, 2014 at 12:19:19PM +0530, sourab.gu...@intel.com wrote:
> > From: Akash Goel
> >
> > Added a new rendering specific Workaround 'WaTlbInvalidateStoreDataBefore'.
> > In this WA, before pipecontrol with TLB invalidate set, nee
On Mon, Mar 24, 2014 at 12:19:19PM +0530, sourab.gu...@intel.com wrote:
> From: Akash Goel
>
> Added a new rendering specific Workaround 'WaTlbInvalidateStoreDataBefore'.
> In this WA, before pipecontrol with TLB invalidate set, need to add 2 MI
> Store data commands.
>
> Signed-off-by: Akash Go
From: Akash Goel
Added a new rendering specific Workaround 'WaTlbInvalidateStoreDataBefore'.
In this WA, before pipecontrol with TLB invalidate set, need to add 2 MI
Store data commands.
Signed-off-by: Akash Goel
Signed-off-by: Sourab Gupta
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 22 +++
On Wed, Jan 22, 2014 at 09:15:05AM +0530, akash.g...@intel.com wrote:
> From: Akash Goel
>
> Added a new rendering specific Workaround 'WaTlbInvalidateStoreDataBefore'.
> In this WA, before pipecontrol with TLB invalidate set, need to add 2 MI
> Store data commands.
>
> Signed-off-by: Akash Goel
From: Akash Goel
Added a new rendering specific Workaround 'WaTlbInvalidateStoreDataBefore'.
In this WA, before pipecontrol with TLB invalidate set, need to add 2 MI
Store data commands.
Signed-off-by: Akash Goel
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 22 ++
1 file c