From: Deepak S deepa...@intel.com
On VLV, FIFO will be shared by both SW and HW. So, we read the
free entries through register and update dev_priv variable
and wait for only 20 entries to be free
Signed-off-by: Deepak S deepa...@intel.com
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drivers/gpu/drm/i915/intel_uncore.c | 6 ++
1
On Wed, Nov 27, 2013 at 09:16:42PM +0530, deepa...@intel.com wrote:
From: Deepak S deepa...@intel.com
On VLV, FIFO will be shared by both SW and HW.
SW I take it means MMIO access coming from the CPU, and HW means eg.
LRI from some CS?
Are there any docs clearly stating this? The Gunit HAS
