This series adds i915_lpsp_info connector debugfs.
v3 has fixed some review comments on patch (2/3)
and added RB tag on patch (3/3).
Test-with: 20200326131929.23072-1-anshuman.gu...@intel.com
Anshuman Gupta (3):
drm/i915: Power well id for ICL PG3
drm/i915: Add i915_lpsp_info debugfs
drm
Gen11 onwards PG3 is contains functions for pipe B,
external displays, and VGA. It make sense to add
a power well id with name ICL_DISP_PW_3 rather then
TGL_DISP_PW_3, Also PG3 power well id requires to
know if lpsp is enabled.
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display
Add connector debugfs attributes for each intel
connector which is getting register.
v2:
- adding connector debugfs for each connector in
intel_connector_register() to fix CI failure for legacy connectors.
Reviewed-by: Jani Nikula
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915
intel_display_power_well_is_enabled() instead of looking
inside power_well count. [Jani]
- fixes the lpsp capable conditional logic. [Jani]
- combined the lpsp capable and enable info. [Jani]
Signed-off-by: Anshuman Gupta
---
.../drm/i915/display/intel_display_debugfs.c | 121 ++
.../drm/i915
gt; reads the same, detects the HDR capability and adds this to
> intel_lspcon struct.
>
> Signed-off-by: Uma Shankar
Hi Vipin ,
Looks like u forgot to add your sign-off.
Thanks,
Anshuman Gupta.
> ---
> .../drm/i915/display/intel_display_types.h| 1 +
> drivers/gpu/dr
e was missing for it.
This patch fixes it.
v2:
- Fixing hdcp CP state in intel_hdcp_atomic_check(), that will
require to check hdcp->value in intel_hdcp_update_pipe() in order
to avoid enabling hdcp, if it was already enabled.
Cc: Ramalingam C
Cc: Maarten Lankhorst
Signed-off-by: Anshum
e was missing for it.
This patch fixes it.
v2:
- Fixing hdcp CP state in intel_hdcp_atomic_check(), that will
require to check hdcp->value in intel_hdcp_update_pipe() in order
to avoid enabling hdcp, if it was already enabled.
Cc: Ramalingam C
Cc: Maarten Lankhorst
Signed-off-by: Anshum
This is resend of v3 to get CI results with
igt v4 lpsp platform agnostic support.
https://patchwork.freedesktop.org/series/74647/
Test-with: 20200331103330.31211-2-anshuman.gu...@intel.com
Anshuman Gupta (3):
drm/i915: Power well id for ICL PG3
drm/i915: Add i915_lpsp_info debugfs
drm
Gen11 onwards PG3 is contains functions for pipe B,
external displays, and VGA. It make sense to add
a power well id with name ICL_DISP_PW_3 rather then
TGL_DISP_PW_3, Also PG3 power well id requires to
know if lpsp is enabled.
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display
intel_display_power_well_is_enabled() instead of looking
inside power_well count. [Jani]
- fixes the lpsp capable conditional logic. [Jani]
- combined the lpsp capable and enable info. [Jani]
Signed-off-by: Anshuman Gupta
---
.../drm/i915/display/intel_display_debugfs.c | 124 ++
.../drm/i915
Add connector debugfs attributes for each intel
connector which is getting register.
v2:
- adding connector debugfs for each connector in
intel_connector_register() to fix CI failure for legacy connectors.
Reviewed-by: Jani Nikula
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915
5 : 1) &&
I had observed that intel_dp_detect may race between user spece invoked
get connector call and intel_encoder_hotplug(), that may leave connector status
to be UNCHANGED in actual hotplug flow as intel_dp_detect() already called from
drm_helper_probe_single_connector_modes(
arting subtest
pipe-D-ts-continuation-suspend
-
<4>[ 501.899229] [ cut here ]
<4>[ 501.899232] i915 raw-wakerefs=1 wakelocks=1 on cleanup
<4>[ 501.899280] WARNING: C
On 2020-04-01 at 21:23:28 +0530, Manna, Animesh wrote:
thanks animesh for review!
>
> On 31-03-2020 17:07, Anshuman Gupta wrote:
> >New i915_pm_lpsp igt solution approach relies on connector specific
> >debugfs attribute i915_lpsp_info, it exposes whether an output is
> >
On 2020-04-02 at 20:59:21 +0530, Manna, Animesh wrote:
>
> On 02-04-2020 18:15, Anshuman Gupta wrote:
> >On 2020-04-01 at 21:23:28 +0530, Manna, Animesh wrote:
> >thanks animesh for review!
> >>On 31-03-2020 17:07, Anshuman Gupta wrote:
> >>>New i915_
_write(dev_priv, AUD_CONFIG_BE, val);
> +}
> +
> static void hsw_audio_codec_enable(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state,
> const struct drm_connector_state *conn_state)
> @@ -529
Gen11 onwards PG3 is contains functions for pipe B,
external displays, and VGA. It make sense to add
a power well id with name ICL_DISP_PW_3 rather then
TGL_DISP_PW_3, Also PG3 power well id requires to
know if lpsp is enabled.
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display
: Anshuman Gupta
---
.../drm/i915/display/intel_display_debugfs.c | 46 +++
.../drm/i915/display/intel_display_power.h| 2 +
2 files changed, 48 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display
v4 has fixed the review comment provided by animesh.
Test-with: 20200409053951.26929-2-anshuman.gu...@intel.com
Anshuman Gupta (4):
drm/i915: Power well id for ICL PG3
drm/i915: Add i915_lpsp_capability debugfs
drm/i915: Add connector dbgfs for all connectors
drm/i915: Add
: Anshuman Gupta
---
.../drm/i915/display/intel_display_debugfs.c | 63 +++
1 file changed, 63 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index bdeea2e02642..402b89daff62 100644
--- a
Add connector debugfs attributes for each intel
connector which is getting register.
v2:
- adding connector debugfs for each connector in
intel_connector_register() to fix CI failure for legacy connectors.
Reviewed-by: Jani Nikula
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915
_VLD);
> tmp |= AUDIO_OUTPUT_ENABLE(cpu_transcoder);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8cebb7a86b8c..f72ea2c2a8e3 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9395,6 +9395,22
On 2020-04-14 at 21:16:00 +0530, Manna, Animesh wrote:
>
> On 09-04-2020 11:36, Anshuman Gupta wrote:
> >New i915_pm_lpsp igt solution approach relies on connector specific
> >debugfs attribute i915_lpsp_capability, it exposes whether an output is
> >capable of driving
Platform Gen condition to add i915_lpsp_capability
and some cosmetic nitpick changes. [Animesh]
Reviewed-by: Animesh Manna
Signed-off-by: Anshuman Gupta
---
.../drm/i915/display/intel_display_debugfs.c | 53 +++
1 file changed, 53 insertions(+)
diff --git a/drivers/gpu/drm/i915
: Animesh Manna
Signed-off-by: Anshuman Gupta
---
.../drm/i915/display/intel_display_debugfs.c | 47 +++
.../drm/i915/display/intel_display_power.h| 2 +
2 files changed, 49 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915
Add connector debugfs attributes for each intel
connector which is getting register.
v2:
- adding connector debugfs for each connector in
intel_connector_register() to fix CI failure for legacy connectors.
Reviewed-by: Jani Nikula
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915
Gen11 onwards PG3 is contains functions for pipe B,
external displays, and VGA. It make sense to add
a power well id with name ICL_DISP_PW_3 rather then
TGL_DISP_PW_3, Also PG3 power well id requires to
know if lpsp is enabled.
Reviewed-by: Animesh Manna
Signed-off-by: Anshuman Gupta
v5 has fixed the review comment for [PATCH 2/4]
provided by animesh and rebased the series.
Test-with: 20200409053951.26929-2-anshuman.gu...@intel.com
Anshuman Gupta (4):
drm/i915: Power well id for ICL PG3
drm/i915: Add i915_lpsp_capability debugfs
drm/i915: Add connector dbgfs for all
Platform Gen condition to add i915_lpsp_capability
and some cosmetic nitpick changes. [Animesh]
Reviewed-by: Animesh Manna
Signed-off-by: Anshuman Gupta
---
.../drm/i915/display/intel_display_debugfs.c | 53 +++
1 file changed, 53 insertions(+)
diff --git a/drivers/gpu/drm/i915
_state->hw.adjusted_mode.crtc_vtotal;
> + hblank_rise = crtc_state->hw.adjusted_mode.crtc_hsync_start;
IMHO with control flow this function above initilization is not
required.
u may remove this initilization if u agree, while pushing the patch.
Revi
Gen11 onwards PG3 contains functions for pipe B,
external displays, and VGA. Add missing ICL_DISP_PW_3
for ehl_power_wells.
Cc: Animesh Manna
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/1737
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_display_power.c | 2
gt; PG3
> * PG5 no longer exists due to the lack of a fourth pipe
>
> Also note that what we refer to as 'DDI-C' and 'DDI-D' need to actually
> be programmed as TC-1 and TC-2 even though this platform doesn't have TC
> outputs.
>
> Bspec: 49234
>
Cc: rodrigo.v...@intel.com
Cc: animesh.ma...@intel.com
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_display_power.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display
Added POWER_DOMAIN_VIDEO power domain and added its helper stuff.
POWER_DOMAIN_VIDEO is a hook to "DC5 Off" power well.
which can disallow DC5/6 in order to allow dc3co.
Cc: jani.nik...@intel.com
Cc: imre.d...@intel.com
Cc: animesh.ma...@intel.com
Signed-off-by: Anshuman Gupta
---
d
: jani.nik...@intel.com
Cc: imre.d...@intel.com
Cc: animesh.ma...@intel.com
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_display.c | 34 +
.../drm/i915/display/intel_display_power.c| 37 +++
.../drm/i915/display/intel_display_power.h| 4
This patch adds following definition to i915_reg.h
1. DC_STATE_EN register DC3CO bit fields and masks.
2. Transcoder EXITLINE register and its bit fields and mask.
v2: Commit log typo fixing.
Cc: jani.nik...@intel.com
Cc: imre.d...@intel.com
Cc: animesh.ma...@intel.com
Signed-off-by: Anshuman
This patch enables dc3co state in enable_dc module param
and adds dc3co enable mask to allowed_dc_mask and gen9_dc_mask.
Cc: jani.nik...@intel.com
Cc: imre.d...@intel.com
Cc: animesh.ma...@intel.com
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_display_power.c | 13
riate place haswell_crtc_enable(). [Imre]
Changed the DC3CO power well enabled call back logic as
recommended in review comments. [Imre]
v4: Used wait_for_us() instead of intel_wait_for_reg(). [Imre (IRC)]
Cc: jani.nik...@intel.com
Cc: imre.d...@intel.com
Cc: rodrigo.v...@intel.com
Cc: animesh.ma...
: animesh.ma...@intel.com
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_psr.c | 44
drivers/gpu/drm/i915/display/intel_psr.h | 2 ++
2 files changed, 46 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915
, currently driver doesn't differentiate between video playback
and a normal flip.
User space will be the best to judge if it is VPB case
otherwise we need to have that intelligence in driver.
Cc: jani.nik...@intel.com
Cc: imre.d...@intel.com
Cc: animesh.ma...@intel.com
Signed-off-by: Anshuman
co must be disabled before PSR2 is disabled.
B.Specs: https://gfxspecs.intel.com/Predator/Home/Index/49196
Anshuman Gupta (10):
drm/i915/tgl:Added DC3CO required register and bits.
i915:Added DC3CO mask to allowed_dc_mask and gen9_dc_mask.
i915:Added DC3CO power well.
drm/i915/tgl:Added mutual
: animesh.ma...@intel.com
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_debugfs.c | 9 -
drivers/gpu/drm/i915/i915_reg.h | 3 +++
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index
This patch adds following definition to i915_reg.h
1. DC_STATE_EN register DC3CO bit fields and masks.
2. Transcoder EXITLINE register and its bit fields and mask.
v2: Commit log typo fixing.
Cc: jani.nik...@intel.com
Cc: imre.d...@intel.com
Cc: animesh.ma...@intel.com
Signed-off-by: Anshuman
: animesh.ma...@intel.com
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_psr.c | 44
drivers/gpu/drm/i915/display/intel_psr.h | 2 ++
2 files changed, 46 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915
This patch enables dc3co state in enable_dc module param
and adds dc3co enable mask to allowed_dc_mask and gen9_dc_mask.
Cc: jani.nik...@intel.com
Cc: imre.d...@intel.com
Cc: animesh.ma...@intel.com
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_display_power.c | 13
Added POWER_DOMAIN_VIDEO power domain and added its helper stuff.
POWER_DOMAIN_VIDEO is a hook to "DC5 Off" power well.
which can disallow DC5/6 in order to allow dc3co.
Cc: jani.nik...@intel.com
Cc: imre.d...@intel.com
Cc: animesh.ma...@intel.com
Signed-off-by: Anshuman Gupta
---
d
, currently driver doesn't differentiate between video playback
and a normal flip.
User space will be the best to judge if it is VPB case
otherwise we need to have that intelligence in driver.
Cc: jani.nik...@intel.com
Cc: imre.d...@intel.com
Cc: animesh.ma...@intel.com
Signed-off-by: Anshuman
Cc: rodrigo.v...@intel.com
Cc: animesh.ma...@intel.com
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_display_power.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display
ble until after that programming is completed.
*DC3co must not be enabled until after PSR2 is enabled.
*DC3co must be disabled before PSR2 is disabled.
B.Specs:49196
Anshuman Gupta (10):
drm/i915/tgl:Added DC3CO required register and bits.
i915:Added DC3CO mask to allowed_dc_mask and gen9_
: animesh.ma...@intel.com
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_debugfs.c | 9 -
drivers/gpu/drm/i915/i915_reg.h | 3 +++
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index
riate place haswell_crtc_enable(). [Imre]
Changed the DC3CO power well enabled call back logic as
recommended in review comments. [Imre]
v4: Used wait_for_us() instead of intel_wait_for_reg(). [Imre (IRC)]
Cc: jani.nik...@intel.com
Cc: imre.d...@intel.com
Cc: rodrigo.v...@intel.com
Cc: animesh.ma...
: jani.nik...@intel.com
Cc: imre.d...@intel.com
Cc: animesh.ma...@intel.com
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_display.c | 34 +
.../drm/i915/display/intel_display_power.c| 37 +++
.../drm/i915/display/intel_display_power.h| 4
This patch enables dc3co state in enable_dc module param
and adds dc3co enable mask to allowed_dc_mask and gen9_dc_mask.
Cc: jani.nik...@intel.com
Cc: imre.d...@intel.com
Cc: animesh.ma...@intel.com
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_display_power.c | 13
riate place haswell_crtc_enable(). [Imre]
Changed the DC3CO power well enabled call back logic as
recommended in review comments. [Imre]
v4: Used wait_for_us() instead of intel_wait_for_reg(). [Imre (IRC)]
Cc: jani.nik...@intel.com
Cc: imre.d...@intel.com
Cc: rodrigo.v...@intel.com
Cc: animesh.ma...
CTL Idle Frames = b)
*Disable DC3co before mode set, or other Aux, PLL, and DBUF programming,
and do not re-enable until after that programming is completed.
*DC3co must not be enabled until after PSR2 is enabled.
*DC3co must be disabled before PSR2 is disabled.
B.Specs:49196
Anshuman Gupta (
This patch adds following definition to i915_reg.h
1. DC_STATE_EN register DC3CO bit fields and masks.
2. Transcoder EXITLINE register and its bit fields and mask.
v2: Commit log typo fixing.
Cc: jani.nik...@intel.com
Cc: imre.d...@intel.com
Cc: animesh.ma...@intel.com
Signed-off-by: Anshuman
Cc: rodrigo.v...@intel.com
Cc: animesh.ma...@intel.com
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_display_power.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display
, currently driver doesn't differentiate between video playback
and a normal flip.
User space will be the best to judge if it is VPB case
otherwise we need to have that intelligence in driver.
Cc: jani.nik...@intel.com
Cc: imre.d...@intel.com
Cc: animesh.ma...@intel.com
Signed-off-by: Anshuman
Added POWER_DOMAIN_VIDEO power domain and added its helper stuff.
POWER_DOMAIN_VIDEO is a hook to "DC5 Off" power well.
which can disallow DC5/6 in order to allow dc3co.
Cc: jani.nik...@intel.com
Cc: imre.d...@intel.com
Cc: animesh.ma...@intel.com
Signed-off-by: Anshuman Gupta
---
d
: jani.nik...@intel.com
Cc: imre.d...@intel.com
Cc: animesh.ma...@intel.com
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_display.c | 34 +
.../drm/i915/display/intel_display_power.c| 37 +++
.../drm/i915/display/intel_display_power.h| 4
: animesh.ma...@intel.com
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_debugfs.c | 9 -
drivers/gpu/drm/i915/i915_reg.h | 3 +++
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index
: animesh.ma...@intel.com
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_psr.c | 44
drivers/gpu/drm/i915/display/intel_psr.h | 2 ++
2 files changed, 46 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915
TGL onwards we have new DC5 and DC6 counter
DMC_DEBUG1 and DMC_DEBUG2, these counter will retain
there values upon DMC reset.
Cc: jani.nik...@intel.com
Cc: imre.d...@intel.com
Cc: animesh.ma...@intel.com
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_debugfs.c | 8 +---
drivers
determine the kms_content_protection behavior on
a particular CI system.
Cc: daniel.vet...@intel.com
Cc: ramalinga...@intel.com
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_debugfs.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/drivers/gpu/drm
On 2019-07-12 at 18:09:39 -0700, Lucas De Marchi wrote:
> From: José Roberto de Souza
>
> Tiger Lask has a new register offset for DC5 and DC6 residency counters.
>
> Signed-off-by: José Roberto de Souza
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 21 +++
determine the kms_content_protection behavior on
a particular CI system.
v2: Reused the intel_hdcp_info() in i915_hdcp_sink_capability_show(). [Ram]
Shifted intel_hdcp_info() to the end of intel_dp_info. [Ram]
Cc: daniel.vet...@intel.com
Cc: ramalinga...@intel.com
Signed-off-by: Anshuman Gupta
: ramalinga...@intel.com
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_debugfs.c | 40 -
1 file changed, 28 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 6b84d04a6a28
On 2019-07-12 at 18:09:25 -0700, Lucas De Marchi wrote:
> From: Anusha Srivatsa
>
> Add Support to load DMC v2.02 on TGL.
>
> Signed-off-by: Anusha Srivatsa
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/intel_csr.c | 7 +++
> 1 file changed, 7 insertions(+)
>
> diff --git
On 2019-07-19 at 11:39:54 -0700, Lucas De Marchi wrote:
> On Thu, Jul 18, 2019 at 11:17:03AM +0530, Anshuman Gupta wrote:
> >On 2019-07-12 at 18:09:39 -0700, Lucas De Marchi wrote:
> >>From: José Roberto de Souza
> >>
> >>Tiger Lask has a new register offse
e-enable until after that programming is completed.
*DC3co must not be enabled until after PSR2 is enabled.
*DC3co must be disabled before PSR2 is disabled.
Anshuman Gupta (9):
drm/i915/tgl: Add DC3CO required register and bits
drm/i915/tgl: Add DC3CO mask to allowed_dc_mask and gen9_dc_mask
Enables dc3co state in enable_dc module param
and adds dc3co enable mask to allowed_dc_mask and gen9_dc_mask.
Cc: Nikula, Jani
Cc: Deak, Imre
Cc: Manna, Animesh
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_display_power.c | 13 +++--
drivers/gpu/drm/i915
Adding following definition to i915_reg.h
1. DC_STATE_EN register DC3CO bit fields and masks.
2. Transcoder EXITLINE register and its bit fields and mask.
Cc: Nikula, Jani
Cc: Deak, Imre
Cc: Manna, Animesh
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_reg.h | 8
1 file
CO power well enabled call back logic as
recommended in review comments. [Imre]
v4: Used wait_for_us() instead of intel_wait_for_reg(). [Imre (IRC)]
Cc: Nikula, Jani
Cc: Deak, Imre
Cc: Manna, Animesh
Cc: Vivi, Rodrigo
Signed-off-by: Anshuman Gupta
---
.../drm/i915/display/intel_display_pow
POWER_DOMAIN_VIDEO is a hook to "DC5 Off" power well,
which can disallow DC5/6 and allow DC3CO.
It will be used when there will be PSR2 idle frame while active
video playback.
Cc: Nikula, Jani
Cc: Deak, Imre
Cc: Manna, Animesh
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i9
Add dc3co helper functions to enable/disable psr2 deep sleep.
Disallow DC3CO state before PSR2 exit, it essentially does
that by putting a reference to POWER_DOMAIN_VIDEO before
PSR2 exit.
Cc: Nikula, Jani
Cc: Deak, Imre
Cc: Manna, Animesh
Cc: Souza, Jose
Signed-off-by: Anshuman Gupta
Adding DC3CO counter in i915_dmc_info debugfs will be
useful for DC3CO validation.
DMC firmware uses DMC_DEBUG3 register as DC3CO counter
register on TGL, as per B.Specs DMC_DEBUG3 is general
purpose register.
Cc: Nikula, Jani
Cc: Deak, Imre
Cc: Manna, Animesh
Signed-off-by: Anshuman Gupta
driver doesn't differentiate between video playback
and a normal flip.
User space will be the best to judge if it is VPB case
otherwise we need to have that intelligence in driver.
Cc: Nikula, Jani
Cc: Deak, Imre
Cc: Manna, Animesh
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/di
Deak, Imre
Cc: Manna, Animesh
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_display.c | 4 ++
.../drm/i915/display/intel_display_power.c| 72 +++
.../drm/i915/display/intel_display_power.h| 5 ++
drivers/gpu/drm/i915/i915_drv.h | 1
: Vivi, Rodrigo
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_display_power.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 1d2aced7f0e7..64bf61a8b427
PI DSI dual link use case.
Cc: Deak Imre
Cc: Syrjala Ville
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_display_power.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_d
other Aux, PLL, and DBUF programming,
and do not re-enable until after that programming is completed.
*DC3co must not be enabled until after PSR2 is enabled.
*DC3co must be disabled before PSR2 is disabled.
Anshuman Gupta (9):
drm/i915/tgl: Add DC3CO required register and bits
drm/i9
Adding following definition to i915_reg.h
1. DC_STATE_EN register DC3CO bit fields and masks.
2. Transcoder EXITLINE register and its bit fields and mask.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_reg.h | 8
1 file
: Rodrigo Vivi
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_display_power.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index c570fda290c4..cd500fbdd8f3
CO power well enabled call back logic as
recommended in review comments. [Imre]
v4: Used wait_for_us() instead of intel_wait_for_reg(). [Imre (IRC)]
v5: using udelay() instead of waiting for DC3CO exit status.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Cc: Rodrigo Vivi
Signed-off-by: A
Enable dc3co state in enable_dc module param and add dc3co
enable mask to allowed_dc_mask and gen9_dc_mask.
v1: Adding enable_dc=3,4 options to enable DC3CO with DC5 and DC6
independently.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
.../drm/i915
: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +
.../drm/i915/display/intel_display_power.c| 106 ++
.../drm/i915/display/intel_display_power.h| 5 +
drivers/gpu/drm/i915/i915_drv.h
The Power domain name VIDEO is inspired from the fact that
DC3CO should be enabled only during VIDEO playback.
POWER_DOMAIN_VIDEO is a hook to "DC5 Off" power well,
which can disallow DC5/6 and allow DC3CO.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Ansh
Add dc3co helper functions to enable/disable psr2 deep sleep.
Disallow DC3CO state before PSR2 exit, it essentially does
that by putting a reference to POWER_DOMAIN_VIDEO before
PSR2 exit.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Cc: José Roberto de Souza
Signed-off-by: Anshuman Gupta
Hence dropping it, dc5_idle_thread() checks the valid wakeref before
putting the reference count, which avoids any chances of dropping
a zero wakeref. [Imre (IRC)]
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel
Adding DC3CO counter in i915_dmc_info debugfs will be
useful for DC3CO validation.
DMC firmware uses DMC_DEBUG3 register as DC3CO counter
register on TGL, as per B.Specs DMC_DEBUG3 is general
purpose register.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
Adding following definition to i915_reg.h
1. DC_STATE_EN register DC3CO bit fields and masks.
2. Transcoder EXITLINE register and its bit fields and mask.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_reg.h | 8
1 file
: Rodrigo Vivi
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_display_power.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index c9e92d48cdab..167839060154
The Power domain name VIDEO is inspired from the fact that
DC3CO should be enabled only during VIDEO playback.
POWER_DOMAIN_VIDEO is a hook to "DC5 Off" power well,
which can disallow DC5/6 and allow DC3CO.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Ansh
CO power well enabled call back logic as
recommended in review comments. [Imre]
v4: Used wait_for_us() instead of intel_wait_for_reg(). [Imre (IRC)]
v5: using udelay() instead of waiting for DC3CO exit status.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Cc: Rodrigo Vivi
Signed-off-by: A
: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +
.../drm/i915/display/intel_display_power.c| 105 ++
.../drm/i915/display/intel_display_power.h| 5 +
drivers/gpu/drm/i915/i915_drv.h
before mode set, or other Aux, PLL, and DBUF programming,
and do not re-enable until after that programming is completed.
*DC3co must not be enabled until after PSR2 is enabled.
*DC3co must be disabled before PSR2 is disabled.
Anshuman Gupta (9):
drm/i915/tgl: Add DC3CO required register and bits
Enable dc3co state in enable_dc module param and add dc3co
enable mask to allowed_dc_mask and gen9_dc_mask.
v1: Adding enable_dc=3,4 options to enable DC3CO with DC5 and DC6
independently.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
.../drm/i915
Hence dropping it, dc5_idle_thread() checks the valid wakeref before
putting the reference count, which avoids any chances of dropping
a zero wakeref. [Imre (IRC)]
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel
Add dc3co helper functions to enable/disable psr2 deep sleep.
Disallow DC3CO state before PSR2 exit, it essentially does
that by putting a reference to POWER_DOMAIN_VIDEO before
PSR2 exit.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Cc: José Roberto de Souza
Signed-off-by: Anshuman Gupta
Adding DC3CO counter in i915_dmc_info debugfs will be
useful for DC3CO validation.
DMC firmware uses DMC_DEBUG3 register as DC3CO counter
register on TGL, as per B.Specs DMC_DEBUG3 is general
purpose register.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
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