From: Clint Taylor
Most of the context WA are already implemented.
Adding adl_p platform tag to reflect so.
BSpec: 54369
Cc: Matt Roper
Cc: Aditya Swarup
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Anusha Srivatsa
Signed-off-by: Madhumitha Tolakanahalli Pradeep
Signed-off-by: José R
From: Clint Taylor
Most of the context WA are already implemented.
Adding adl_p platform tag to reflect so.
v2: adjust comments for clarity (MattR)
BSpec: 54369
Cc: Matt Roper
Cc: Aditya Swarup
Reviewed-by: Matt Roper
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Anusha Srivatsa
Signe
From: Clint Taylor
Add protections to prevent NULL de-reference for a couple variables used
in skl_check_pipe_max_pixel_clock to prevent GP exception from occurring
during some IGT tests.
References: https://bugs.freedesktop.org/show_bug.cgi?id=109084
Cc: Rodrigo Vivi
Cc: Martin Peres
Signed-
From: Clint Taylor
Skip decode options and formatting when the quiet option is used during
mmio reads. Makes intel_reg usable by scripts to return MMIO values.
Signed-off-by: Clint Taylor
---
tools/intel_reg.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/tools/inte
From: Clint Taylor
In August 2018 the BSPEC changed the ICL port programming sequence to
closely resemble earlier gen programming sequence.
BSpec: 21257
Cc: Ville Syrjälä
Cc: Imre Deak
Cc: Rodrigo Vivi
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/i915_reg.h | 4 +
drivers/gpu
From: Clint Taylor
In August 2018 the BSPEC changed the ICL port programming sequence to
closely resemble earlier gen programming sequence.
v2: remove debug code that Imre found
BSpec: 21257
Cc: Ville Syrjälä
Cc: Imre Deak
Cc: Rodrigo Vivi
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i9
From: Clint Taylor
In August 2018 the BSPEC changed the ICL port programming sequence to
closely resemble earlier gen programming sequence.
v2: remove debug code that Imre found
v3: simplify translation table if-else
BSpec: 21257
Cc: Ville Syrjälä
Cc: Imre Deak
Cc: Rodrigo Vivi
Signed-off-by
From: Clint Taylor
Setting the SCDC scrambling CTS mode causes HDMI Link Layer protocol tests
HF1-12 and HF1-13 to fail.
V2: Removed "Source Shall" entries to a new patch
V3: Rebase to drm-tip
Cc: Ville Syrjälä
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107895
Bugzilla: https://bugs
From: Clint Taylor
In August 2018 the BSPEC changed the ICL port programming sequence to
closely resemble earlier gen programming sequence. Restrict combo phy to
HBR max rate unless eDP panel is connected to port.
v2: remove debug code that Imre found
v3: simplify translation table if-else
v4: e
From: Clint Taylor
Program PORT_TX_DW7 to the value specified in the DDI Buffer section of the
BSPEC.
BSEPC: 21257
Cc: Madhav Chauhan
Cc: Jani Nikula
Cc: Imre Deak
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/icl_dsi.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/
From: Clint Taylor
In August 2018 the BSPEC changed the ICL port programming sequence to
closely resemble earlier gen programming sequence. Restrict combo phy to
HBR max rate unless eDP panel is connected to port.
v2: remove debug code that Imre found
v3: simplify translation table if-else
v4: e
From: Clint Taylor
Elkhart Lake has additional bits in port_cl_dw10 that should be set
during vswing programming. According to BSPEC these bits should be set
based on OEM selection. Since VBT does not contain a definition for
these bits we will currently clear them until VBT is updated to give
OE
From: Clint Taylor
Updated new values from BSPEC.
BSPEC: 53920
Cc: Jani Nikula
Cc: José Roberto de Souza
Cc: Imre Deak
Signed-off-by: Clint Taylor
---
.../drm/i915/display/intel_ddi_buf_trans.c| 42 +--
1 file changed, 21 insertions(+), 21 deletions(-)
diff --git a/dri
From: Clint Taylor
BSPEC: 46123
Cc: Matt Roper
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
drivers/gpu/drm/i915/i915_reg.h | 4
2 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/
From: Clint Taylor
drm/i915/adlp: Remove require_force_probe protection
Removing force probe protection from ADL_P platform. Did
not observe warnings, errors, flickering or any visual
defects while doing ordinary tasks like browsing and
editing documents in a two monitor setu
From: Clint Taylor
Remove force probe protection from ADL_P platform. Did not obsevre
warnings, errors, flickering or any visual defects while doing ordinary
tasks like browsing and editing documents in a two monitor setup.
For more info drm-tip idle run results :
https://intel-gfx-ci.01.org/tre
From: Clint Taylor
BSPEC: 46123
v2: Address review feedback [MattR]
Cc: Matt Roper
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
drivers/gpu/drm/i915/i915_reg.h | 2 ++
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/i
From: Clint Taylor
BSPEC: 46123
v2: Address review feedback [MattR]
v3: move register definition to gt_regs [MattR]
Cc: Matt Roper
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++
drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
2 files changed, 8 inse
From: Clint Taylor
During the Display Interrupt Service routine the Display Interrupt
Enable bit must be disabled, The interrupts handled, then the
Display Interrupt Enable bit must be set to prevent possible missed
interrupts.
Bspec: 49212
Cc: Lucas De Marchi
Cc: Aditya Swarup
Signed-off-by:
From: Clint Taylor
During the Display Interrupt Service routine the Display Interrupt
Enable bit must be disabled, The interrupts handled, then the
Display Interrupt Enable bit must be set to prevent possible missed
interrupts.
Bspec: 49212
Cc: Lucas De Marchi
Cc: Aditya Swarup
Reviewed-by: M
From: Clint Taylor
During the Display Interrupt Service routine the Display Interrupt
Enable bit must be disabled, The interrupts handled, then the
Display Interrupt Enable bit must be set to prevent possible missed
interrupts.
Bspec: 49212
V2: Change Title to remove SDE reference.
V3: Fix TAB s
From: Clint Taylor
Add DDR5 and LPDDR5 return values from punit fw.
BSPEC: 54023
Cc: Matt Roper
Cc: José Roberto de Souza
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/display/intel_bw.c | 12 +++-
drivers/gpu/drm/i915/i915_drv.h | 4 +++-
drivers/gpu/drm/i915/intel_d
From: Clint Taylor
Set GS Timer to 224. Combine with Wa_1604555607 due to register FF_MODE2
not being able to be read.
Cc: Caz Yokoyama
Cc: Matt Atwood
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 8
drivers/gpu/drm/i915/i915_reg.h | 2 ++
From: Clint Taylor
Set GS Timer to 224. Combine with Wa_1604555607 due to register FF_MODE2
not being able to be read.
V2: Math issue fixed
Cc: Chris Wilson
Cc: Caz Yokoyama
Cc: Matt Atwood
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 8
drivers/gp
From: Clint Taylor
Enable HW Default flip for small PL.
bspec: 52890
bspec: 53508
bspec: 53273
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/
From: Clint Taylor
Enable HW Default flip for small PL.
bspec: 52890
bspec: 53508
bspec: 53273
v2: rebase to drm-tip
Reviewed-by: Matt Atwood
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files cha
From: Clint Taylor
Enable HW Default flip for small PL.
bspec: 52890
bspec: 53508
bspec: 53273
v2: rebase to drm-tip
v3: move from ctx to gt workarounds. Remove whitelist.
Cc: Matt Atwood
Cc: Matt Roper
Cc: José Roberto de Souza
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/gt/inte
From: Clint Taylor
Enable HW Default flip for small PL.
bspec: 52890
bspec: 53508
bspec: 53273
v2: rebase to drm-tip
v3: move from ctx to gt workarounds. Remove whitelist.
v4: move to rcs WA init
Cc: Matt Atwood
Cc: Matt Roper
Cc: José Roberto de Souza
Signed-off-by: Clint Taylor
---
driv
From: Clint Taylor
In commit dc911f5bd8aa ("drm/i915/edp: Allow alternate fixed mode for eDP
if available."), the patch was always selecting the alternate refresh rate
even though user space was asking for the higher rate. This patch confirms
the alt mode setup time meets requirements and only us
From: Clint Taylor
HDMI 2.0 594Mhz modes were incorrectly selecting 25.200Mhz Automatic N value
mode instead of HDMI specification values.
V2: Fix 88.2 Hz N value
Cc: Jani Nikula
Cc: sta...@vger.kernel.org
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/intel_audio.c | 17 ++
From: Clint Taylor
reorder structure of 297, 594 N values to group Audio Sample Frequencies
together to make updating from HDMI specification easier.
V2: Match patch 1/2 version
Cc: Jani Nikula
Cc: sta...@vger.kernel.org
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/intel_audio.c | 2
From: Clint Taylor
Added HDMI 2.0 N and CTS values for 594 Pixel clock modes. Reorganized
structure to group by Audio Sample Frequency
Clint Taylor (2):
drm/i915/hdmi: Add HDMI 2.0 audio clock recovery N values
drm/i915/hdmi: Reorder structure to match specification
drivers/gpu/drm/i915/in
From: Clint Taylor
reorder structure of 297, 594 N values to group Audio Sample Frequencies
together to make updating from HDMI specification easier.
V2: Match patch 1/2 version
V3: Arrange by sample freq, then pixel clock.
Cc: Jani Nikula
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915
From: Clint Taylor
The calibration RCOMP value in PORT_TX_DW6 in stored in dev_priv during
driver init. Use this value instead of reading the register again as the
power well for PORTA RCOMP register may not be enabled and will return
0x instead of the computed value.
Cc: Ville Syrjälä
From: Clint Taylor
The Analogix 7737 DP to HDMI converter requires reduced N and M values when
to operate correctly at HBR2. Detect this IC by its OUI value of 0x0022B9.
Cc: Jani Nikula
Cc: Dhinakaran Pandiyan
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/i915_drv.h | 3 ++-
dr
From: Clint Taylor
Setting the SCDC scrambling CTS mode causes HDMI Link Layer protocol tests
HF1-12 and HF1-13 to fail. Added "Source Shall" entries from SCDC
section before enabling scrambling.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107895
Bugzilla: https://bugs.freedesktop.org
From: Clint Taylor
HDMI 2.0 594Mhz modes were incorrectly selecting 25.200Mhz Automatic N
value mode instead of HDMI specification values.
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/intel_audio.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i9
From: Clint Taylor
Setting the SCDC scrambling CTS mode causes HDMI Link Layer protocol tests
HF1-12 and HF1-13 to fail.
V2: Removed "Source Shall" entries to a new patch
Cc: Ville Syrjälä
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107895
Bugzilla: https://bugs.freedesktop.org/show_
From: Clint Taylor
Initialize SCDC Source Version and TDMS_Config_0 registers to nominal
values during intel_hdmi_detect(). The i915 driver currently doesn't
implement features that require polling of the status update bits. Once
FRL, DSC, or Source Test is enabled in the driver the status flags
From: Clint Taylor
HDMI 2.0 monitors may not support SCDC and still be able to accept VICs
above 63. Use multiple EDID capbilities to determine if the SINK is
actually an HDMI 2.0 device. The QD980B HDMI 2.0 Analyzer generates unique
EDIDs during CTS tests that don't contain a HDMI Forum VSDB if
From: Clint Taylor
HDMI 2.0 monitors may not support SCDC and still be able to accept VICs
above 63. Use multiple EDID capbilities to determine if the SINK is
actually an HDMI 2.0 device. The QD980B HDMI 2.0 Analyzer generates unique
EDIDs during CTS tests that don't contain a HDMI Forum VSDB if
From: Clint Taylor
On GLK NUC platforms the HDMI retiming buffer needs additional disabled
time to correctly sync to a faster incoming signal.
When measured on a scope the highspeed lines of the HDMI clock turn off
for ~400uS during a normal resolution change. The HDMI retimer on the
GLK NUC a
From: Clint Taylor
On GLK NUC platforms the HDMI retiming buffer needs additional disabled
time to correctly sync to a faster incoming signal.
When measured on a scope the highspeed lines of the HDMI clock turn off
for ~400uS during a normal resolution change. The HDMI retimer on the
GLK NUC a
From: Clint Taylor
In commit dc911f5bd8aa ("drm/i915/edp: Allow alternate fixed mode for eDP
if available."), the patch was always selecting the alternate refresh rate
even though user space was asking for the higher rate. This patch adds a
check for vrefresh rate as well as the rest of the mode
From: Clint Taylor
In commit dc911f5bd8aa ("drm/i915/edp: Allow alternate fixed mode for eDP
if available."), the patch was always selecting the alternate refresh rate
even though user space was asking for the higher rate. This patch adds a
check for vrefresh rate as well as the rest of the mode
From: Clint Taylor
On GLK NUC platforms the HDMI retiming buffer needs additional disabled
time to correctly sync to a faster incoming signal.
When measured on a scope the highspeed lines of the HDMI clock turn off
for ~400uS during a normal resolution change. The HDMI retimer on the
GLK NUC a
From: Clint Taylor
On GLK NUC platforms the HDMI retiming buffer needs additional disabled
time to correctly sync to a faster incoming signal.
When measured on a scope the highspeed lines of the HDMI clock turn off
for ~400uS during a normal resolution change. The HDMI retimer on the
GLK NUC a
From: Clint Taylor
Add IS_BROXTON() to the HAS_PSR() MACRO. Tested with a Sharp 2560x1440
panel that claims PSR is enable and in progress.
v2:rebase to latest nightly
CC: Imre Deak
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/i915_drv.h |3 ++-
1 file changed, 2 insertions(+), 1
From: Clint Taylor
Add SKL and KBL cdclk changes during modeset. Taking into account new
linkrates available using 8640 VCO.
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/intel_display.c | 68 ++
1 file changed, 68 insertions(+)
diff --git a/drivers/gp
From: Clint Taylor
Track VCO frequency of SKL instead of the boot CDCLK and allow modeset
to set cdclk based on the max required pixel clock based on VCO
selected.
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/i915_drv.h |2 +-
drivers/gpu/drm/i915/intel_ddi.c |2 +-
dr
From: Clint Taylor
Track VCO frequency of SKL instead of the boot CDCLK and allow modeset
to set cdclk based on the max required pixel clock based on VCO
selected.
The vco should be tracked at the atomic level and all CRTCs updated if
the required vco is changed. At this time the eDP pll is conf
From: Clint Taylor
Track VCO frequency of SKL instead of the boot CDCLK and allow modeset
to set cdclk based on the max required pixel clock based on VCO
selected.
The vco should be tracked at the atomic level and all CRTCs updated if
the required vco is changed. At this time the eDP pll is conf
From: Clint Taylor
Set cdclk based on the max required pixel clock based on VCO
selected. Track boot vco instead of boot cdclk.
The vco is now tracked at the atomic level and all CRTCs updated if
the required vco is changed. Not tested with eDP v1.4 panels that
require 8640 vco due to availabili
From: Clint Taylor
Set cdclk based on the max required pixel clock based on VCO
selected. Track boot vco instead of boot cdclk.
The vco is now tracked at the atomic level and all CRTCs updated if
the required vco is changed. Not tested with eDP v1.4 panels that
require 8640 vco due to availabili
From: Clint Taylor
Set cdclk based on the max required pixel clock based on VCO
selected. Track boot vco instead of boot cdclk.
The vco is now tracked at the atomic level and all CRTCs updated if
the required vco is changed. Not tested with eDP v1.4 panels that
require 8640 vco due to availabili
From: Clint Taylor
WARNING: Using ChromeOS with an eDP panel and a 4K@60 DP monitor connected
to DDI1 the system will hard hang during a cold boot. Occurs when DDI1
is enabled when the cdclk is less then required. DP connected to DDI2
and HPD on either port works correctly.
Set cdclk based on th
From: Clint Taylor
WARNING: Using ChromeOS with an eDP panel and a 4K@60 DP monitor connected
to DDI1 the system will hard hang during a cold boot. Occurs when DDI1
is enabled when the cdclk is less then required. DP connected to DDI2
and HPD on either port works correctly.
Set cdclk based on th
From: Clint Taylor
WARNING: Using ChromeOS with an eDP panel and a 4K@60 DP monitor connected
to DDI1 the system will hard hang during a cold boot. Occurs when DDI1
is enabled when the cdclk is less then required. DP connected to DDI2
and HPD on either port works correctly.
Set cdclk based on th
From: Clint Taylor
WARNING: Using ChromeOS with an eDP panel and a 4K@60 DP monitor connected
to DDI1 the system will hard hang during a cold boot. Occurs when DDI1
is enabled when the cdclk is less then required. DP connected to DDI2
and HPD on either port works correctly.
Set cdclk based on th
From: Clint Taylor
Add IS_BROXTON() to the HAS_PSR() MACRO. Tested with a Sharp 2560x1440
panel that claims PSR is enable and in progress.
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/i915_drv.h |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i9
From: Clint Taylor
The TMDS_296M define was computing as 296704 but the mode->clock is
296700 as defined by EDID. Adjusted define to allow correct detection
of the need to program the correct N value for 29.97 and 23.98 refresh
rate.
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/intel_a
From: Clint Taylor
Add reboot notifier for all platforms. This guarantees T12 delay
compliance during reboot cycles when pre-os enables the panel within
500ms.
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/intel_dp.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
d
From: Clint Taylor
RGB565 Pixel format planes can now be rotated at 90 and 270 degrees
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/intel_atomic_plane.c | 11 ---
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c
b/drivers/
From: Clint Taylor
DDIA Lane capability control 4 lane bit is not being set by firmware during
clone mode boot. This occurs when multiple monitors are connected during
boot. The driver will configure the port for 2 lane maximum width if this
bit is not set.
Once DDIA/E lane split is supported in
From: Clint Taylor
DisplayPort Phy compliance test patterns register definitions.
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/i915_reg.h | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 95a2
From: Clint Taylor
Current 50ms max threshold timing for an EDID read is very close to the
actual time for a 2 block HDMI EDID read of 48ms. Any delay like a clock
stretch by the EDID eeprom will cause this test to fail. A 4 block HDMI
EDID read takes approximately 88ms under nominal conditions,
From: Clint Taylor
Current 50ms max threshold timing for an EDID read is very close to the
actual time for a 2 block HDMI EDID read. Adjust the timings base on
connector type as DP reads are at 1 MBit and HDMI at 100K bit. If an LSPcon
is connected to device under test the -l option should be pas
From: Clint Taylor
Current 50ms max threshold timing for an EDID read is very close to the
actual time for a 2 block HDMI EDID read. Adjust the timings base on
connector type as DP reads are at 1 MBit and HDMI at 100K bit. If an LSPcon
is connected to device under test the -l option should be pas
From: Clint Taylor
Current 50ms max threshold timing for an EDID read is very close to the
actual time for a 2 block HDMI EDID read. Adjust the timings base on
connector type as DP reads are at 1 MBit and HDMI at 100K bit. If an LSPcon
is connected to device under test the -l option should be pas
From: Clint Taylor
Several major vendor USB-C->HDMI converters fail to recover a 5.4 GHz 1 lane
signal if the Data Link N is greater than 0x8.
Patch detects when 1 lane 5.4 GHz signal is being used and makes the maximum
value 20 bit instead of the maximum specification supported 24 bit value.
From: Clint Taylor
Several major vendor USB-C->HDMI converters fail to recover a 5.4 GHz 1 lane
signal if the Data Link N is greater than 0x8.
Patch detects when 1 lane 5.4 GHz signal is being used and makes the maximum
value 20 bit instead of the maximum specification supported 24 bit value.
From: Clint Taylor
P010 is a planar 4:2:0 YUV with interleaved UV plane, 10 bits per
channel video format.
P012 is a planar 4:2:0 YUV 12 bits per channel
P016 is a planar 4:2:0 YUV with interleaved UV plane, 16 bits per
channel video format.
V3: Added P012 and fixed cpp for P010
V4: format def
From: Clint Taylor
The .disable_display parameter was causing a fatal crash when fbdev was
dereferenced during driver init.
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/i915_drv.c |4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c
From: Clint Taylor
The .disable_display parameter was causing a fatal crash when fbdev
was dereferenced during driver init.
V1: protection in i915_drv.c
V2: Moved protection to intel_fbdev.c
Cc: Chris Wilson
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/intel_fbdev.c |3 +++
1 fi
From: Clint Taylor
The panel power sequencer on vlv doesn't appear to accept changes to its T12
power down duration during warm reboots. This change forces a delay for warm
reboots to the T12 panel timing as defined in the VBT table for the connected
panel.
Signed-off-by: Clint Taylor
---
d
From: Clint Taylor
The panel power sequencer on vlv doesn't appear to accept changes to its T12
power down duration during warm reboots. This change forces a delay for warm
reboots to the T12 panel timing as defined in the VBT table for the connected
panel.
Ver2: removed redundant pr_crit(),
From: Clint Taylor
The panel power sequencer on vlv doesn't appear to accept changes to its
T12 power down duration during warm reboots. This change forces a delay
for warm reboots to the T12 panel timing as defined in the VBT table for
the connected panel.
Ver2: removed redundant pr_crit(), com
From: Clint Taylor
The panel power sequencer on vlv doesn't appear to accept changes to its
T12 power down duration during warm reboots. This change forces a delay
for warm reboots to the T12 panel timing as defined in the VBT table for
the connected panel.
Ver2: removed redundant pr_crit(), com
From: Clint Taylor
Remove OUI read function from the lower half interrupt handler. Upon
closing the eDP panel lid an HPD interrupt is generated. The lower half
handler calls intel_dp_probe_oui() as part of intel_dp_detect().
intel_dp_probe_oui() enables eDP VDD and subsequently disables eDP VDD
c
From: Clint Taylor
Latest version of the "CHV DPIO programming notes" no longer requires writes
to TX DW 11 to fix a +2UI interpair skew issue. The current code from
April 2014 was actually causing additional skew issues between all
TMDS pairs.
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i
From: Clint Taylor
Latest version of the "CHV DPIO programming notes" no longer requires writes
to TX DW 11 to fix a +2UI interpair skew issue. The current code from
April 2014 was actually causing additional skew issues between all
TMDS pairs.
ver2: added same treatment to intel_dp.c based on V
From: Clint Taylor
CHV infoframes were not being enabled.
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/intel_hdmi.c |7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index ec87333..3abc200 100644
--- a/d
From: Clint Taylor
Added PIPE C register support for CHV audio programming.
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/i915_reg.h | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.
From: Clint Taylor
The panel power sequencer on vlv doesn't appear to accept changes to its
T12 power down duration during warm reboots. This change forces a delay
for warm reboots to the T12 panel timing as defined in the VBT table for
the connected panel.
Ver2: removed redundant pr_crit(), com
From: Jesse Barnes
Signed-off-by: Jesse Barnes
Signed-off-by: Wayne Boyer
Change-Id: I0838b7c84f1913e1026ad98b8b2e79eb133d17e3
Reviewed-on: https://chromium-review.googlesource.com/192468
Reviewed-by: Stéphane Marchesin
Reviewed-by: Aaron Durbin
Tested-by: Wayne Boyer
Commit-Queue: Wayne Bo
From: Clint Taylor
Upstreaming Chromium backlight related patches which including minimum duty
cycle and 0..max_brightness scaling of the sysfs requested brightness level.
Ben Widawsky (5):
CHROMIUM: drm/i915/vlv: Initialize pipe B backlight to A's value
CHROMIUM: drm/i915: Provide valleyv
From: Ben Widawsky
On VLV specifically, going too low runs the risk of getting the BLC_EN
signal out of sync, preventing resume from working correctly. Scale
/sys/class/backlight at this level to prevent userspace from doing this
on suspend.
This gets rid of the explicitly hardcoded value for a
From: Ben Widawsky
This patch enables the VBT to override the PWM left in the BLC register,
or correct for VBIOS which doesn't program the BLC, with a VBT entry.
It kills the long hardcoded VLV_DEFAULT_BACKLIGHT_MOD_FREQ
As of the last patch, we always will have a default VBT value provided
in
From: Jesse Barnes
Needed for spec compliance
Signed-off-by: Jesse Barnes
Signed-off-by: Wayne Boyer
Change-Id: Ib09f64bdc44108c13bbe5a6ab8ab2f536360f8d2
Reviewed-on: https://chromium-review.googlesource.com/192469
Reviewed-by: Stéphane Marchesin
Reviewed-by: Aaron Durbin
Tested-by: Wayne B
From: Jesse Barnes
Per eDP spec, we must disable the backlight in order to power down the
panel. However, in our code, we have always disabled the backlight
before we try to turn off the panel. The assertions from the previous
patch make sure this is the case.
Signed-off-by: Jesse Barnes
Signed
From: Jesse Barnes
Signed-off-by: Jesse Barnes
Signed-off-by: Wayne Boyer
BUG=chrome-os-partner:25159
TEST=suspend/resume test on instrumented system shows correct signaling
on oscope.
Conflicts:
drivers/gpu/drm/i915/intel_dp.c
Change-Id: Id736d39da630cdfb045b293772f5594576660c12
Rev
From: Ben Widawsky
Not sure if this is needed or not. The code still falls back to a
potentially bad value if PIPE_A was not set.
Signed-off-by: Ben Widawsky
Signed-off-by: Wayne Boyer
Change-Id: I54eb5d4d9fd93e86878c9fa1daec19bdb6b3bd0b
Reviewed-on: https://chromium-review.googlesource.com/1
From: Jani Nikula
We don't actually do anything with the information yet, but parse and
log what's in the VBT.
Signed-off-by: Jani Nikula
Signed-off-by: Rodrigo Vivi
Reviewed-by: Rodrigo Vivi
Signed-off-by: Daniel Vetter
(cherry picked from commit f00076d2fd3fe25b2e8c83921818914dee37ffef)
S
From: Kevin Strasser
Misplaced paren causing test to always fail.
BUG=chrome-os-partner:27096,chrome-os-partner:28914
TEST=Manual: Check that the screen immediately goes black at
minimum brightness.
Change-Id: If9d813ab4ef8cfd9c90f2183f1bb674172bdffe9
Signed-off-by: Kevin Strasser
Reviewed-on:
From: Ben Widawsky
The fallback values for VLV reflect the Rambi3 panel values.
This patch introduces min_brightness member, which defined a part of VBT
that has some confusion. The field itself is a byte ranging from 0-255.
How this value is supposed to be used by the driver is unclear. Though
From: Ben Widawsky
The new assertion code mandates that backlight should be disabled.
Since we've just bent over backwards over the last few patches to make
sure we don't program a 0 into duty cycle, we need some additional
checks to see if the panel is on. This can easily be accomplished by
chec
From: Clint Taylor
CEA SD interlaced modes use a horizontal 720 pixels that are pixel replicated
to 1440. The current driver reports 1440 pixel to the OS and does not set pixel
replicated modes.
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/drm_edid.c| 68 ++--
From: Clint Taylor
Intel HDMI does not correctly configure pixel replicated HDMI modes
480i and 576i. Remove support for these modes until DRM has been
changed to correctly identify SD interlaced modes by reporting there
true horizontal resolution 720 instead of the pre-pixel doubled 1440.
Signe
From: Clint Taylor
Pixel replicated modes should be 720 horizontal pixel and pixel
replicated by the HW across the HDMI cable at 2X pixel clock. Current
horizontal resolution of 1440 does not allow pixel duplication to
occur and scaling artifacts occur on the TV. HDMI certification
7-26 currently
From: Clint Taylor
To reduce eDP T3 time check for digital port connected instead of
msleep. Maintain VBT time if HPD is not asserted on the port.
Current eDP T3 time is an msleep for the panel_power_up time specified
in VBT. The eDP specification allows maximum T3 time of 200ms.
Typically panel
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