Re: [RFC 00/13] virtio-iommu on non-devicetree platforms

2019-12-03 Thread Jacob Pan (Jun)
Hi Jean, Sorry for the delay, I was out last week. Comments inline below. On Mon, 25 Nov 2019 19:02:47 +0100 Jean-Philippe Brucker wrote: > On Fri, Nov 22, 2019 at 04:01:02PM -0800, Jacob Pan (Jun) wrote: > > > (1) ACPI has one table per vendor (DMAR for Intel, IVRS for AMD > > > and IORT for

Re: kernel BUG at drivers/iommu/intel-iommu.c:667!

2019-12-03 Thread Lu Baolu
Hi, On 12/4/19 3:22 AM, AM wrote: Hi Lu Baolu, I tried kernel 4.18.0-147.6.el8.x86_64+debug and used the following API sequence for mapping multiple hugepages: get_user_pages_fast() sg_alloc_table_from_pages() // also tried sg_alloc_table() w/ sg_set_page() using 1GB size for each entry

Re: [PATCH 0/5] iommu/vt-d: Consolidate various cache flush ops

2019-12-03 Thread Lu Baolu
Hi Jacob, On 12/4/19 12:50 AM, Jacob Pan wrote: On Tue, 3 Dec 2019 10:44:45 +0800 Lu Baolu wrote: Hi Jacob, On 12/3/19 4:02 AM, Jacob Pan wrote: On Fri, 22 Nov 2019 11:04:44 +0800 Lu Baolu wrote: Intel VT-d 3.0 introduces more caches and interfaces for software to flush when it runs

Re: [PATCH 0/5] iommu/vt-d: Consolidate various cache flush ops

2019-12-03 Thread Lu Baolu
Hi David, On 12/3/19 4:49 PM, David Woodhouse wrote: On Fri, 2019-11-22 at 11:04 +0800, Lu Baolu wrote: Intel VT-d 3.0 introduces more caches and interfaces for software to flush when it runs in the scalable mode. Currently various cache flush helpers are scattered around. This consolidates

Re: dmar pte read access not set error messages on hp dl388 gen8 systems

2019-12-03 Thread Lu Baolu
Hi, On 12/3/19 5:56 PM, Jerry Snitselaar wrote: On Tue Dec 03 19, Lu Baolu wrote: Hi, On 12/3/19 12:13 AM, Jerry Snitselaar wrote: On Mon Dec 02 19, Jerry Snitselaar wrote: On Mon Dec 02 19, Lu Baolu wrote: Hi, On 12/2/19 2:34 PM, Jerry Snitselaar wrote: We are seeing DMAR PTE read

Re: [Patch v2 2/3] iommu: optimize iova_magazine_free_pfns()

2019-12-03 Thread Cong Wang
On Mon, Dec 2, 2019 at 2:02 AM John Garry wrote: > > On 30/11/2019 06:02, Cong Wang wrote: > > On Fri, Nov 29, 2019 at 5:24 AM John Garry wrote: > >> > >> On 29/11/2019 00:48, Cong Wang wrote: > >>> If the maganize is empty, iova_magazine_free_pfns() should > >> > >> magazine > > > > Good catch!

Re: [Patch v2 2/3] iommu: optimize iova_magazine_free_pfns()

2019-12-03 Thread Cong Wang
On Mon, Dec 2, 2019 at 8:59 AM Christoph Hellwig wrote: > > > + return (mag && mag->size == IOVA_MAG_SIZE); > > > + return (!mag || mag->size == 0); > > No need for the braces in both cases. The current code is already this, I don't want to mix coding style changes with a

Re: [Patch v2 1/3] iommu: match the original algorithm

2019-12-03 Thread Cong Wang
On Mon, Dec 2, 2019 at 2:55 AM John Garry wrote: > Apart from this change, did anyone ever consider kmem cache for the > magazines? You can always make any changes you want after this patch, I can't do all optimizations in one single patch. :) So, I will leave this to you. Thanks.

Re: [Patch v2 1/3] iommu: match the original algorithm

2019-12-03 Thread Cong Wang
On Mon, Dec 2, 2019 at 8:58 AM Christoph Hellwig wrote: > > I think a subject line better describes what you change, no that > it matches an original algorithm. The fact that the fix matches > the original algorithm can go somewhere towards the commit log, > preferably with a reference to the

Re: kernel BUG at drivers/iommu/intel-iommu.c:667!

2019-12-03 Thread AM
Hi Lu Baolu, I tried kernel 4.18.0-147.6.el8.x86_64+debug and used the following API sequence for mapping multiple hugepages: get_user_pages_fast() sg_alloc_table_from_pages() // also tried sg_alloc_table() w/ sg_set_page() using 1GB size for each entry dma_map_sg() I'm able to DMA upto 1GB

Re: [PATCH v2 1/8] dt-bindings: arm-smmu: Add Adreno GPU variant

2019-12-03 Thread Rob Herring
On Fri, Nov 22, 2019 at 11:31:51PM +, Jordan Crouse wrote: > Add a compatible string to identify SMMUs that are attached > to Adreno GPU devices that wish to support split pagetables. > > Signed-off-by: Jordan Crouse > --- > > Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 6

Re: [PATCH v5 8/8] iommu/vt-d: Misc macro clean up for SVM

2019-12-03 Thread Jacob Pan
On Mon, 02 Dec 2019 12:10:45 -0800 Joe Perches wrote: > On Mon, 2019-12-02 at 11:58 -0800, Jacob Pan wrote: > > Use combined macros for_each_svm_dev() to simplify SVM device > > iteration and error checking. > [] > > diff --git a/drivers/iommu/intel-svm.c b/drivers/iommu/intel-svm.c > [] > >

Re: [PATCH 4/5] iommu/vt-d: Consolidate pasid-based tlb invalidation

2019-12-03 Thread Jacob Pan
On Fri, 22 Nov 2019 11:04:48 +0800 Lu Baolu wrote: > Merge pasid-based tlb invalidation into iommu->flush.p_iotlb_inv. > > Signed-off-by: Lu Baolu > --- > drivers/iommu/intel-iommu.c | 43 > + drivers/iommu/intel-pasid.c | > 18 ++--

Re: [PATCH v4 7/8] linux/log2.h: Fix 64bit calculations in roundup/down_pow_two()

2019-12-03 Thread Chuck Lever
> On Dec 3, 2019, at 6:47 AM, Nicolas Saenz Julienne > wrote: > > Some users need to make sure their rounding function accepts and returns > 64bit long variables regardless of the architecture. Sadly > roundup/rounddown_pow_two() takes and returns unsigned longs. It turns > out ilog2()

Re: [PATCH 0/5] iommu/vt-d: Consolidate various cache flush ops

2019-12-03 Thread Jacob Pan
On Tue, 3 Dec 2019 10:44:45 +0800 Lu Baolu wrote: > Hi Jacob, > > On 12/3/19 4:02 AM, Jacob Pan wrote: > > On Fri, 22 Nov 2019 11:04:44 +0800 > > Lu Baolu wrote: > > > >> Intel VT-d 3.0 introduces more caches and interfaces for software > >> to flush when it runs in the scalable mode.

Re: [PATCH v4 8/8] linux/log2.h: Use roundup/dow_pow_two() on 64bit calculations

2019-12-03 Thread Nicolas Saenz Julienne
Hi Rob, On Tue, 2019-12-03 at 09:53 -0600, Rob Herring wrote: > On Tue, Dec 3, 2019 at 5:48 AM Nicolas Saenz Julienne > wrote: > > The function now is safe to use while expecting a 64bit value. Use it > > where relevant. > > What was wrong with the existing code? This is missing some context.

Re: [PATCH v4 8/8] linux/log2.h: Use roundup/dow_pow_two() on 64bit calculations

2019-12-03 Thread Rob Herring
On Tue, Dec 3, 2019 at 5:48 AM Nicolas Saenz Julienne wrote: > > The function now is safe to use while expecting a 64bit value. Use it > where relevant. What was wrong with the existing code? This is missing some context. > Signed-off-by: Nicolas Saenz Julienne > --- >

[PATCH v6 3/3] PCI: Add DMA alias quirk for PLX PEX NTB

2019-12-03 Thread James Sewart via iommu
The PLX PEX NTB forwards DMA transactions using Requester ID's that don't exist as PCI devices. The devfn for a transaction is used as an index into a lookup table storing the origin of a transaction on the other side of the bridge. This patch aliases all possible devfn's to the NTB device so

[PATCH v6 2/3] PCI: Add parameter nr_devfns to pci_add_dma_alias

2019-12-03 Thread James Sewart via iommu
pci_add_dma_alias can now be used to create a dma alias for a range of devfns. Reviewed-by: Logan Gunthorpe Signed-off-by: James Sewart --- drivers/pci/pci.c| 22 +- drivers/pci/quirks.c | 14 +++--- include/linux/pci.h | 2 +- 3 files changed, 25

[PATCH v6 1/3] PCI: Fix off by one in dma_alias_mask allocation size

2019-12-03 Thread James Sewart via iommu
The number of possible devfns is 256, add def and correct uses. Reviewed-by: Logan Gunthorpe Signed-off-by: James Sewart --- drivers/pci/pci.c| 2 +- drivers/pci/search.c | 2 +- include/linux/pci.h | 2 ++ 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/pci/pci.c

[PATCH v4 0/8] Raspberry Pi 4 PCIe support

2019-12-03 Thread Nicolas Saenz Julienne
This series aims at providing support for Raspberry Pi 4's PCIe controller, which is also shared with the Broadcom STB family of devices. There was a previous attempt to upstream this some years ago[1] but was blocked as most STB PCIe integrations have a sparse DMA mapping[2] which is something

[PATCH v4 7/8] linux/log2.h: Fix 64bit calculations in roundup/down_pow_two()

2019-12-03 Thread Nicolas Saenz Julienne
Some users need to make sure their rounding function accepts and returns 64bit long variables regardless of the architecture. Sadly roundup/rounddown_pow_two() takes and returns unsigned longs. It turns out ilog2() already handles 32/64bit calculations properly, and being the building block to the

[PATCH v4 8/8] linux/log2.h: Use roundup/dow_pow_two() on 64bit calculations

2019-12-03 Thread Nicolas Saenz Julienne
The function now is safe to use while expecting a 64bit value. Use it where relevant. Signed-off-by: Nicolas Saenz Julienne --- drivers/acpi/arm64/iort.c| 2 +- drivers/net/ethernet/mellanox/mlx4/en_clock.c| 3 ++- drivers/of/device.c | 3

Re: dmar pte read access not set error messages on hp dl388 gen8 systems

2019-12-03 Thread Jerry Snitselaar
On Tue Dec 03 19, Lu Baolu wrote: Hi, On 12/3/19 12:13 AM, Jerry Snitselaar wrote: On Mon Dec 02 19, Jerry Snitselaar wrote: On Mon Dec 02 19, Lu Baolu wrote: Hi, On 12/2/19 2:34 PM, Jerry Snitselaar wrote: We are seeing DMAR PTE read access not set errors when booting a kernel with

Re: [PATCH 0/5] iommu/vt-d: Consolidate various cache flush ops

2019-12-03 Thread David Woodhouse
On Fri, 2019-11-22 at 11:04 +0800, Lu Baolu wrote: > Intel VT-d 3.0 introduces more caches and interfaces for software to > flush when it runs in the scalable mode. Currently various cache flush > helpers are scattered around. This consolidates them by putting them in > the existing iommu_flush