Re: [PATCH v4 13/24] iommu/mediatek: Add device link for smi-common and m4u

On Thu, 2020-11-12 at 09:10 +0800, Nicolas Boichat wrote: > On Wed, Nov 11, 2020 at 8:40 PM Yong Wu wrote: > > > > In the lastest SoC, M4U has its special power domain. thus, If the engine > > begin to work, it should help enable the power for M4U firstly. > > Currently if the engine work, it alwa

Re: [PATCH v4 05/24] dt-bindings: mediatek: Add binding for mt8192 IOMMU

Hi Krzysztof, On Wed, 2020-11-11 at 22:33 +0100, Krzysztof Kozlowski wrote: > On Wed, Nov 11, 2020 at 08:38:19PM +0800, Yong Wu wrote: > > This patch adds decriptions for mt8192 IOMMU and SMI. > > > > mt8192 also is MTK IOMMU gen2 which uses ARM Short-Descriptor translation > > table format. The

Re: [PATCH v6 5/5] vfio/type1: Use mdev bus iommu_ops for IOMMU callbacks

Hi Alex, On 11/3/20 1:22 PM, Lu Baolu wrote: Hi Alex, On 10/31/20 5:06 AM, Alex Williamson wrote: On Fri, 30 Oct 2020 06:16:28 + "Tian, Kevin" wrote: From: Lu Baolu Sent: Friday, October 30, 2020 12:58 PM With the IOMMU driver registering iommu_ops for the mdev_bus, the IOMMU operatio

[PATCH 1/1] vfio/type1: Add subdev_ioasid callback to vfio_iommu_driver_ops

Add API for getting the ioasid of a subdevice (vfio/mdev). This calls into the backend IOMMU module to get the actual value or error number if ioasid for subdevice is not supported. The physical device driver implementations which rely on the vfio/mdev framework for mediated device user level acces

Re: [PATCH v4 13/24] iommu/mediatek: Add device link for smi-common and m4u

On Wed, Nov 11, 2020 at 8:40 PM Yong Wu wrote: > > In the lastest SoC, M4U has its special power domain. thus, If the engine > begin to work, it should help enable the power for M4U firstly. > Currently if the engine work, it always enable the power/clocks for > smi-larbs/smi-common. This patch ad

Re: [PATCH v7 04/24] iommu: Add a page fault handler

Hi Jean, On 2020/11/11 21:57, Jean-Philippe Brucker wrote: Hi Baolu, Thanks for the review. I'm only now reworking this and realized I've never sent a reply, sorry about that. On Wed, May 20, 2020 at 02:42:21PM +0800, Lu Baolu wrote: Hi Jean, On 2020/5/20 1:54, Jean-Philippe Brucker wrote:

[PATCH RESEND 3/5] iommu/tegra-smmu: Use fwspec in tegra_smmu_(de)attach_dev

In tegra_smmu_(de)attach_dev() functions, we poll DTB for each client's iommus property to get swgroup ID in order to prepare "as" and enable smmu. Actually tegra_smmu_configure() prepared an fwspec for each client, and added to the fwspec all swgroup IDs of client DT node in DTB. So this patch us

[PATCH RESEND 4/5] iommu/tegra-smmu: Rework tegra_smmu_probe_device()

The bus_set_iommu() in tegra_smmu_probe() enumerates all clients to call in tegra_smmu_probe_device() where each client searches its DT node for smmu pointer and swgroup ID, so as to configure an fwspec. But this requires a valid smmu pointer even before mc and smmu drivers are probed. So in tegra_

[PATCH RESEND 5/5] iommu/tegra-smmu: Add PCI support

This patch simply adds support for PCI devices. Reviewed-by: Dmitry Osipenko Tested-by: Dmitry Osipenko Signed-off-by: Nicolin Chen --- drivers/iommu/tegra-smmu.c | 35 +-- 1 file changed, 25 insertions(+), 10 deletions(-) diff --git a/drivers/iommu/tegra-smmu.

[PATCH RESEND 1/5] iommu/tegra-smmu: Unwrap tegra_smmu_group_get

The tegra_smmu_group_get was added to group devices in different SWGROUPs and it'd return a NULL group pointer upon a mismatch at tegra_smmu_find_group(), so for most of clients/devices, it very likely would mismatch and need a fallback generic_device_group(). But now tegra_smmu_group_get handles

[PATCH RESEND 0/5] iommu/tegra-smmu: Some pending reviewed changes

This is a merged set of resend for previously two series of patches that were reviewed/acked a month ago yet have not got applied. Series-1: https://lkml.org/lkml/2020/9/29/73 "[PATCH v4 0/2] iommu/tegra-smmu: Two followup changes" Series-2: https://lkml.org/lkml/2020/10/9/808 "[PATCH v7 0/3] iom

[PATCH RESEND 2/5] iommu/tegra-smmu: Expand mutex protection range

This is used to protect potential race condition at use_count. since probes of client drivers, calling attach_dev(), may run concurrently. Reviewed-by: Dmitry Osipenko Tested-by: Dmitry Osipenko Acked-by: Thierry Reding Signed-off-by: Nicolin Chen --- drivers/iommu/tegra-smmu.c | 34 +

Re: [PATCH v4 18/24] iommu/mediatek: Support master use iova over 32bit

On Wed, Nov 11, 2020 at 08:38:32PM +0800, Yong Wu wrote: > After extending v7s, our pagetable already support iova reach > 16GB(34bit). the master got the iova via dma_alloc_attrs may reach > 34bits, but its HW register still is 32bit. then how to set the > bit32/bit33 iova? this depend on a SMI la

Re: [PATCH v4 06/24] iommu/mediatek: Use the common mtk-smi-larb-port.h

On Wed, Nov 11, 2020 at 08:38:20PM +0800, Yong Wu wrote: > Use the common larb-port header in the source code. > > Signed-off-by: Yong Wu > --- > drivers/iommu/mtk_iommu.c | 7 --- > drivers/iommu/mtk_iommu.h | 1 + > drivers/memory/mtk-smi.c | 1 + > include/soc/mediatek/smi.h | 2 -- >

Re: [PATCH v4 05/24] dt-bindings: mediatek: Add binding for mt8192 IOMMU

On Wed, Nov 11, 2020 at 08:38:19PM +0800, Yong Wu wrote: > This patch adds decriptions for mt8192 IOMMU and SMI. > > mt8192 also is MTK IOMMU gen2 which uses ARM Short-Descriptor translation > table format. The M4U-SMI HW diagram is as below: > > EMI >

Re: [PATCH v4 04/24] dt-bindings: memory: mediatek: Add domain definition

On Wed, Nov 11, 2020 at 08:38:18PM +0800, Yong Wu wrote: > In the latest SoC, there are several HW IP require a sepecial iova > range, mainly CCU and VPU has this requirement. Take CCU as a example, > CCU require its iova locate in the range(0x4000_ ~ 0x43ff_). > > In this patch we add a d

Re: [PATCH v4 03/24] dt-bindings: memory: mediatek: Extend LARB_NR_MAX to 32

On Wed, Nov 11, 2020 at 08:38:17PM +0800, Yong Wu wrote: > Extend the max larb number definition as mt8192 has larb_nr over 16. > > Signed-off-by: Yong Wu > Acked-by: Rob Herring > --- > Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml | 2 +- > include/dt-bindings/memory/mtk-smi-lar

Re: [PATCH v4 02/24] dt-bindings: memory: mediatek: Add a common larb-port header file

On Wed, Nov 11, 2020 at 08:38:16PM +0800, Yong Wu wrote: > Put all the macros about smi larb/port togethers, this is a preparing > patch for extending LARB_NR and adding new dom-id support. > > Signed-off-by: Yong Wu > Acked-by: Rob Herring > --- > include/dt-bindings/memory/mt2712-larb-port.h

Re: [PATCH v4 24/24] MAINTAINERS: Add entry for MediaTek IOMMU

Hi Yong: Yong Wu 於 2020年11月11日 週三 下午8:53寫道： > > I am the author of MediaTek iommu driver, and will to maintain and > develop it further. > Add myself to cover these items. Reviewed-by: Chun-Kuang Hu > > Signed-off-by: Yong Wu > --- > MAINTAINERS | 9 + > 1 file changed, 9 insertions(

Re: [PATCH v7 04/24] iommu: Add a page fault handler

Hi Xiang, Thank you for reviewing this. I forgot to send a reply, sorry for the delay. On Fri, May 29, 2020 at 05:18:27PM +0800, Xiang Zheng wrote: > Hi, > > On 2020/5/20 1:54, Jean-Philippe Brucker wrote: > > Some systems allow devices to handle I/O Page Faults in the core mm. For > > example s

Re: [PATCH v7 04/24] iommu: Add a page fault handler

Hi Baolu, Thanks for the review. I'm only now reworking this and realized I've never sent a reply, sorry about that. On Wed, May 20, 2020 at 02:42:21PM +0800, Lu Baolu wrote: > Hi Jean, > > On 2020/5/20 1:54, Jean-Philippe Brucker wrote: > > Some systems allow devices to handle I/O Page Faults i

[PATCH v4 23/24] iommu/mediatek: Add mt8192 support

Add mt8192 iommu support. For multi domain, Add 1M gap for the vdec domain size. That is because vdec HW has a end address register which require (start_addr + len) rather than (start_addr + len - 1). Take a example, if the start_addr is 0xfff0, size is 0x10, then the end_address is 0xfff0

[PATCH v4 24/24] MAINTAINERS: Add entry for MediaTek IOMMU

I am the author of MediaTek iommu driver, and will to maintain and develop it further. Add myself to cover these items. Signed-off-by: Yong Wu --- MAINTAINERS | 9 + 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index e73636b75f29..462a87ee19c8 100644 --- a/MAIN

[PATCH v4 21/24] iommu/mediatek: Add support for multi domain

Some HW IP(ex: CCU) require the special iova range. That means the iova got from dma_alloc_attrs for that devices must locate in his special range. In this patch, we allocate a special iova_range for each a special requirement and create each a iommu domain for each a iova_range. meanwhile we stil

[PATCH v4 22/24] iommu/mediatek: Adjust the structure

Add "struct mtk_iommu_data *" in the "struct mtk_iommu_domain", reduce the call mtk_iommu_get_m4u_data(). No functional change. Signed-off-by: Yong Wu --- drivers/iommu/mtk_iommu.c | 18 ++ 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/drivers/iommu/mtk_iommu.c b

[PATCH v4 13/24] iommu/mediatek: Add device link for smi-common and m4u

In the lastest SoC, M4U has its special power domain. thus, If the engine begin to work, it should help enable the power for M4U firstly. Currently if the engine work, it always enable the power/clocks for smi-larbs/smi-common. This patch adds device_link for smi-common and M4U. then, if smi-common

[PATCH v4 20/24] iommu/mediatek: Support report iova 34bit translation fault in ISR

If the iova is over 32bit, the fault status register bit is a little different. Add a flag for the special register bits. Signed-off-by: Yong Wu --- drivers/iommu/mtk_iommu.c | 17 +++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/mtk_iommu.c b/driver

[PATCH v4 18/24] iommu/mediatek: Support master use iova over 32bit

After extending v7s, our pagetable already support iova reach 16GB(34bit). the master got the iova via dma_alloc_attrs may reach 34bits, but its HW register still is 32bit. then how to set the bit32/bit33 iova? this depend on a SMI larb setting(bank_sel). we separate whole 16GB iova to four banks:

[PATCH v4 14/24] iommu/mediatek: Add pm runtime callback

This patch adds pm runtime callback. In pm runtime case, all the registers backup/restore and bclk are controlled in the pm_runtime callback, then pm_suspend is not needed in this case. runtime PM is disabled when suspend, thus we call pm_runtime_status_suspended instead of pm_runtime_suspended.

[PATCH v4 17/24] iommu/mediatek: Add single domain

Defaultly the iova range is 0-4G. here we add a single-domain(0-4G) for the previous SoC. this also is a preparing patch for supporting multi-domains. Signed-off-by: Yong Wu --- drivers/iommu/mtk_iommu.c | 12 1 file changed, 12 insertions(+) diff --git a/drivers/iommu/mtk_iommu.c

[PATCH v4 16/24] iommu/mediatek: Add iova reserved function

For multiple iommu_domains, we need to reserve some iova regions. Take a example, If the default iova region is 0 ~ 4G, but the 0x4000_ ~ 0x43ff_ is only for the special CCU0 domain. Thus we should exclude this region for the default iova region. This patch adds iova reserved flow. It's a

[PATCH v4 19/24] iommu/mediatek: Support up to 34bit iova in tlb flush

If the iova is 34bit, the iova[32][33] is the bit0/1 in the tlb flush register. Add a new macro for this. there is a minor change unrelated with this patch. it also use the new macro. Signed-off-by: Yong Wu --- drivers/iommu/mtk_iommu.c | 11 +++ 1 file changed, 7 insertions(+), 4 delet

[PATCH v4 15/24] iommu/mediatek: Add power-domain operation

In the previous SoC, the M4U HW is in the EMI power domain which is always on. the latest M4U is in the display power domain which may be turned on/off, thus we have to add pm_runtime interface for it. When the engine work, the engine always enable the power and clocks for smi-larb/smi-common, the

[PATCH v4 08/24] iommu/io-pgtable-arm-v7s: Extend PA34 for MediaTek

MediaTek extend the bit5 in lvl1 and lvl2 descriptor as PA34. Signed-off-by: Yong Wu Acked-by: Will Deacon --- drivers/iommu/io-pgtable-arm-v7s.c | 9 +++-- drivers/iommu/mtk_iommu.c | 2 +- include/linux/io-pgtable.h | 4 ++-- 3 files changed, 10 insertions(+), 5 deletions

[PATCH v4 07/24] iommu/io-pgtable-arm-v7s: Use ias to check the valid iova in unmap

Use the ias for the valid iova checking in arm_v7s_unmap. This is a preparing patch for supporting iova 34bit for MediaTek. Signed-off-by: Yong Wu --- drivers/iommu/io-pgtable-arm-v7s.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/driv

[PATCH v4 12/24] iommu/mediatek: Move hw_init into attach_device

In attach device, it will update the pagetable base address register. Move the hw_init function also here. Then it only need call pm_runtime_get/put one time here if m4u has power domain. Signed-off-by: Yong Wu --- drivers/iommu/mtk_iommu.c | 10 ++ 1 file changed, 6 insertions(+), 4 del

[PATCH v4 09/24] iommu/io-pgtable-arm-v7s: Clear LVL_SHIFT/BITS macro instead of the formula

The current _ARM_V7S_LVL_BITS/ARM_V7S_LVL_SHIFT use a formula to calculate the corresponding value for level1 and level2 to pretend the code sane. Actually their level1 and level2 values are different from each other. This patch only clear the two macro. No functional change. Suggested-by: Robin M

[PATCH v4 10/24] iommu/io-pgtable-arm-v7s: Add cfg as a param in some macros

Add "cfg" as a parameter for some macros. This is a preparing patch for mediatek extend the lvl1 pgtable. No functional change. Signed-off-by: Yong Wu Acked-by: Will Deacon --- drivers/iommu/io-pgtable-arm-v7s.c | 36 +++--- 1 file changed, 18 insertions(+), 18 deletions

[PATCH v4 11/24] iommu/io-pgtable-arm-v7s: Quad lvl1 pgtable for MediaTek

The standard input iova bits is 32. MediaTek quad the lvl1 pagetable (4 * lvl1). No change for lvl2 pagetable. Then the iova bits can reach 34bit. Signed-off-by: Yong Wu --- drivers/iommu/io-pgtable-arm-v7s.c | 7 --- drivers/iommu/mtk_iommu.c | 2 +- 2 files changed, 5 insertions(+

[PATCH v4 03/24] dt-bindings: memory: mediatek: Extend LARB_NR_MAX to 32

Extend the max larb number definition as mt8192 has larb_nr over 16. Signed-off-by: Yong Wu Acked-by: Rob Herring --- Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml | 2 +- include/dt-bindings/memory/mtk-smi-larb-port.h | 4 ++-- 2 files changed, 3 insertions(+), 3 del

[PATCH v4 06/24] iommu/mediatek: Use the common mtk-smi-larb-port.h

Use the common larb-port header in the source code. Signed-off-by: Yong Wu --- drivers/iommu/mtk_iommu.c | 7 --- drivers/iommu/mtk_iommu.h | 1 + drivers/memory/mtk-smi.c | 1 + include/soc/mediatek/smi.h | 2 -- 4 files changed, 2 insertions(+), 9 deletions(-) diff --git a/drivers/iom

[PATCH v4 00/24] MT8192 IOMMU support

This patch mainly adds support for mt8192 Multimedia IOMMU and SMI. mt8192 also is MTK IOMMU gen2 which uses ARM Short-Descriptor translation table format. The M4U-SMI HW diagram is as below: EMI | M4U

[PATCH v4 02/24] dt-bindings: memory: mediatek: Add a common larb-port header file

Put all the macros about smi larb/port togethers, this is a preparing patch for extending LARB_NR and adding new dom-id support. Signed-off-by: Yong Wu Acked-by: Rob Herring --- include/dt-bindings/memory/mt2712-larb-port.h | 2 +- include/dt-bindings/memory/mt6779-larb-port.h | 2 +- inclu

[PATCH v4 01/24] dt-bindings: iommu: mediatek: Convert IOMMU to DT schema

Convert MediaTek IOMMU to DT schema. Signed-off-by: Yong Wu --- .../bindings/iommu/mediatek,iommu.txt | 105 --- .../bindings/iommu/mediatek,iommu.yaml| 167 ++ 2 files changed, 167 insertions(+), 105 deletions(-) delete mode 100644 Documentation/devicetr

[PATCH v4 05/24] dt-bindings: mediatek: Add binding for mt8192 IOMMU

This patch adds decriptions for mt8192 IOMMU and SMI. mt8192 also is MTK IOMMU gen2 which uses ARM Short-Descriptor translation table format. The M4U-SMI HW diagram is as below: EMI | M4U |

[PATCH v4 04/24] dt-bindings: memory: mediatek: Add domain definition

In the latest SoC, there are several HW IP require a sepecial iova range, mainly CCU and VPU has this requirement. Take CCU as a example, CCU require its iova locate in the range(0x4000_ ~ 0x43ff_). In this patch we add a domain definition for the special port. In the example of CCU, If we

RE: [PATCH v3 1/2] dma-mapping: add benchmark support for streaming DMA APIs

> -Original Message- > From: John Garry > Sent: Wednesday, November 11, 2020 10:37 PM > To: Song Bao Hua (Barry Song) ; > iommu@lists.linux-foundation.org; h...@lst.de; robin.mur...@arm.com; > m.szyprow...@samsung.com > Cc: linux-kselft...@vger.kernel.org; Will Deacon ; Joerg > Roedel ;