d-off-by: Nipun Gupta <nipun.gu...@nxp.com>
> ---
> .../devicetree/bindings/misc/fsl,qoriq-mc.txt | 39
> ++
> 1 file changed, 39 insertions(+)
Reviewed-by: Rob Herring <r...@kernel.org>
___
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On Fri, Apr 27, 2018 at 03:57:02PM +0530, Nipun Gupta wrote:
> iommu-map property is also used by devices with fsl-mc. This
> patch moves the of_pci_map_rid to generic location, so that it
> can be used by other busses too.
>
> 'of_pci_map_rid' is renamed here to 'of_map_rid' and there is no
>
On Tue, Apr 10, 2018 at 01:26:41PM +0200, Heiko Stuebner wrote:
> Hi Robin,
>
> Am Dienstag, 10. April 2018, 13:18:48 CEST schrieb Robin Murphy:
> > On 10/04/18 10:26, Heiko Stuebner wrote:
> > > Rockchip IOMMUs are used without explicit clock handling for 4 years
> > > now, so we should keep
/gpu/host1x/bus.c | 5 ++---
> drivers/of/device.c | 6 --
> drivers/of/of_reserved_mem.c | 2 +-
> drivers/pci/pci-driver.c | 3 +--
> include/linux/device.h| 4
> include/linux/of_device.h | 8 ++--
> 10 file
On Fri, Mar 16, 2018 at 8:51 AM, Geert Uytterhoeven
wrote:
> Hi all,
>
> If NO_DMA=y, get_dma_ops() returns a reference to the non-existing
> symbol bad_dma_ops, thus causing a link failure if it is ever used.
>
> The intention of this is twofold:
> 1. To catch
: Magnus Damm <damm+rene...@opensource.se>
> ---
>
> Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt |1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Rob Herring <r...@kernel.org>
___
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On Fri, Mar 23, 2018 at 03:38:09PM +0800, Jeffy Chen wrote:
> Add clock property, since we are going to control clocks in rockchip
> iommu driver.
>
> Signed-off-by: Jeffy Chen <jeffy.c...@rock-chips.com>
> Reviewed-by: Robin Murphy <robin.mur...@arm.com>
> --
On Mon, Mar 05, 2018 at 07:59:21PM +0530, Nipun Gupta wrote:
> The existing IOMMU bindings cannot be used to specify the relationship
> between fsl-mc devices and IOMMUs. This patch adds a binding for
> mapping fsl-mc devices to IOMMUs, using a new iommu-parent property.
>
> Signed-off-by: Nipun
On Wed, Mar 7, 2018 at 12:32 AM, Vivek Gautam
wrote:
> Qualcomm's arm-smmu 500 implementation supports runtime pm
> so enable the same.
That's a driver detail unrelated to the binding.
>
> Signed-off-by: Vivek Gautam
> ---
>
> Based on
ent number of clocks before.
> Changes in v5: None
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
>
> Documentation/devicetree/bindings/iommu/rockchip,iommu.txt | 7 +++
> 1 file changed, 7 insertio
vmsa.txt | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Rob Herring <r...@kernel.org>
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> +
> +- pasid-bits: Some masters support multiple address spaces for DMA, by
> + tagging DMA transactions with an address space identifier. By default,
> + this is 0, which means that the device only has one address space.
So 3 would mean 8 address spaces?
Maybe pasid-num-bits would
On Wed, Jan 31, 2018 at 1:52 AM, Tomasz Figa <tf...@chromium.org> wrote:
> Hi Rob,
>
> On Wed, Jan 31, 2018 at 2:05 AM, Rob Herring <r...@kernel.org> wrote:
>> On Wed, Jan 24, 2018 at 06:35:11PM +0800, Jeffy Chen wrote:
>>> From: Tomasz Figa <tf...@ch
On Wed, Jan 24, 2018 at 06:35:11PM +0800, Jeffy Chen wrote:
> From: Tomasz Figa
>
> Current code relies on master driver enabling necessary clocks before
> IOMMU is accessed, however there are cases when the IOMMU should be
> accessed while the master is not running yet, for
gned-off-by: Vivek Gautam <vivek.gau...@codeaurora.org>
> ---
> .../devicetree/bindings/iommu/arm,smmu.txt | 43
> ++
> drivers/iommu/arm-smmu.c | 13 +++
> 2 files changed, 56 insertions(+)
Re
On Tue, Jan 09, 2018 at 03:31:48PM +0530, Vivek Gautam wrote:
> qcom,smmu-v2 is an arm,smmu-v2 implementation with specific
> clock and power requirements. This smmu core is used with
> multiple masters on msm8996, viz. mdss, video, etc.
> Add bindings for the same.
>
> Signed-off-by: Vivek
On Mon, Oct 16, 2017 at 5:23 AM, Jean-Philippe Brucker
<jean-philippe.bruc...@arm.com> wrote:
> On 13/10/17 20:10, Rob Herring wrote:
>> On Fri, Oct 06, 2017 at 02:31:39PM +0100, Jean-Philippe Brucker wrote:
>>> On ARM systems, some platform devices behind an IOMMU may sup
On Fri, Oct 06, 2017 at 02:31:39PM +0100, Jean-Philippe Brucker wrote:
> On ARM systems, some platform devices behind an IOMMU may support stall
> and PASID features. Stall is the ability to recover from page faults and
> PASID offers multiple process address spaces to the device. Together they
>
On Wed, Oct 04, 2017 at 02:33:08PM +0200, Geert Uytterhoeven wrote:
> Use the preferred generic node name in the example.
>
> Signed-off-by: Geert Uytterhoeven
> ---
> Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt | 2 +-
> 1 file changed, 1
mentation/devicetree/bindings/iommu/arm,smmu-v3.txt | 9 -
> 2 files changed, 9 insertions(+), 1 deletion(-)
Acked-by: Rob Herring <r...@kernel.org>
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: Magnus Damm <damm+rene...@opensource.se>
> ---
>
> Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt |1 +
> 1 file changed, 1 insertion(+)
Acked-by: Rob Herring <r...@kernel.org>
___
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: Magnus Damm <damm+rene...@opensource.se>
> ---
>
> Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt |1 +
> 1 file changed, 1 insertion(+)
Acked-by: Rob Herring <r...@kernel.org>
___
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On Thu, Sep 14, 2017 at 01:57:52PM +0100, Shameer Kolothum wrote:
> From: John Garry
>
> The HiSilicon erratum 161010801 describes the limitation of HiSilicon
> platforms
> hip06/hip07 to support the SMMU mappings for MSI transactions.
>
> On these platforms, GICv3 ITS
On Tue, Sep 12, 2017 at 05:31:07PM +0530, Vivek Gautam wrote:
> ARM MMU-500 implements a TBU (uTLB) for each connected master
> besides a single TCU which controls and manages the address
> translations. Each of these TBUs can either be in the same
> power domain as the master, or they can have a
are HW fixed, SW can NOT adjust it.
>
> Signed-off-by: Yong Wu <yong...@mediatek.com>
> ---
> Hi Rob,
> Comparing with the v1, I add larb8 and larb9 in this version.
> So I don't add your ACK here.
Thanks for the explanation. That's minor enough you could have kept it.
Acked
++
> 4 files changed, 102 insertions(+), 6 deletions(-)
> create mode 100644 include/dt-bindings/memory/mt2712-larb-port.h
Acked-by: Rob Herring <r...@kernel.org>
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Now that we have a custom printf format specifier, convert users of
full_name to use %pOF instead. This is preparation to remove storing
of the full path string for each node.
Signed-off-by: Rob Herring <r...@kernel.org>
Cc: Joerg Roedel <j...@8bytes.org>
Cc: Heiko Stuebner <he..
On Thu, Jul 06, 2017 at 03:07:05PM +0530, Vivek Gautam wrote:
> qcom,msm8996-smmu-v2 is an arm,smmu-v2 implementation with
> specific clock and power requirements. This smmu core is used
> with multiple masters on msm8996, viz. mdss, video, etc.
> Add bindings for the same.
>
> Signed-off-by:
On Thu, Jul 06, 2017 at 03:07:04PM +0530, Vivek Gautam wrote:
> From: Sricharan R
>
> The MMU400x/500 is the implementation of the SMMUv2
> arch specification. It is split in to two blocks
> TBU, TCU. TBU caches the page table, instantiated
> for each master locally,
On Thu, Jun 01, 2017 at 01:28:01PM +0100, Jean-Philippe Brucker wrote:
> On 31/05/17 18:23, Rob Herring wrote:
> > On Wed, May 24, 2017 at 07:01:38PM +0100, Jean-Philippe Brucker wrote:
> >> Address Translation Service (ATS) is an extension to PCIe allowing
> >> endpoint
On Wed, May 24, 2017 at 07:01:38PM +0100, Jean-Philippe Brucker wrote:
> Address Translation Service (ATS) is an extension to PCIe allowing
> endpoints to manage their own IOTLB, called Address Translation Cache
> (ATC). Instead of having every memory transaction processed by the IOMMU,
> the
On Tue, May 30, 2017 at 11:58:50AM +0100, Jean-Philippe Brucker wrote:
> On 30/05/17 11:01, Joerg Roedel wrote:
> > On Wed, May 24, 2017 at 07:01:38PM +0100, Jean-Philippe Brucker wrote:
> >> +- ats-supported: if present, the root complex supports the Address
> >> + Translation Service (ATS). It
DT changes should go to DT list.
On Fri, May 12, 2017 at 7:41 AM, Geetha sowjanya
wrote:
> From: Linu Cherian
>
> Cavium ThunderX2 SMMU implementation doesn't support page 1 register space
> and PAGE0_REGS_ONLY option is enabled as an errata
On Sat, May 13, 2017 at 4:47 AM, shameer
wrote:
> Signed-off-by: shameer
> ---
> Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git
On Thu, May 4, 2017 at 8:34 AM, Rob Clark wrote:
> An iommu driver for Qualcomm "B" family devices which do not completely
> implement the ARM SMMU spec. These devices have context-bank register
> layout that is similar to ARM SMMU, but no global register space (or at
>
On Tue, May 2, 2017 at 11:46 PM, Oza Pawandeep wrote:
> current device framework and of framework integration assumes
> dma-ranges in a way where memory-mapped devices define their
> dma-ranges. (child-bus-address, parent-bus-address, length).
>
> of_dma_configure is
On Tue, May 2, 2017 at 11:46 PM, Oza Pawandeep wrote:
> current device framework and of framework integration assumes
> dma-ranges in a way where memory-mapped devices define their
> dma-ranges. (child-bus-address, parent-bus-address, length).
>
> of_dma_configure is
On Sat, Apr 22, 2017 at 3:08 AM, Oza Pawandeep wrote:
> current device frmework and of framework integration assumes dma-ranges
> in a way where memory-mapped devices define their dma-ranges.
> dma-ranges: (child-bus-address, parent-bus-address, length).
>
> but iproc based
llback just before the probe of the
> bus/driver is called. Similarly dma_deconfigure is called during
> device/driver_detach path.
For patches 3, 4, 6, 7, 8:
Acked-by: Rob Herring <r...@kernel.org>
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On Fri, Mar 10, 2017 at 12:30:57AM +0530, Sricharan R wrote:
> From: Laurent Pinchart
>
> Failures to look up an IOMMU when parsing the DT iommus property need to
> be handled separately from the .of_xlate() failures to support deferred
> probing.
>
>
On Tue, Mar 28, 2017 at 12:27 AM, Oza Oza <oza@broadcom.com> wrote:
> On Mon, Mar 27, 2017 at 8:16 PM, Rob Herring <r...@kernel.org> wrote:
>> On Sat, Mar 25, 2017 at 12:31 AM, Oza Pawandeep <oza@broadcom.com> wrote:
>>> it is possible that PCI d
On Thu, Mar 23, 2017 at 9:45 PM, Rob Clark <robdcl...@gmail.com> wrote:
> On Thu, Mar 23, 2017 at 6:21 PM, Rob Herring <r...@kernel.org> wrote:
>> On Tue, Mar 14, 2017 at 11:18:05AM -0400, Rob Clark wrote:
>>> Cc: devicet...@vger.kernel.org
>>> Signed
On Sat, Mar 25, 2017 at 12:31 AM, Oza Pawandeep wrote:
> it jumps to the parent node without examining the child node.
> also with that, it throws "no dma-ranges found for node"
> for pci dma-ranges.
>
> this patch fixes device node traversing for dma-ranges.
What's the DT
On Tue, Mar 14, 2017 at 11:18:05AM -0400, Rob Clark wrote:
> Cc: devicet...@vger.kernel.org
> Signed-off-by: Rob Clark
> ---
> .../devicetree/bindings/iommu/qcom,iommu.txt | 113
> +
> 1 file changed, 113 insertions(+)
> create mode 100644
On Thu, Mar 09, 2017 at 09:05:46PM +0530, Sricharan R wrote:
> The QCOM_SMMUV2 is an implementation of the arm,smmu-v2 architecture.
> The qcom,smmu is instantiated for each of the multimedia cores (for eg)
> Venus (video encoder/decoder), mdp (display) etc, and they are connected
> to the
On Thu, Mar 09, 2017 at 09:05:45PM +0530, Sricharan R wrote:
> The MMU400x/500 is the implementation of the SMMUv2
> arch specification. It is split in to two blocks
> TBU, TCU. TBU caches the page table, instantiated
> for each master locally, clocked by the TBUn_clk.
> TCU manages the address
On Wed, Mar 01, 2017 at 12:42:52PM -0500, Rob Clark wrote:
Nit: use "dt-bindings: iommu: ..." for subject. And a commit message
would be nice.
> Cc: devicet...@vger.kernel.org
> Signed-off-by: Rob Clark
> ---
> .../devicetree/bindings/iommu/qcom,iommu.txt | 106
>
On Fri, Feb 03, 2017 at 04:10:30PM +0200, Laurent Pinchart wrote:
> Hi Rob,
>
> On Monday 29 Feb 2016 23:33:09 Magnus Damm wrote:
> > From: Magnus Damm
> >
> > Update the IPMMU DT binding documentation to include the r8a7795 compat
> > string as well as the
On Fri, Dec 16, 2016 at 01:19:29PM +, Robin Murphy wrote:
> The current SMR masking support using a 2-cell iommu-specifier is
> primarily intended to handle individual masters with large and/or
> complex Stream ID assignments; it quickly gets a bit clunky in other SMR
> use-cases where we just
On Thu, Dec 15, 2016 at 06:16:13PM -0600, Stuart Yoder wrote:
> The generic IOMMU binding says that the meaning of an 'IOMMU specifier'
> is defined by the binding of a specific SMMU. The ARM SMMU binding
> never explicitly uses the term 'specifier' at all. Update implicit
> references to use
t; Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt |1 +
> 1 file changed, 1 insertion(+)
Acked-by: Rob Herring <r...@kernel.org>
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On Mon, Sep 12, 2016 at 05:13:43PM +0100, Robin Murphy wrote:
> We're about to ratify our use of the generic binding, so document it.
>
> CC: Rob Herring <robh...@kernel.org>
> CC: Mark Rutland <mark.rutl...@arm.com>
> Signed-off-by: Robin Murphy <robin.mur...@arm.
On Tue, Aug 23, 2016 at 08:05:27PM +0100, Robin Murphy wrote:
> Document how the generic "iommus" binding should be used to describe ARM
> SMMU stream IDs instead of the old "mmu-masters" binding.
>
> CC: Rob Herring <robh...@kernel.org>
> CC: Mark Ru
property. Drag the
> core parsing routine up yet another layer into the general OF-PCI code,
> and further generalise it for either kind of lookup in either flavour
> of map property.
>
> CC: Rob Herring <robh...@kernel.org>
> CC: Frank Rowand <frowand.l...@gmail.com>
> CC:
devicetree/bindings/iommu/msm,iommu-v0.txt
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-bindings/memory/mt2701-larb-port.h | 85
> ++
> 4 files changed, 115 insertions(+), 8 deletions(-)
> create mode 100644 include/dt-bindings/memory/mt2701-larb-port.h
Acked-by: Rob Herring <r...@kernel.org>
_
On Mon, May 09, 2016 at 04:00:12PM +0800, honghui.zh...@mediatek.com wrote:
> From: Honghui Zhang
>
> This patch defines the local arbitor port IDs for mediatek SoC MT2701 and
> add descriptions of binding for mediatek generation one iommu and smi.
>
> Signed-off-by:
On Mon, Apr 4, 2016 at 10:49 AM, Joerg Roedel <j...@8bytes.org> wrote:
> Hi,
>
> here is a new version of the implementation of the iterator
> over phandles concept which Rob Herring suggested to me some
> time ago. My approach is a little bit different from what
&
On Wed, Apr 06, 2016 at 07:59:31PM +0530, Sricharan R wrote:
> The driver currently works based on platform data. Remove this
> and add support for DT. A single master can have multiple ports
> connected to more than one iommu.
>
> master
> |
>
> - None
> ---
> Documentation/devicetree/bindings/{powerpc => soc}/fsl/guts.txt | 3 +++
> 1 file changed, 3 insertions(+)
> rename Documentation/devicetree/bindings/{powerpc => soc}/fsl/guts.txt (91%)
Acked-by: Rob Herring <r...@kernel.org>
_
On Wed, Mar 23, 2016 at 6:54 AM, Joerg Roedel <j...@8bytes.org> wrote:
> Hi Rob,
>
> On Tue, Mar 22, 2016 at 01:45:41PM -0500, Rob Herring wrote:
>> On Tue, Mar 22, 2016 at 12:58 PM, Joerg Roedel <j...@8bytes.org> wrote:
>> > Please review. Patches are ba
On Tue, Mar 22, 2016 at 12:58 PM, Joerg Roedel wrote:
> From: Joerg Roedel
>
> Remove the usage of of_parse_phandle_with_args() and replace
> it by the phandle-iterator implementation so that we can
> parse out all of the potentially present 128 stream-ids.
>
>
On Wed, Mar 09, 2016 at 06:08:49PM +0800, Yangbo Lu wrote:
> Move guts devicetree doc to Documentation/devicetree/bindings/soc/fsl/
> since it's used by not only PowerPC but also ARM. And add a specification
> for 'little-endian' property.
>
> Signed-off-by: Yangbo Lu
> ---
>
On Thu, Mar 17, 2016 at 12:11 PM, Arnd Bergmann <a...@arndb.de> wrote:
> On Thursday 17 March 2016 12:06:40 Rob Herring wrote:
>> > diff --git a/Documentation/devicetree/bindings/powerpc/fsl/guts.txt
>> > b/Documentation/devicetree/bindings/soc/fsl/guts.txt
>> &
-...@vger.kernel.org;
> >> ulf.hans...@linaro.org; Zhao Qiang; Russell King; Bhupesh Sharma; Joerg
> >> Roedel; Santosh Shilimkar; Scott Wood; Rob Herring; Claudiu Manoil; Kumar
> >> Gala; Yang-Leo Li; Xiaobo Xie
> >> Subject: Re: [v6, 5/5] mmc: sdhci-of-
On Wed, Mar 16, 2016 at 11:42 AM, Joerg Roedel wrote:
> From: Joerg Roedel
>
> Getting the arguments of phandles is somewhat limited at the
> moement, because the number of arguments supported by core
> code is limited to MAX_PHANDLE_ARGS, which is set to 16
>
---
> .../devicetree/bindings/iommu/arm,smmu.txt | 40
> ++
> 1 file changed, 25 insertions(+), 15 deletions(-)
Acked-by: Rob Herring <r...@kernel.org>
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1
> +
> 1 file changed, 171 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pci/pci-iommu.txt
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te mode 100644
> Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
> create mode 100644 include/dt-bindings/memory/mt8173-larb-port.h
Acked-by: Rob Herring <r...@kernel.org>
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On Fri, Dec 18, 2015 at 04:09:39PM +0800, Yong Wu wrote:
> This patch add mediatek iommu dts binding document.
>
> Signed-off-by: Yong Wu <yong...@mediatek.com>
Acked-by: Rob Herring <r...@kernel.org>
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On Tue, Dec 08, 2015 at 05:49:10PM +0800, Yong Wu wrote:
> This patch add smi binding document.
>
> Signed-off-by: Yong Wu <yong...@mediatek.com>
Acked-by: Rob Herring <r...@kernel.org>
> ---
> .../memory-controllers/mediatek,smi-common.txt | 24
On Tue, Dec 08, 2015 at 05:49:09PM +0800, Yong Wu wrote:
> This patch add mediatek iommu dts binding document.
>
> Signed-off-by: Yong Wu
> ---
> .../devicetree/bindings/iommu/mediatek,iommu.txt | 68 +
> include/dt-bindings/memory/mt8173-larb-port.h |
On Fri, Nov 20, 2015 at 10:25:07AM +0800, Chen Feng wrote:
> Documentation for hi6220 iommu driver.
>
> Signed-off-by: Chen Feng <puck.c...@hisilicon.com>
Acked-by: Rob Herring <r...@kernel.org>
> ---
> .../bindings/iommu/hisi,hi6220-iommu.txt | 32
> ++
On Tue, Nov 17, 2015 at 5:57 AM, Chen Feng wrote:
> Documentation for hi6220 iommu driver.
Please use get_maintainers.pl and re-send to correct lists
(devicet...@vger.kernel.org).
>
> Signed-off-by: Chen Feng
> ---
>
compatible string may be used as fallback.
>
> Signed-off-by: Magnus Damm <damm+rene...@opensource.se>
Acked-by: Rob Herring <r...@kernel.org>
> ---
>
> Changes since V1:
> - Updated compat string section to the following:
>"Must contain SoC-specif
On Thu, Nov 05, 2015 at 09:34:43PM +0800, Chen Feng wrote:
> Add Document for mtcmos driver on hi6220 SoC
>
> Signed-off-by: Chen Feng
> Signed-off-by: Fei Wang
> ---
> .../bindings/regulator/hisilicon,hi6220-mtcmos.txt | 32
> ++
>
On Mon, Aug 24, 2015 at 5:17 AM, Mark Rutland mark.rutl...@arm.com wrote:
On Wed, Aug 05, 2015 at 05:51:20PM +0100, Mark Rutland wrote:
Rob,
Do you have any objections to this, or are you happy to take this patch?
There's a user of this binding (the GICv3 ITS) queued for v4.3 already in
the
On Thu, Jul 16, 2015 at 6:09 AM, Joerg Roedel jroe...@suse.de wrote:
Hi Will,
On Thu, Jul 16, 2015 at 11:23:26AM +0100, Will Deacon wrote:
On Thu, Jul 16, 2015 at 09:30:43AM +0100, Joerg Roedel wrote:
+struct of_phandle_args *of_alloc_phandle_args(int size)
+{
+ struct of_phandle_args
the of_dma_configure() function is.
Signed-off-by: Laurent Pinchart laurent.pinchart+rene...@ideasonboard.com
One minor fix below, but otherwise:
Acked-by: Rob Herring r...@kernel.org
---
drivers/of/device.c | 12
drivers/of/platform.c | 5 -
include/linux
On Thu, May 14, 2015 at 6:00 PM, Laurent Pinchart
laurent.pinchart+rene...@ideasonboard.com wrote:
The of_configure_dma() function configures both the DMA masks and ops.
Moving DMA ops configuration to probe time would thus also delay
configuration of the DMA masks, which might not be safe. To
. Anyway, looks fine to me:
Acked-by: Rob Herring r...@kernel.org
Rob
2 files changed, 18 insertions(+), 17 deletions(-)
diff --git a/drivers/of/address.c b/drivers/of/address.c
index 78a7dcbec7d8..75eebd19ebfa 100644
--- a/drivers/of/address.c
+++ b/drivers/of/address.c
@@ -924,8 +924,8
Cc: Grant Likely grant.lik...@linaro.org
Cc: Rob Herring robh...@kernel.org
Cc: Bjorn Helgaas bhelg...@google.com
Cc: Will Deacon will.dea...@arm.com
Cc: Russell King li...@arm.linux.org.uk
Cc: Arnd Bergmann a...@arndb.de
Cc: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
Signed
: Joerg Roedel j...@8bytes.org
Cc: Grant Likely grant.lik...@linaro.org
Cc: Rob Herring robh...@kernel.org
Cc: Bjorn Helgaas bhelg...@google.com
Cc: Will Deacon will.dea...@arm.com
Cc: Russell King li...@arm.linux.org.uk
Cc: Arnd Bergmann a...@arndb.de
Cc: Suravee Suthikulpanit
-range is used for PCI and iommu is not
supported. So return error if the device is PCI.
Cc: Joerg Roedel j...@8bytes.org
Cc: Grant Likely grant.lik...@linaro.org
Cc: Rob Herring robh...@kernel.org
Acked-by: Rob Herring r...@kernel.org
Cc: Will Deacon will.dea...@arm.com
Cc: Russell King li
() for implementing this.
Cc: Joerg Roedel j...@8bytes.org
Cc: Grant Likely grant.lik...@linaro.org
Cc: Rob Herring robh...@kernel.org
Acked-by: Rob Herring r...@kernel.org
Cc: Will Deacon will.dea...@arm.com
Cc: Russell King li...@arm.linux.org.uk
Cc: Arnd Bergmann a...@arndb.de
Cc: Suravee
On Fri, Jan 23, 2015 at 12:19 PM, Murali Karicheri m-kariche...@ti.com wrote:
On 01/09/2015 10:34 AM, Rob Herring wrote:
On Thu, Jan 8, 2015 at 4:24 PM, Arnd Bergmanna...@arndb.de wrote:
On Thursday 08 January 2015 14:26:36 Murali Karicheri wrote:
On 01/08/2015 03:40 AM, Arnd Bergmann
On Thu, Jan 8, 2015 at 4:24 PM, Arnd Bergmann a...@arndb.de wrote:
On Thursday 08 January 2015 14:26:36 Murali Karicheri wrote:
On 01/08/2015 03:40 AM, Arnd Bergmann wrote:
On Wednesday 07 January 2015 17:37:56 Rob Herring wrote:
On Wed, Jan 7, 2015 at 12:49 PM, Murali Karicherim-kariche
+Andreas
On Wed, Jan 7, 2015 at 12:53 PM, Will Deacon will.dea...@arm.com wrote:
On Wed, Jan 07, 2015 at 06:35:41PM +, Mitchel Humpherys wrote:
On Wed, Jan 07 2015 at 10:04:20 AM, Will Deacon will.dea...@arm.com wrote:
On Wed, Jan 07, 2015 at 05:52:46PM +, Mitchel Humpherys wrote:
On Wed, Jan 7, 2015 at 12:49 PM, Murali Karicheri m-kariche...@ti.com wrote:
Function of_iommu_configure() is called from of_dma_configure() to
setup iommu ops using DT property. This API is currently used for
platform devices for which DMA configuration (including iommu ops)
may come from
On Wed, Jan 7, 2015 at 12:49 PM, Murali Karicheri m-kariche...@ti.com wrote:
Move of_dma_configure() to device.c so that same function can be re-used
for PCI devices to obtain DMA configuration from DT. Also add a second
argument so that for PCI, DT node of root bus host bridge can be used to
On Tue, Jan 6, 2015 at 2:16 PM, Mitchel Humpherys
mitch...@codeaurora.org wrote:
On Tue, Jan 06 2015 at 06:15:07 AM, Will Deacon will.dea...@arm.com wrote:
/* Invalidate the TLB, just in case */
-writel_relaxed(0, gr0_base + ARM_SMMU_GR0_STLBIALL);
writel_relaxed(0, gr0_base +
robin.mur...@arm.com
Signed-off-by: Will Deacon will.dea...@arm.com
One comment below, but for the DT parts:
Acked-by: Rob Herring r...@kernel.org
---
arch/arm/include/asm/dma-mapping.h | 8
drivers/of/platform.c | 31 +--
include/linux/dma
...@samsung.com
Tested-by: Robin Murphy robin.mur...@arm.com
Signed-off-by: Will Deacon will.dea...@arm.com
Acked-by: Rob Herring r...@kernel.org
---
arch/arm/include/asm/dma-mapping.h | 4 +++-
drivers/of/platform.c | 21 ++---
include/linux/dma-mapping.h| 8
Adding Grant and Pantelis...
On Mon, Dec 1, 2014 at 10:57 AM, Will Deacon will.dea...@arm.com wrote:
IOMMU drivers must be initialised before any of their upstream devices,
otherwise the relevant iommu_ops won't be configured for the bus in
question. To solve this, a number of IOMMU drivers
of you take a look at this please?
I've been quiet on this round, but I think prior input I've had has
been addressed. If we believe this will work for ARM SMMU and MSM
IOMMU and some of the crazy chaining scenarios, then I'm fine with the
binding.
Acked-by: Rob Herring r...@kernel.org
Rob
P.S
On Fri, May 23, 2014 at 3:33 PM, Thierry Reding
thierry.red...@gmail.com wrote:
From: Thierry Reding tred...@nvidia.com
This commit introduces a generic device tree binding for IOMMU devices.
Only a very minimal subset is described here, but it is enough to cover
the requirements of both the
On Fri, May 30, 2014 at 2:06 PM, Arnd Bergmann a...@arndb.de wrote:
On Friday 30 May 2014 08:16:05 Rob Herring wrote:
On Fri, May 23, 2014 at 3:33 PM, Thierry Reding
thierry.red...@gmail.com wrote:
From: Thierry Reding tred...@nvidia.com
+IOMMU master node
On Thu, Jan 16, 2014 at 6:44 AM, Andreas Herrmann
andreas.herrm...@calxeda.com wrote:
Cc: Rob Herring robh...@kernel.org
Cc: Andreas Herrmann herrmann.der.u...@googlemail.com
Signed-off-by: Andreas Herrmann andreas.herrm...@calxeda.com
One minor comment, but otherwise:
Acked-by: Rob Herring r
.
To support Calxeda ECX-2000 hardware arm-smmu driver requires a
slightly higher value for MAX_PHANDLE_ARGS as this hardware has 10
stream IDs for one master device.
Cc: Grant Likely grant.lik...@linaro.org
Cc: Rob Herring robh...@kernel.org
Cc: devicet...@vger.kernel.org
Cc: Andreas Herrmann
On Thu, Jan 16, 2014 at 6:44 AM, Andreas Herrmann
andreas.herrm...@calxeda.com wrote:
This patch adds descriptions fore new properties of device tree
binding for the ARM SMMU architecture. These properties control
arm-smmu driver options.
Cc: Rob Herring robherri...@gmail.com
Cc: Grant
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