Re: [j-nsp] GRE interfaces doesn't show up

2019-08-29 Thread Wojciech Janiszewski
Hi Jeff, What type of DPC card you're using? As per your initial email I wouldn't expect PIC 4 on DPC card related to gr-5/4/0 interface to be present as PICs can take numbers between 0 and 3. What is your network-services mode (show chassis network-services)? Is DPC card up (show chassis fpc)?

Re: [j-nsp] GRE interfaces doesn't show up

2019-08-29 Thread Jeff Meyers
Hi Jim, thanks for the quick reply! However, unfortunately that did not do the job and the interface still doesn't show up, neither with 1g nor 10g for the bandwidth: # show chassis fpc 0 pic 0 {     tunnel-services {     bandwidth 10g;     } } # show interfaces gr-0/0/0 unit 0 {    

Re: [j-nsp] MX10 Pseduwire

2019-08-29 Thread Mohammad Khalil
Thanks very much for the kind reply. My customer is evaluating the options for serving its customers and evaluating the vendors to check what best suits him. I am trying to convince him with Juniper MX10 but he needs some scale values :) Thanks again mate. On Thu, 29 Aug 2019 at 23:48, Saku Ytti

Re: [j-nsp] MX10 Pseduwire

2019-08-29 Thread Saku Ytti
Hey Mohammad, I don't think you'll find anything concrete. I don't think there will be specific hard limit. And answer would require more dimensions. It's different to have 10k pseudowires to 1 remote PE than to have 1 pseudowire to 10k different remote PE. LDP/BGP affects the answer. It would

Re: [j-nsp] LAG/ECMP hash performance

2019-08-29 Thread Saku Ytti
On Thu, 29 Aug 2019 at 23:10, wrote: > All this time watching the thread I'm thinking if it's just coincidence that > in some cases no matter how good the hash value is the available buckets > skew the balancing. (and I guess that's why three are knobs to shift the > hash around. Obviously

Re: [j-nsp] LAG/ECMP hash performance

2019-08-29 Thread Saku Ytti
On Thu, 29 Aug 2019 at 22:17, Thomas Bellman wrote: > I don't think anyone has said that any product use the ethernet > packet's CRC for LAG/ECMP hashing. Just that they might reuse > the CRC circuitry in the NPU/ASIC for calculating this hash, but > based on different inputs. Exactly and even

Re: [j-nsp] LAG/ECMP hash performance

2019-08-29 Thread adamv0025
> James Bensley > Sent: Thursday, August 29, 2019 9:52 AM > > In the worst case scenario (1), with 4 bytes of CRC output to represent an > entire frame there is a large amount of hash collisions; Min size frame; 6 byte > SRC, 6 byte DST, 2 byte EType, 46 byte payload == 2^480 possible Ethernet >

Re: [j-nsp] LAG/ECMP hash performance

2019-08-29 Thread Thomas Bellman
On 2019-08-29 17:31 +0200, Robert Raszuk wrote: > You are very correct. I was very highly surprised to read Saku mentioning > use of CRC for hashing but then quick google revealed this link: > >

[j-nsp] MX10 Pseduwire

2019-08-29 Thread Mohammad Khalil
Greetings all. Am trying to find how many pseduwires are supported on MX10 with no luck. Any ideas? Appreciated. ___ juniper-nsp mailing list juniper-nsp@puck.nether.net https://puck.nether.net/mailman/listinfo/juniper-nsp

Re: [j-nsp] LAG/ECMP hash performance

2019-08-29 Thread Robert Raszuk
Hi Eldon, You are very correct. I was very highly surprised to read Saku mentioning use of CRC for hashing but then quick google revealed this link: https://www.juniper.net/documentation/en_US/junos/topics/reference/configuration-statement/hash-parameters-edit-forwarding-options.html Looks

Re: [j-nsp] Ramp up old MX480

2019-08-29 Thread Richard McGovern
Reduced scale is currently honor based. Please note that in the future, Juniper is very likely to put in SW hooks to make licenses actually active, and no longer honor based. This is likely to be across the whole product portfolio. Rich Richard McGovern Sr Sales Engineer, Juniper Networks

Re: [j-nsp] LAG/ECMP hash performance

2019-08-29 Thread Eldon Koyle
On Thu, Aug 29, 2019 at 2:52 AM James Bensley wrote: > Different parameters may or may not change the diffusion density, but > they may increase the range of results, i.e. perfect diffusion over > 2^2 outcomes vs. perfect diffusion over 2^6 outcomes. > > Also, ASR9Ks use a CRC32 on Typhoon cards

Re: [j-nsp] Ramp up old MX480

2019-08-29 Thread john doe
Thank you for all answers! Is there any licenses required for MPC-3D-16XGE-SFPP, or is the "reduced scale L3" only a gentlemen agreement? Johan On Wed, Aug 28, 2019 at 5:27 PM Tobias Heister wrote: > On 28.08.2019 17:10, Brian Johnson wrote: > > Do you know if you have the enhanced

Re: [j-nsp] GRE interfaces doesn't show up

2019-08-29 Thread Jim Alias
On DPCs you need to set the bandwidth setting. set chassis fpc pic tunnel-services bandwidth <10g - 100g> Be advised that this will burn a 10 gig port for each 10 gigs you assign to tunnel-services. Regard, Clay Haynes Sent from my iPhone > On 29 Aug 2019, at 10:50, Jeff Meyers wrote: >

[j-nsp] GRE interfaces doesn't show up

2019-08-29 Thread Jeff Meyers
Hi list, I'm trying to setup a GRE tunnel interface on a MX480 with DPCE linecards. I want to use xe-5/4/0 and have therefore configured this interface under 'edit chassis' for tunnel-services. The interface vanishes as expected. I have then configured the interface gr-5/4/0 with unit 0 but is

Re: [j-nsp] LAG/ECMP hash performance

2019-08-29 Thread Saku Ytti
On Thu, 29 Aug 2019 at 11:52, James Bensley wrote: > Hmm, interesting, but has anyone confirmed to you these devices to use > a CRC32 for the hashing are you trying to reverse engineer this? Is > there any reason why this couldn't just be a dodgy Juniper proprietary > hash algo? I'm just playing