On 22 May 2016 at 10:14, Adam Vitkovsky wrote:
Hey,
> Aww now I see where the confusion is coming from.
> I wasn't talking about the traffic entering the PFE via WAN input, but I
> meant traffic coming in via Fabric input, should have mention that explicitly.
>
>
> From: Saku Ytti [mailto:s...@ytti.fi]
> Sent: Saturday, May 21, 2016 2:36 PM
>
> On 21 May 2016 at 16:15, Adam Vitkovsky
> wrote:
> >> I'm very very dubious if there is business case to plan to congest XL.
> >> I consider lookup congestion fault which needs to be
On 21 May 2016 at 16:15, Adam Vitkovsky wrote:
>> I'm very very dubious if there is business case to plan to congest XL.
>> I consider lookup congestion fault which needs to be fixed.
>>
> Well during DDoS attack the XL will get congested so you better be prepared
>
> Saku Ytti [mailto:s...@ytti.fi]
> Sent: Saturday, May 21, 2016 12:11 PM
>
> On 21 May 2016 at 04:15, Adam Vitkovsky
> wrote:
>
> Hey,
>
> > So there are no inter XM HSL2 links on the card please?
> > For it to constitute as two PFEs I would then, as per design,
On 21 May 2016 at 04:15, Adam Vitkovsky wrote:
Hey,
> So there are no inter XM HSL2 links on the card please?
> For it to constitute as two PFEs I would then, as per design, expect there to
> be a separate set of VOQs per each XM(PFE) so that each XM can
> From: Hannes Viertel [mailto:hvier...@juniper.net]
> Sent: Friday, May 20, 2016 4:23 PM
>
> A couple of remarks
>
> It’s more like Gen2 (MPC4) and Gen2,5 (MPC5) trio…
>
Well I'd consider MPC3 and MPC4 as Gen 1.5 because they are somewhere half way
between Gen1 (LU+MQ) and Gen2 (XL+XM).
> On
y Envoyé : vendredi 20 mai 2016 16:20 À :
>juniper-nsp@puck.nether.net Objet : [j-nsp] what’s the story behind MPC5E
>
>Hi folks,
>
>Would anyone know what’s the story behind MPC5E (which I think uses one PFE)
>with Gen 2 TRIO (XM, XL)?
>Forwarding capability of up to 130 Gbps per Pack
On 20 May 2016 at 17:23, wrote:
> MPC5e has one PFE (260Gpbs) made of 2 XM chip, 1 XL and 1 XQ (only for Q mode)
Why do you consider it one PFE? One XM has to cross fabric to see
other XM's WAN interfaces, to me that classifies it as dual PFE.
There are some designs
This is the same design for MPC6e PFE and I didn't see any issue with this
design. I also didn't see any specific issue due to this design in POC where we
stressed the PFE. XL ressources are just shared. For Inter XM forwarding, the
shared XL is not used but the fabric links is used.
> Of david@orange.com
> Sent: Friday, May 20, 2016 3:24 PM
>
> MPC5e has one PFE (260Gpbs) made of 2 XM chip, 1 XL and 1 XQ (only for Q
> mode)
>
OMG, now that's bummer like it has two PFEs but they share a common XL :)
Now that's got to be the stupidest TRIO design I've seen so far.
I'd love
)
-Message d'origine-
De : juniper-nsp [mailto:juniper-nsp-boun...@puck.nether.net] De la part de
Adam Vitkovsky Envoyé : vendredi 20 mai 2016 16:20 À :
juniper-nsp@puck.nether.net Objet : [j-nsp] what’s the story behind MPC5E
Hi folks,
Would anyone know what’s the story behind MPC5E (which I
MPC5e has one PFE (260Gpbs) made of 2 XM chip, 1 XL and 1 XQ (only for Q mode)
-Message d'origine-
De : juniper-nsp [mailto:juniper-nsp-boun...@puck.nether.net] De la part de
Adam Vitkovsky
Envoyé : vendredi 20 mai 2016 16:20
À : juniper-nsp@puck.nether.net
Objet : [j-nsp] what’s
Hi folks,
Would anyone know what’s the story behind MPC5E (which I think uses one PFE)
with Gen 2 TRIO (XM, XL)?
Forwarding capability of up to 130 Gbps per Packet Forwarding Engine.
Up to 240 Gbps of full-duplex traffic.
- Since 240 is not 2x130 it begs the question what components are the
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