hi;
does general_protection trap necessarily result to die ?
when executing this instruction : mov(%eax),%gs ,$ip turns to be
general_protection.
then it comes to debug()
I have no clue for what has happend leads kernel to go here . it denotes
what?
Are there some
Hi All
In performance benchmark tools, When we profile read/write timings mostly,
those read/writes are done to cache only.
I want to measure my DDR(RAM chip) performance.
So i want to make sure, every read/write should happen to DDR RAM chip only.
How can i achieve this...Any
The mechanism to disable the L1/L2 memory caches of the CPU will depend on
the processor architecture itself. This can be possibly be done at kernel
boot-time or more preferably, in your case, through a kernel module.
For Intel x86, the kernel module would look something like following: (The
key
I am not sure but what if you make the variable as a volatile?
On Tue, Feb 26, 2013 at 5:01 PM, sandeep kumar coolsandyfor...@gmail.comwrote:
Hi All
In performance benchmark tools, When we profile read/write timings mostly,
those read/writes are done to cache only.
I want to measure my
On Tue, 26 Feb 2013 06:23:34 +0800, horseriver said:
does general_protection trap necessarily result to die ?
Think for a bit - what other actions can reasonably be taken? You
hit a GPF, it's obvious that the variables you're working on have
been corrupted, so automatically continuing is
On Tue, Feb 26, 2013 at 6:31 PM, sandeep kumar
coolsandyfor...@gmail.com wrote:
Hi All
In performance benchmark tools, When we profile read/write timings mostly,
those read/writes are done to cache only.
I want to measure my DDR(RAM chip) performance.
So i want to make sure, every read/write
Hi list,
I am writing a network driver for the e1000 card. While doing the
receive part, I saw that the kernel freezes whenever it reaches the
netif_rx(skb) call. I was able to reproduce the same error when using
a bare bones driver where I hard codde the skb data.
Please see the code of that
On Tue, Feb 26, 2013 at 11:19:18AM -0500, Phani Vadrevu wrote:
unsigned char t[] =
On Tue, 26 Feb 2013 22:35:35 +0700, Mulyadi Santosa said:
let' see
what if you do read and write pattern, in certain order so that it
will be invalidated by the L1/L2/L3 cache everytime?
AFAIK, one thing for sure, reading data from sequentially and re-read
them will make end up reading
On Tue, 26 Feb 2013 11:19:18 -0500, Phani Vadrevu said:
I am writing a network driver for the e1000 card. While doing the
receive part, I saw that the kernel freezes whenever it reaches the
netif_rx(skb) call. I was able to reproduce the same error when using
a bare bones driver where I hard
On Tue, Feb 26, 2013 at 11:57 PM, valdis.kletni...@vt.edu wrote:
Of you could just download a copy of memtest+ and run that - I think that
provides some timing info in addition to actually testing your memory.
How could I missed memtest ! :) Of course, that's the easiest way I
could think
How could I missed memtest ! :) Of course, that's the easiest way I
could think of... if the OP doesn't mind with non programming method
IMHO
But i want to check it on ARM based Android board..
On Wed, Feb 27, 2013 at 6:12 AM, Mulyadi Santosa
mulyadi.sant...@gmail.comwrote:
On Tue, Feb 26,
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