7;s how it's designed to work today (NC
symbols are only for pins) We could add that though.
On Tue, Jun 5, 2018 at 12:50 PM, André S.
wrote:
One reason one wants (labeled) NC nets can be isolation of nets via net
classes to ensure proper distances between not connected pins and other
si
One reason one wants (labeled) NC nets can be isolation of nets via net classes
to ensure proper distances between not connected pins and other signals.
Regards,
André
PS: This reminds me that eeschema correctly recognizes NC symbols as
termination for nets (via ERC) but still shows a “not te
act the same as OpenGL/Cairo in
4.0.7. (Legacy in 4.0.7 behaves differently as Legacy in Nightly.)
I hope this made it clearer.
André
Am 2018-01-04 um 14:18 schrieb Nick Østergaard:
2018-01-04 9:55 GMT+01:00 André S.
mailto:list.dev.ki...@nospamail.de>>:
Hi everyone,
Hi everyone,
I discovered some not consistent behaviour in the current stable release:
On the Legacy canvas you can display Value of the footprint by enabling
Value option under Elements in the Visibility menu.
This is not true for OpenGL and Cairo canvas.
In the Nightly from 2018-01-02 Legacy
negatively. ;)
e.g. the new options for graphical lines in the schematics. Useful
addition there would be to have an option to set the default for this
(type and color). :)
Am 2018-01-02 um 18:28 schrieb José Ignacio:
On Tue, Jan 2, 2018 at 11:18 AM, André S. <mailto:list.dev.ki...@nospamail.de
Hi everyone,
I want to add from a users view:
In the current KiCad 4.0.7 (Windows 64 bit) you can't drag traces in
OpenGL/Cairo, only in legacy. (With this I mean: move a segment of a
trace and it stays attached to the other segments of the trace (Hotkey:
'G')).
Hotkey 'M' moves segments in Op
This is an important feature. +1
André
On April 25, 2016 11:44:19 AM GMT+02:00, Daniel Silverstone
wrote:
>On Sun, Apr 24, 2016 at 14:31:05 +0200, Marco Ciampa wrote:
>> > Therefore, I don't think using a special component/special
>footprint is just a hack: it could be the
>> > right way to
What you describe is the perfect use case for 0 ohm resistors, one
>resistor per net, DRC is happy.
>>> I have seen that technique used in very high power inverters.
>>>
>>> Jean-Paul
>>> N1JPL
>>>
>>>> On Apr 22, 2016, at 4:50 PM, André
0 ohm resistor will do the trick, and can be
>used with a resistor,
>a capacitor, a diode or an inductor without being a nuisance and no
>worries about DRC.
>
>My two cents,
>Jean-Paul
>N1JPL
>
>> On Apr 22, 2016, at 11:34 AM, André S.
>wrote:
>>
>>
&g
Hi everyone,
From a users view I also would love to use net ties in Kicad.
In my opinion they should allow to connect 2 to 4 nets on one point.
In the schematic they could be just a normal component from the presentation
and handling. They may just need a custom field to identify as a net tie
On 12.03.2016 15:54, Chris Pavlina wrote:
You're doing it the wrong way around - if the documentation suggests doing it
this way, it should probably be changed.
First, place the hierarchical labels _inside_ the sheets (not the sheet symbols
- switch to that sheet and place them) using the "Place
Hi everyone,
currently I started a new project.
The project is quite complex with about 10 hierarchical sheets.
I wanted to develop the hierarchy first with which connection goes from
what block, what is the best partitioning for the design, etc.
Today I placed in the parent schematic some hie
could not find this function in KiCad 4.0.2-4.
But I was under the impression that the field is fixed in the symbol,
which it is not.
So it is only a minor annoyance to put the fields in the desired
position when placing the component in the schematic.
André
2016-03-03 16:54 GMT+01:00 André S
file format has no way of supporting this. The goal is to get
the new file formats implemented during the current development cycle.
Whether that happens or not remains to be seen.
On 3/3/2016 9:12 AM, André S. wrote:
Hi everyone,
today I started to create a symbol for a microcontroller.
Since
Hi everyone,
today I started to create a symbol for a microcontroller.
Since there are so many pins I decided to split the device to 3 gates:
One for general GPIO, one for Analog Inputs, one for supply and clock
and jtag etc.
This results in different sized symbols for each gate.
Currently the
Hi,
I see that the GUI of KiCad is not completely translated to German
(misses some translated strings).
However when I look on GitHUb into KiCad/kicad-i18n in branch 4.0 the
translation looks quite complete. (for example the strings in Pcbnew
view menu for switching the canvas).
I see thi
On 11.02.2016 18:04, Clemens Koller wrote:
I am not there yet. But I could imagine to follow your prayer there
and translate it into german.
that was my idea too: the official documentation repository provides an
infrastructure for translation already.
So if it is regarded useful to KiCad users
Hi Simon,
7 sounds like a compact way to provide power connections to devices with
a lot of power pins.
On the other hand I would think you still need bypass capacitors on each
pin and therefore you still need to draw wires for those. Thinking:
- draw a compact power gate for the device with al
As I see it this is what it boils down to.
Though I'm not sure if the current documentation about hidden pins reflects the
actual (intended) behavior of hidden pins and (power) net connections and
naming conventions. Would be great if someone could review this.
André
On February 9, 2016 2
s intended or an error on his
side.
Silently connecting nets and also setting the resulting net name in the netlist
"randomly" to one of the names of the different net labels is --
in my opinion -- not the "right way" to do things.
Regards,
André
On 07.02.2016 12:44, jp ch
the approach fully. I make separate
>> components "POWER_INDUCTOR" etc that have one terminal a power input
>> and the other a power output.
>>
>> On 06/02/16 09:55, André S. wrote:
>>> >This may work when the output is directly connected to the net. But
&g
On 03.02.2016 07:33, Jeff Barlow wrote:
Actually I have intentionally located two footprints so they overlap.
Only one or the other (not both) are stuffed on a given board. One
board, two different BOMs, two different assembles. Very common trick.
Not really a DRC error. There needs to be a way
same thing - power flags and hidden pins are banned in my
designs. To supply power to a net I set the "power output" flag on the
pins of the connector going to the battery/power plug.
On 06/02/16 09:23, André S. wrote:
Ok, I see your point regarding not breaking old designs.
However: t
about what we can achieve given our
current manpower. I can always add new tasks to the global road map for
future dev cycles.
-Original Message- From: Chris Pavlina
Sent: Saturday, February 06, 2016 3:30 PM
To: André S.
Cc: KiCad Developers
Subject: Re: [Kicad-developers] Discussion:
Hi everyone,
this issues are still on my wishlist for KiCad:
- Ban hidden Pins.
- Disallow multiple labels on the same net.
Especially the combination of those two is a source for non-obvious
design bugs.
Wayne recently stated that now the planning for release 5 has started,
so I just thought
Hi everyone.
I worked my way through most of the KiCad documentation during
translation and think it could be improved in one or two places…
Is this the right place to start a discussion on this topic or if not
where would I go?
Regards,
André
__
GMT+01:00 Jon Neal :
It isn't missing, it is just hidden.
Click this button and try again:
https://misc.c4757p.com/this_stupid_button.png
On Thu, Dec 31, 2015 at 6:04 PM André S.
wrote:
Hi everyone,
I'm currently translating the documentation for Pcbnew to German.
Quite early in the
Hi everyone,
I'm currently translating the documentation to German and am currently
on the documentation for Eeschema.
There is mentioned:
"Each sheet is reachable by clicking on its name. For quick access,
right click on a sheet name, and choose to Enter Sheet."
This does not work in the cu
Hi Marco,
that sounds like a good solution until a new workflow is set up and usable.
Regards,
André
On 21.12.2015 13:35, Marco Ciampa wrote:
Hi André,
the doc translation procedure is in the half of a Makefile to CMake
procedure migration, so I am afraid that not all is working properly
and
structions for translators are here:
https://github.com/KiCad/kicad-doc/blob/master/translation_instructions.adoc
Hopefully everything you need should be there.
Best Regards,
Brian.
On 21 December 2015 at 11:02, André S. wrote:
Hi everyone!
I'm planning translating some of the kicad-doc to
Hi everyone!
I'm planning translating some of the kicad-doc to German.
However I could not find any information if there is a "head of
translation" or any German translation team.
Is there anyone I could approach for checking my results if done?
Also: I'm not quite sure what's the current sour
something about this in some FAQ?
Regards,
André
On December 3, 2015 11:34:40 PM GMT+01:00, "Nick Østergaard"
wrote:
>No, you just have an outdated fp-lib-table.
>
>2015-12-03 23:33 GMT+01:00 André S. :
>> Am 03.12.2015 um 23:24 schrieb Jon Neal:
>>>
>>
Am 03.12.2015 um 23:24 schrieb Jon Neal:
Nick is currently ironing out the last issues with the windows
installer. No guarantees when it will be done.
I just downloaded the current build and after starting the CVPCB I got
the attached error message. Seems some paths are hardcoded somewhere...
Am 29.11.2015 um 21:39 schrieb Wayne Stambaugh:
I just finished rolling out KiCad 4.0.0. Many thanks to everyone who
made this possible. Each and every one of you deserve to sit back and
enjoy this accomplishment. I have a few minor requests before I make a
trip to my refrigerator to grab a co
On September 7, 2015 7:06:41 PM GMT+02:00, LordBlick
wrote:
>> As it is today, I can see that this will cause complaints if VCC/+5V
>triggers
>> the ERC to often.
>> This needs to be deiscussed properly before a decission is made.
>If rule check will have settings per project with checkbox „Do
in my eyes.
Regards,
André
Am 28.08.2015 um 17:31 schrieb Chris Pavlina:
With due respect, it sounds to me like you're saying "if I turn off
pieces that make it look good, it doesn't look good anymore". Which,
well, yeah.
On Fri, Aug 28, 2015 at 05:29:58PM +0200, "André S.
Hi all,
not sure if this is the right place to address this, but I think it is a
bad move to change library parts in a way that breaks old designs and
adds a lot of additional work. What I'm referring here is the change to
LEDs and Diodes to the opposite polarity (see attachment).
I wonder wh
labels--something like A0/MOISTURE or
>something like that, assuming one label was A0 and another was
>MOISTURE.
>If you're worried about netnames staying the same, though, there'd have
>to
>be a consistent ordering...
>
>But--it works for me as it is.
>
>Ada
On July 25, 2015 6:04:18 PM GMT+02:00, Adam Wolf
wrote:
>I hate to be "this guy" (https://xkcd.com/1172/),
:D
>have also "seen it in the wild" quite a bit as well.
>
How do you know that net in the layout? It can have any of the labels there. In
the netlist "there can only be one". It may e
Hi everyone,
Some time ago I stumpled across a behavior of kicad that I find at least
annoying if not error producing.
KiCAD does not generate a warning when a net has two (or more) labels attached
to the same net. This is true for global labels and also for power labels.
In one of my designs
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