Il 17/07/2013 18:16, Dave Hansen ha scritto:
I'm causing qemu to spew these emulation failure messages until I kill
it. The guest kernel being run has been hacked up pretty heavily and is
probably either accessing bad physical addresses (above the address
ranges in the e820 table) or trying
On 07/18/2013 01:31 PM, Gleb Natapov wrote:
On Thu, Jul 18, 2013 at 12:52:37PM +0800, Xiao Guangrong wrote:
Currently, fast page fault tries to fix mmio page fault when the
generation number is invalid (spte.gen != kvm.gen) and returns to
guest to retry the fault since it sees the last spte is
On Thu, Jul 18, 2013 at 02:01:47PM +0800, Xiao Guangrong wrote:
On 07/18/2013 01:31 PM, Gleb Natapov wrote:
On Thu, Jul 18, 2013 at 12:52:37PM +0800, Xiao Guangrong wrote:
Currently, fast page fault tries to fix mmio page fault when the
generation number is invalid (spte.gen != kvm.gen) and
Signed-off-by: Bharat Bhushan bharat.bhus...@freescale.com
---
arch/powerpc/kvm/e500.h |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/kvm/e500.h b/arch/powerpc/kvm/e500.h
index c2e5e98..277cb18 100644
--- a/arch/powerpc/kvm/e500.h
+++
If there is a struct page for the requested mapping then it's
normal DDR and the mapping sets M bit (coherent, cacheable)
else this is treated as I/O and we set I + G (cache inhibited, guarded)
This helps setting proper TLB mapping for direct assigned device
Signed-off-by: Bharat Bhushan
On 07/18/2013 02:04 PM, Bharat Bhushan wrote:
If there is a struct page for the requested mapping then it's
normal DDR and the mapping sets M bit (coherent, cacheable)
else this is treated as I/O and we set I + G (cache inhibited, guarded)
This helps setting proper TLB mapping for direct
On 07/18/2013 02:06 PM, Gleb Natapov wrote:
On Thu, Jul 18, 2013 at 02:01:47PM +0800, Xiao Guangrong wrote:
On 07/18/2013 01:31 PM, Gleb Natapov wrote:
On Thu, Jul 18, 2013 at 12:52:37PM +0800, Xiao Guangrong wrote:
Currently, fast page fault tries to fix mmio page fault when the
generation
On Thu, Jul 18, 2013 at 02:25:19PM +0800, Xiao Guangrong wrote:
On 07/18/2013 02:06 PM, Gleb Natapov wrote:
On Thu, Jul 18, 2013 at 02:01:47PM +0800, Xiao Guangrong wrote:
On 07/18/2013 01:31 PM, Gleb Natapov wrote:
On Thu, Jul 18, 2013 at 12:52:37PM +0800, Xiao Guangrong wrote:
On Thu, Jul 18, 2013 at 07:58:31AM +0200, Paolo Bonzini wrote:
Il 17/07/2013 18:16, Dave Hansen ha scritto:
I'm causing qemu to spew these emulation failure messages until I kill
it. The guest kernel being run has been hacked up pretty heavily and is
probably either accessing bad physical
Hi,
just to let You know, with realtek instead of virtio-net, it seems
to be reachable for almost three days.. I'd give it another day, then we
can be pretty sure it's virtio related...
BR
nik
--
-
Ing. Nikola CIPRICH
LinuxBox.cz, s.r.o.
28.rijna 168, 709
On Thu, Jul 18, 2013 at 08:55:25AM +0200, Nikola Ciprich wrote:
Hi,
just to let You know, with realtek instead of virtio-net, it seems
to be reachable for almost three days.. I'd give it another day, then we
can be pretty sure it's virtio related...
Thanks. Interesting. Copying virtio-net
-Original Message-
From: “tiejun.chen” [mailto:tiejun.c...@windriver.com]
Sent: Thursday, July 18, 2013 11:56 AM
To: Bhushan Bharat-R65777
Cc: kvm-...@vger.kernel.org; kvm@vger.kernel.org; ag...@suse.de; Wood Scott-
B07421; Bhushan Bharat-R65777
Subject: Re: [PATCH 2/2] kvm:
On Thu, Jul 18, 2013 at 07:52:21AM +0200, Paolo Bonzini wrote:
Il 17/07/2013 20:54, Arthur Chunqi Li ha scritto:
+ .globl entry_sysenter\n\t
+ entry_sysenter:\n\t
+ SAVE_GPR
+ and $0xf, %rax\n\t
+ push%rax\n\t
push should be wrong here, the first
On 07/18/2013 03:12 PM, Bhushan Bharat-R65777 wrote:
-Original Message-
From: “tiejun.chen” [mailto:tiejun.c...@windriver.com]
Sent: Thursday, July 18, 2013 11:56 AM
To: Bhushan Bharat-R65777
Cc: kvm-...@vger.kernel.org; kvm@vger.kernel.org; ag...@suse.de; Wood Scott-
B07421; Bhushan
-Original Message-
From: kvm-ppc-ow...@vger.kernel.org [mailto:kvm-ppc-ow...@vger.kernel.org] On
Behalf Of “tiejun.chen”
Sent: Thursday, July 18, 2013 1:01 PM
To: Bhushan Bharat-R65777
Cc: kvm-...@vger.kernel.org; kvm@vger.kernel.org; ag...@suse.de; Wood Scott-
B07421
Subject:
On 07/18/2013 04:08 PM, Bhushan Bharat-R65777 wrote:
-Original Message-
From: kvm-ppc-ow...@vger.kernel.org [mailto:kvm-ppc-ow...@vger.kernel.org] On
Behalf Of “tiejun.chen”
Sent: Thursday, July 18, 2013 1:01 PM
To: Bhushan Bharat-R65777
Cc: kvm-...@vger.kernel.org;
-Original Message-
From: “tiejun.chen” [mailto:tiejun.c...@windriver.com]
Sent: Thursday, July 18, 2013 1:52 PM
To: Bhushan Bharat-R65777
Cc: kvm-...@vger.kernel.org; kvm@vger.kernel.org; ag...@suse.de; Wood Scott-
B07421
Subject: Re: [PATCH 2/2] kvm: powerpc: set cache coherency
On 07/18/2013 02:04 PM, Bharat Bhushan wrote:
If there is a struct page for the requested mapping then it's
normal DDR and the mapping sets M bit (coherent, cacheable)
else this is treated as I/O and we set I + G (cache inhibited, guarded)
This helps setting proper TLB mapping for direct
-Original Message-
From: Bhushan Bharat-R65777
Sent: Thursday, July 18, 2013 1:53 PM
To: '“tiejun.chen”'
Cc: kvm-...@vger.kernel.org; kvm@vger.kernel.org; ag...@suse.de; Wood Scott-
B07421
Subject: RE: [PATCH 2/2] kvm: powerpc: set cache coherency only for kernel
managed pages
On 07/18/2013 04:25 PM, Bhushan Bharat-R65777 wrote:
-Original Message-
From: Bhushan Bharat-R65777
Sent: Thursday, July 18, 2013 1:53 PM
To: '“tiejun.chen”'
Cc: kvm-...@vger.kernel.org; kvm@vger.kernel.org; ag...@suse.de; Wood Scott-
B07421
Subject: RE: [PATCH 2/2] kvm: powerpc: set
On 18.07.2013, at 10:55, “tiejun.chen” wrote:
On 07/18/2013 04:25 PM, Bhushan Bharat-R65777 wrote:
-Original Message-
From: Bhushan Bharat-R65777
Sent: Thursday, July 18, 2013 1:53 PM
To: '“tiejun.chen”'
Cc: kvm-...@vger.kernel.org; kvm@vger.kernel.org; ag...@suse.de; Wood
On 18.07.2013, at 10:25, Bhushan Bharat-R65777 wrote:
-Original Message-
From: Bhushan Bharat-R65777
Sent: Thursday, July 18, 2013 1:53 PM
To: '“tiejun.chen”'
Cc: kvm-...@vger.kernel.org; kvm@vger.kernel.org; ag...@suse.de; Wood Scott-
B07421
Subject: RE: [PATCH 2/2] kvm:
-Original Message-
From: kvm-ppc-ow...@vger.kernel.org [mailto:kvm-ppc-ow...@vger.kernel.org] On
Behalf Of Alexander Graf
Sent: Thursday, July 18, 2013 3:19 PM
To: Bhushan Bharat-R65777
Cc: “tiejun.chen”; kvm-...@vger.kernel.org; kvm@vger.kernel.org; Wood Scott-
B07421
Subject:
On 07/18/2013 05:44 PM, Alexander Graf wrote:
On 18.07.2013, at 10:55, �tiejun.chen� wrote:
On 07/18/2013 04:25 PM, Bhushan Bharat-R65777 wrote:
-Original Message-
From: Bhushan Bharat-R65777
Sent: Thursday, July 18, 2013 1:53 PM
To: '�tiejun.chen�'
Cc: kvm-...@vger.kernel.org;
On 18.07.2013, at 11:56, “tiejun.chen” wrote:
On 07/18/2013 05:44 PM, Alexander Graf wrote:
On 18.07.2013, at 10:55, �tiejun.chen� wrote:
On 07/18/2013 04:25 PM, Bhushan Bharat-R65777 wrote:
-Original Message-
From: Bhushan Bharat-R65777
Sent: Thursday, July 18, 2013 1:53
On 07/18/2013 05:48 PM, Alexander Graf wrote:
On 18.07.2013, at 10:25, Bhushan Bharat-R65777 wrote:
-Original Message-
From: Bhushan Bharat-R65777
Sent: Thursday, July 18, 2013 1:53 PM
To: '�tiejun.chen�'
Cc: kvm-...@vger.kernel.org; kvm@vger.kernel.org; ag...@suse.de; Wood Scott-
On 18.07.2013, at 12:08, “tiejun.chen” wrote:
On 07/18/2013 05:48 PM, Alexander Graf wrote:
On 18.07.2013, at 10:25, Bhushan Bharat-R65777 wrote:
-Original Message-
From: Bhushan Bharat-R65777
Sent: Thursday, July 18, 2013 1:53 PM
To: '�tiejun.chen�'
Cc:
On 07/18/2013 06:00 PM, Alexander Graf wrote:
On 18.07.2013, at 11:56, “tiejun.chen” wrote:
On 07/18/2013 05:44 PM, Alexander Graf wrote:
On 18.07.2013, at 10:55, �tiejun.chen� wrote:
On 07/18/2013 04:25 PM, Bhushan Bharat-R65777 wrote:
-Original Message-
From: Bhushan
On 07/18/2013 06:12 PM, Alexander Graf wrote:
On 18.07.2013, at 12:08, “tiejun.chen” wrote:
On 07/18/2013 05:48 PM, Alexander Graf wrote:
On 18.07.2013, at 10:25, Bhushan Bharat-R65777 wrote:
-Original Message-
From: Bhushan Bharat-R65777
Sent: Thursday, July 18, 2013 1:53 PM
On 18.07.2013, at 12:19, “tiejun.chen” wrote:
On 07/18/2013 06:12 PM, Alexander Graf wrote:
On 18.07.2013, at 12:08, “tiejun.chen” wrote:
On 07/18/2013 05:48 PM, Alexander Graf wrote:
On 18.07.2013, at 10:25, Bhushan Bharat-R65777 wrote:
-Original Message-
From: Bhushan
Il 18/07/2013 09:26, Gleb Natapov ha scritto:
I had written a long explanation here about why I don't trust the
compiler to do the right thing, and ideas about how to fix that. But in
the end the only workable solution is a single assembly blob like vmx.c
in KVM to do vmlaunch/vmresume,
On Thu, Jul 18, 2013 at 12:47:46PM +0200, Paolo Bonzini wrote:
and for a testsuite I'd prefer the latter---which means I'd still favor
setjmp/longjmp.
Now, here is the long explanation.
I must admit that the code looks nice. There are some nits I'd like to
see done
Il 18/07/2013 13:06, Gleb Natapov ha scritto:
On Thu, Jul 18, 2013 at 12:47:46PM +0200, Paolo Bonzini wrote:
and for a testsuite I'd prefer the latter---which means I'd still favor
setjmp/longjmp.
Now, here is the long explanation.
I must admit that the code looks nice. There are some nits
On Tue, Jul 16, 2013 at 03:01:58PM +0300, Gleb Natapov wrote:
On Tue, Jul 16, 2013 at 07:56:25PM +0800, Arthur Chunqi Li wrote:
On Tue, Jul 16, 2013 at 7:42 PM, Gleb Natapov g...@redhat.com wrote:
On Sun, Jul 07, 2013 at 11:13:37PM +0800, Arthur Chunqi Li wrote:
The recent KVM patch adds
Signed-off-by: Bharat Bhushan bharat.bhus...@freescale.com
---
v2:
- No change
arch/powerpc/kvm/e500.h |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/kvm/e500.h b/arch/powerpc/kvm/e500.h
index c2e5e98..277cb18 100644
--- a/arch/powerpc/kvm/e500.h
+++
If there is a struct page for the requested mapping then it's
normal RAM and the mapping is set to M bit (coherent, cacheable)
otherwise this is treated as I/O and we set I + G (cache inhibited, guarded)
This helps setting proper TLB mapping for direct assigned device
Signed-off-by: Bharat
Il 11/07/2013 12:41, Christian Borntraeger ha scritto:
On 11/07/13 11:04, Gleb Natapov wrote:
On Wed, Jul 10, 2013 at 02:59:55PM +0200, Dominik Dingel wrote:
This patch enables async page faults for s390 kvm guests.
It provides the userspace API to enable, disable or get the status of this
On Thu, Jul 18, 2013 at 8:08 PM, Paolo Bonzini pbonz...@redhat.com wrote:
Il 18/07/2013 13:06, Gleb Natapov ha scritto:
On Thu, Jul 18, 2013 at 12:47:46PM +0200, Paolo Bonzini wrote:
and for a testsuite I'd prefer the latter---which means I'd still favor
setjmp/longjmp.
Now, here is the long
On 18/07/13 15:57, Paolo Bonzini wrote:
Il 11/07/2013 12:41, Christian Borntraeger ha scritto:
On 11/07/13 11:04, Gleb Natapov wrote:
On Wed, Jul 10, 2013 at 02:59:55PM +0200, Dominik Dingel wrote:
This patch enables async page faults for s390 kvm guests.
It provides the userspace API to
This needs a description. Why shouldn't we ignore E?
Alex
On 18.07.2013, at 15:19, Bharat Bhushan wrote:
Signed-off-by: Bharat Bhushan bharat.bhus...@freescale.com
---
v2:
- No change
arch/powerpc/kvm/e500.h |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git
On 18.07.2013, at 15:19, Bharat Bhushan wrote:
If there is a struct page for the requested mapping then it's
normal RAM and the mapping is set to M bit (coherent, cacheable)
otherwise this is treated as I/O and we set I + G (cache inhibited,
guarded)
This helps setting proper TLB
-Original Message-
From: kvm-ppc-ow...@vger.kernel.org [mailto:kvm-ppc-ow...@vger.kernel.org] On
Behalf Of Alexander Graf
Sent: Thursday, July 18, 2013 8:18 PM
To: Bhushan Bharat-R65777
Cc: kvm-...@vger.kernel.org; kvm@vger.kernel.org; Wood Scott-B07421; Bhushan
Bharat-R65777
-Original Message-
From: kvm-ppc-ow...@vger.kernel.org [mailto:kvm-ppc-ow...@vger.kernel.org] On
Behalf Of Alexander Graf
Sent: Thursday, July 18, 2013 8:23 PM
To: Bhushan Bharat-R65777
Cc: kvm-...@vger.kernel.org; kvm@vger.kernel.org; Wood Scott-B07421; Bhushan
Bharat-R65777
On 18.07.2013, at 17:15, Bhushan Bharat-R65777 wrote:
-Original Message-
From: kvm-ppc-ow...@vger.kernel.org [mailto:kvm-ppc-ow...@vger.kernel.org] On
Behalf Of Alexander Graf
Sent: Thursday, July 18, 2013 8:23 PM
To: Bhushan Bharat-R65777
Cc: kvm-...@vger.kernel.org;
On 18.07.2013, at 17:12, Bhushan Bharat-R65777 wrote:
-Original Message-
From: kvm-ppc-ow...@vger.kernel.org [mailto:kvm-ppc-ow...@vger.kernel.org] On
Behalf Of Alexander Graf
Sent: Thursday, July 18, 2013 8:18 PM
To: Bhushan Bharat-R65777
Cc: kvm-...@vger.kernel.org;
-Original Message-
From: Alexander Graf [mailto:ag...@suse.de]
Sent: Thursday, July 18, 2013 8:50 PM
To: Bhushan Bharat-R65777
Cc: kvm-...@vger.kernel.org; kvm@vger.kernel.org; Wood Scott-B07421
Subject: Re: [PATCH 1/2 v2] kvm: powerpc: Do not ignore E attribute in mas2
On
On 07/18/2013 05:00:42 AM, Alexander Graf wrote:
Now why is setting invalid flags a problem? If I understand Scott
correctly, it can break the host if you access certain host devices
with caching enabled. But to be sure I'd say we ask him directly :).
The architecture makes it illegal to
On 07/18/2013 10:12:30 AM, Bhushan Bharat-R65777 wrote:
-Original Message-
From: kvm-ppc-ow...@vger.kernel.org
[mailto:kvm-ppc-ow...@vger.kernel.org] On
Behalf Of Alexander Graf
Sent: Thursday, July 18, 2013 8:18 PM
To: Bhushan Bharat-R65777
Cc: kvm-...@vger.kernel.org;
On 07/18/2013 08:19:03 AM, Bharat Bhushan wrote:
If there is a struct page for the requested mapping then it's
normal RAM and the mapping is set to M bit (coherent, cacheable)
otherwise this is treated as I/O and we set I + G (cache
inhibited, guarded)
This helps setting proper TLB mapping
On 18.07.2013, at 19:17, Scott Wood wrote:
On 07/18/2013 08:19:03 AM, Bharat Bhushan wrote:
If there is a struct page for the requested mapping then it's
normal RAM and the mapping is set to M bit (coherent, cacheable)
otherwise this is treated as I/O and we set I + G (cache inhibited,
On 07/18/2013 12:32:18 PM, Alexander Graf wrote:
On 18.07.2013, at 19:17, Scott Wood wrote:
On 07/18/2013 08:19:03 AM, Bharat Bhushan wrote:
Likewise, we want to make sure this matches the host entry.
Unfortunately, this is a bit of a mess already. 64-bit booke appears
to always set
On Thu, Jul 18, 2013 at 02:08:51PM +0200, Paolo Bonzini wrote:
Il 18/07/2013 13:06, Gleb Natapov ha scritto:
On Thu, Jul 18, 2013 at 12:47:46PM +0200, Paolo Bonzini wrote:
and for a testsuite I'd prefer the latter---which means I'd still favor
setjmp/longjmp.
Now, here is the long
From: Andi Kleen a...@linux.intel.com
[KVM maintainers:
The underlying support for this is in perf/core now. So please merge
this patch into the KVM tree.]
This is not arch perfmon, but older CPUs will just ignore it. This makes
it possible to do at least some TSX measurements from a KVM guest
On 07/16/2013 10:53 AM, Alexey Kardashevskiy wrote:
The changes are:
1. rebased on v3.11-rc1 so the capability numbers changed again
2. fixed multiple comments from maintainers
3. KVM: PPC: Add support for IOMMU in-kernel handling is split into
2 patches, the new one is powerpc/iommu: rework
Signed-off-by: Bharat Bhushan bharat.bhus...@freescale.com
---
arch/powerpc/kvm/e500.h |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/kvm/e500.h b/arch/powerpc/kvm/e500.h
index c2e5e98..277cb18 100644
--- a/arch/powerpc/kvm/e500.h
+++
If there is a struct page for the requested mapping then it's
normal DDR and the mapping sets M bit (coherent, cacheable)
else this is treated as I/O and we set I + G (cache inhibited, guarded)
This helps setting proper TLB mapping for direct assigned device
Signed-off-by: Bharat Bhushan
On 07/18/2013 02:04 PM, Bharat Bhushan wrote:
If there is a struct page for the requested mapping then it's
normal DDR and the mapping sets M bit (coherent, cacheable)
else this is treated as I/O and we set I + G (cache inhibited, guarded)
This helps setting proper TLB mapping for direct
-Original Message-
From: “tiejun.chen” [mailto:tiejun.c...@windriver.com]
Sent: Thursday, July 18, 2013 11:56 AM
To: Bhushan Bharat-R65777
Cc: kvm-ppc@vger.kernel.org; k...@vger.kernel.org; ag...@suse.de; Wood Scott-
B07421; Bhushan Bharat-R65777
Subject: Re: [PATCH 2/2] kvm:
On 07/18/2013 03:12 PM, Bhushan Bharat-R65777 wrote:
-Original Message-
From: “tiejun.chen” [mailto:tiejun.c...@windriver.com]
Sent: Thursday, July 18, 2013 11:56 AM
To: Bhushan Bharat-R65777
Cc: kvm-ppc@vger.kernel.org; k...@vger.kernel.org; ag...@suse.de; Wood Scott-
B07421; Bhushan
-Original Message-
From: kvm-ppc-ow...@vger.kernel.org [mailto:kvm-ppc-ow...@vger.kernel.org] On
Behalf Of “tiejun.chen”
Sent: Thursday, July 18, 2013 1:01 PM
To: Bhushan Bharat-R65777
Cc: kvm-ppc@vger.kernel.org; k...@vger.kernel.org; ag...@suse.de; Wood Scott-
B07421
Subject:
On 07/18/2013 04:08 PM, Bhushan Bharat-R65777 wrote:
-Original Message-
From: kvm-ppc-ow...@vger.kernel.org [mailto:kvm-ppc-ow...@vger.kernel.org] On
Behalf Of “tiejun.chen”
Sent: Thursday, July 18, 2013 1:01 PM
To: Bhushan Bharat-R65777
Cc: kvm-ppc@vger.kernel.org;
-Original Message-
From: “tiejun.chen” [mailto:tiejun.c...@windriver.com]
Sent: Thursday, July 18, 2013 1:52 PM
To: Bhushan Bharat-R65777
Cc: kvm-ppc@vger.kernel.org; k...@vger.kernel.org; ag...@suse.de; Wood Scott-
B07421
Subject: Re: [PATCH 2/2] kvm: powerpc: set cache coherency
On 07/18/2013 02:04 PM, Bharat Bhushan wrote:
If there is a struct page for the requested mapping then it's
normal DDR and the mapping sets M bit (coherent, cacheable)
else this is treated as I/O and we set I + G (cache inhibited, guarded)
This helps setting proper TLB mapping for direct
-Original Message-
From: Bhushan Bharat-R65777
Sent: Thursday, July 18, 2013 1:53 PM
To: '“tiejun.chen”'
Cc: kvm-ppc@vger.kernel.org; k...@vger.kernel.org; ag...@suse.de; Wood Scott-
B07421
Subject: RE: [PATCH 2/2] kvm: powerpc: set cache coherency only for kernel
managed pages
On 07/18/2013 04:25 PM, Bhushan Bharat-R65777 wrote:
-Original Message-
From: Bhushan Bharat-R65777
Sent: Thursday, July 18, 2013 1:53 PM
To: '“tiejun.chen”'
Cc: kvm-ppc@vger.kernel.org; k...@vger.kernel.org; ag...@suse.de; Wood Scott-
B07421
Subject: RE: [PATCH 2/2] kvm: powerpc: set
On 18.07.2013, at 10:55, “tiejun.chen” wrote:
On 07/18/2013 04:25 PM, Bhushan Bharat-R65777 wrote:
-Original Message-
From: Bhushan Bharat-R65777
Sent: Thursday, July 18, 2013 1:53 PM
To: '“tiejun.chen”'
Cc: kvm-ppc@vger.kernel.org; k...@vger.kernel.org; ag...@suse.de; Wood
On 18.07.2013, at 10:25, Bhushan Bharat-R65777 wrote:
-Original Message-
From: Bhushan Bharat-R65777
Sent: Thursday, July 18, 2013 1:53 PM
To: '“tiejun.chen”'
Cc: kvm-ppc@vger.kernel.org; k...@vger.kernel.org; ag...@suse.de; Wood Scott-
B07421
Subject: RE: [PATCH 2/2] kvm:
-Original Message-
From: kvm-ppc-ow...@vger.kernel.org [mailto:kvm-ppc-ow...@vger.kernel.org] On
Behalf Of Alexander Graf
Sent: Thursday, July 18, 2013 3:19 PM
To: Bhushan Bharat-R65777
Cc: “tiejun.chen”; kvm-ppc@vger.kernel.org; k...@vger.kernel.org; Wood
Scott-
B07421
On 07/18/2013 05:44 PM, Alexander Graf wrote:
On 18.07.2013, at 10:55, �tiejun.chen� wrote:
On 07/18/2013 04:25 PM, Bhushan Bharat-R65777 wrote:
-Original Message-
From: Bhushan Bharat-R65777
Sent: Thursday, July 18, 2013 1:53 PM
To: '�tiejun.chen�'
Cc: kvm-ppc@vger.kernel.org;
On 18.07.2013, at 11:56, “tiejun.chen” wrote:
On 07/18/2013 05:44 PM, Alexander Graf wrote:
On 18.07.2013, at 10:55, �tiejun.chen� wrote:
On 07/18/2013 04:25 PM, Bhushan Bharat-R65777 wrote:
-Original Message-
From: Bhushan Bharat-R65777
Sent: Thursday, July 18, 2013 1:53
On 18.07.2013, at 12:08, “tiejun.chen” wrote:
On 07/18/2013 05:48 PM, Alexander Graf wrote:
On 18.07.2013, at 10:25, Bhushan Bharat-R65777 wrote:
-Original Message-
From: Bhushan Bharat-R65777
Sent: Thursday, July 18, 2013 1:53 PM
To: '�tiejun.chen�'
Cc:
On 07/18/2013 06:00 PM, Alexander Graf wrote:
On 18.07.2013, at 11:56, “tiejun.chen” wrote:
On 07/18/2013 05:44 PM, Alexander Graf wrote:
On 18.07.2013, at 10:55, �tiejun.chen� wrote:
On 07/18/2013 04:25 PM, Bhushan Bharat-R65777 wrote:
-Original Message-
From: Bhushan
On 07/18/2013 06:12 PM, Alexander Graf wrote:
On 18.07.2013, at 12:08, “tiejun.chen” wrote:
On 07/18/2013 05:48 PM, Alexander Graf wrote:
On 18.07.2013, at 10:25, Bhushan Bharat-R65777 wrote:
-Original Message-
From: Bhushan Bharat-R65777
Sent: Thursday, July 18, 2013 1:53 PM
Signed-off-by: Bharat Bhushan bharat.bhus...@freescale.com
---
v2:
- No change
arch/powerpc/kvm/e500.h |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/kvm/e500.h b/arch/powerpc/kvm/e500.h
index c2e5e98..277cb18 100644
--- a/arch/powerpc/kvm/e500.h
+++
If there is a struct page for the requested mapping then it's
normal RAM and the mapping is set to M bit (coherent, cacheable)
otherwise this is treated as I/O and we set I + G (cache inhibited, guarded)
This helps setting proper TLB mapping for direct assigned device
Signed-off-by: Bharat
This needs a description. Why shouldn't we ignore E?
Alex
On 18.07.2013, at 15:19, Bharat Bhushan wrote:
Signed-off-by: Bharat Bhushan bharat.bhus...@freescale.com
---
v2:
- No change
arch/powerpc/kvm/e500.h |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git
On 18.07.2013, at 15:19, Bharat Bhushan wrote:
If there is a struct page for the requested mapping then it's
normal RAM and the mapping is set to M bit (coherent, cacheable)
otherwise this is treated as I/O and we set I + G (cache inhibited,
guarded)
This helps setting proper TLB
On 18.07.2013, at 17:15, Bhushan Bharat-R65777 wrote:
-Original Message-
From: kvm-ppc-ow...@vger.kernel.org [mailto:kvm-ppc-ow...@vger.kernel.org] On
Behalf Of Alexander Graf
Sent: Thursday, July 18, 2013 8:23 PM
To: Bhushan Bharat-R65777
Cc: kvm-ppc@vger.kernel.org;
On 18.07.2013, at 17:12, Bhushan Bharat-R65777 wrote:
-Original Message-
From: kvm-ppc-ow...@vger.kernel.org [mailto:kvm-ppc-ow...@vger.kernel.org] On
Behalf Of Alexander Graf
Sent: Thursday, July 18, 2013 8:18 PM
To: Bhushan Bharat-R65777
Cc: kvm-ppc@vger.kernel.org;
-Original Message-
From: Alexander Graf [mailto:ag...@suse.de]
Sent: Thursday, July 18, 2013 8:50 PM
To: Bhushan Bharat-R65777
Cc: kvm-ppc@vger.kernel.org; k...@vger.kernel.org; Wood Scott-B07421
Subject: Re: [PATCH 1/2 v2] kvm: powerpc: Do not ignore E attribute in mas2
On
On 07/18/2013 05:00:42 AM, Alexander Graf wrote:
Now why is setting invalid flags a problem? If I understand Scott
correctly, it can break the host if you access certain host devices
with caching enabled. But to be sure I'd say we ask him directly :).
The architecture makes it illegal to
On 07/18/2013 10:12:30 AM, Bhushan Bharat-R65777 wrote:
-Original Message-
From: kvm-ppc-ow...@vger.kernel.org
[mailto:kvm-ppc-ow...@vger.kernel.org] On
Behalf Of Alexander Graf
Sent: Thursday, July 18, 2013 8:18 PM
To: Bhushan Bharat-R65777
Cc: kvm-ppc@vger.kernel.org;
On 18.07.2013, at 19:17, Scott Wood wrote:
On 07/18/2013 08:19:03 AM, Bharat Bhushan wrote:
If there is a struct page for the requested mapping then it's
normal RAM and the mapping is set to M bit (coherent, cacheable)
otherwise this is treated as I/O and we set I + G (cache inhibited,
On 07/16/2013 10:53 AM, Alexey Kardashevskiy wrote:
The changes are:
1. rebased on v3.11-rc1 so the capability numbers changed again
2. fixed multiple comments from maintainers
3. KVM: PPC: Add support for IOMMU in-kernel handling is split into
2 patches, the new one is powerpc/iommu: rework
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