On Wed, May 21, 2014 at 12:17:37AM +0100, James Hogan wrote:
> On Tuesday 20 May 2014 16:47:15 Andreas Herrmann wrote:
> > Change CPU selection, enable SMP, enable almost all virtio options.
>
> Looks like this should just be squashed into the previous patch if the
> original defconfig was insuff
On Wed, May 21, 2014 at 12:14:31AM +0100, James Hogan wrote:
> Hi Andreas,
>
> On Tuesday 20 May 2014 16:47:14 Andreas Herrmann wrote:
> > From: David Daney
> >
> > Signed-off-by: David Daney
> > Signed-off-by: Andreas Herrmann
> > ---
> > arch/mips/configs/mips_paravirt_defconfig | 1524
> >
On Tue, May 20, 2014 at 04:23:03PM -0700, David Daney wrote:
> On 05/20/2014 03:52 PM, James Hogan wrote:
> >Hi Andreas,
> >
> >On Tuesday 20 May 2014 16:47:04 Andreas Herrmann wrote:
> >>From: David Daney
> >>
> >>CVMSEG is related to the CPU core not the SoC system. So needs to be
> >>configura
On Wed, 05/21 05:40, Liu, RongrongX wrote:
> Hi,
>
> After download the latest
> qemu.git(http://git.qemu.org/?p=qemu.git;a=summary), then compile the
> qemu.git, it will build fail with error
>
> Some build log
>
> CCtrace/generated-events.o
> CCtrace/generated-tracers.o
>
Hi,
After download the latest qemu.git(http://git.qemu.org/?p=qemu.git;a=summary),
then compile the qemu.git, it will build fail with error
Some build log
CCtrace/generated-events.o
CCtrace/generated-tracers.o
CCutil/cutils.o
ARlibqemustub.a
lt LINK vscclient
AR
https://bugzilla.kernel.org/show_bug.cgi?id=65561
--- Comment #6 from Jatin Kumar ---
(In reply to Jatin Kumar from comment #5)
> whenever I hit an out instruction, the very next instruction is not skipped
Sorry I meant 'is skipped'.
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--- Comment #5 from Jatin Kumar ---
@Paolo: Thanks for the info. That makes sense to me.
(In reply to Jidong Xiao from comment #4)
> Jatin, are you using gdb to do the single step?(In reply to Jatin Kumar from
> comment #2)
No. I have been doing
From: Kim Phillips
Needed by platform device drivers, such as the vfio-platform driver
later in series, in order to bypass the existing OF, ACPI, id_table and
name string matches, and successfully be able to be bound to any
device, like so:
echo vfio-platform > /sys/bus/platform/devices/fff51000
On Tuesday 20 May 2014 16:47:10 Andreas Herrmann wrote:
> From: David Daney
>
> Signed-off-by: David Daney
> Signed-off-by: Andreas Herrmann
These look similar to the kvm_hypercall${n} functions in
arch/{x86,s390}/include/asm/kvm_para.h. Does it make sense to define that API
in kvm_para.h fo
On 05/20/2014 03:52 PM, James Hogan wrote:
Hi Andreas,
On Tuesday 20 May 2014 16:47:04 Andreas Herrmann wrote:
From: David Daney
CVMSEG is related to the CPU core not the SoC system. So needs to be
configurable there.
Signed-off-by: David Daney
Signed-off-by: Andreas Herrmann
---
arch/m
On Tuesday 20 May 2014 16:47:15 Andreas Herrmann wrote:
> Change CPU selection, enable SMP, enable almost all virtio options.
Looks like this should just be squashed into the previous patch if the
original defconfig was insufficient.
Cheers
James
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Description: This is a digitally s
Hi Andreas,
On Tuesday 20 May 2014 16:47:14 Andreas Herrmann wrote:
> From: David Daney
>
> Signed-off-by: David Daney
> Signed-off-by: Andreas Herrmann
> ---
> arch/mips/configs/mips_paravirt_defconfig | 1524
> + 1 file changed, 1524 insertions(+)
> create mode 1
Hi Andreas,
On Tuesday 20 May 2014 16:47:04 Andreas Herrmann wrote:
> From: David Daney
>
> CVMSEG is related to the CPU core not the SoC system. So needs to be
> configurable there.
>
> Signed-off-by: David Daney
> Signed-off-by: Andreas Herrmann
> ---
> arch/mips/cavium-octeon/Kconfig |
On 20/05/14 18:52, Pekka Enberg wrote:
> On 05/20/2014 02:20 PM, James Hogan wrote:
>> I don't know what Pekka's policy is for kvm tools, but to avoid
>> confusion I'd like to make clear that this patchset depends on a KVM
>> implementation (KVM_VM_TYPE==1 for VZ) which hasn't been accepted into
>>
The old stats contain information not available in the tracepoints.
Signed-off-by: Marcelo Tosatti
diff --git a/scripts/kvm/kvm_stat b/scripts/kvm/kvm_stat
index 762544b..6ac3b21 100755
--- a/scripts/kvm/kvm_stat
+++ b/scripts/kvm/kvm_stat
@@ -493,12 +493,21 @@ options.add_option('-f', '--field
https://bugzilla.kernel.org/show_bug.cgi?id=30402
--- Comment #3 from Joerg Roedel ---
(In reply to Jidong Xiao from comment #2)
> Joerg, how do you know this?
>
> "Some investigation showed that this kernel uses MMX instructions to access
> MMIO regions. These instructions are not emulated by t
https://bugzilla.kernel.org/show_bug.cgi?id=30402
Jidong Xiao changed:
What|Removed |Added
CC||jidong.x...@gmail.com
--- Comment #2 from J
https://bugzilla.kernel.org/show_bug.cgi?id=65561
--- Comment #4 from Jidong Xiao ---
Jatin, are you using gdb to do the single step?(In reply to Jatin Kumar from
comment #2)
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On 05/20/2014 02:20 PM, James Hogan wrote:
I don't know what Pekka's policy is for kvm tools, but to avoid
confusion I'd like to make clear that this patchset depends on a KVM
implementation (KVM_VM_TYPE==1 for VZ) which hasn't been accepted into
the mainline kernel yet.
Is that something that
In order to allow KVM to run on Cortex-A53 implementations, wire the
minimal support required.
Signed-off-by: Marc Zyngier
---
arch/arm64/include/asm/cputype.h | 1 +
arch/arm64/include/uapi/asm/kvm.h| 3 ++-
arch/arm64/kvm/guest.c | 2 ++
arch/arm64/kvm/sys_regs_generic_v8
Implement switching of the debug registers. While the number
of registers is massive, CPUs usually don't implement them all
(A57 has 6 breakpoints and 4 watchpoints, which gives us a total
of 22 registers "only").
Also, we only save/restore them when MDSCR_EL1 has debug enabled,
or when we've flag
This patch series adds debug support, a key feature missing from the
KVM/arm64 port.
The main idea is to keep track of whether the debug registers are
"dirty" (changed by the guest) or not. In this case, perform the usual
save/restore dance, for one run only. It means we only have a penalty
if a g
As we're about to trap a bunch of CP14 registers, let's rework
the CP15 handling so it can be generalized and work with multiple
tables.
Reviewed-by: Anup Patel
Signed-off-by: Marc Zyngier
---
arch/arm64/include/asm/kvm_asm.h| 2 +-
arch/arm64/include/asm/kvm_coproc.h | 3 +-
arch/arm64
Add handlers for all the AArch32 debug registers that are accessible
from EL0 or EL1. The code follow the same strategy as the AArch64
counterpart with regards to tracking the dirty state of the debug
registers.
Reviewed-by: Anup Patel
Signed-off-by: Marc Zyngier
---
arch/arm64/include/asm/kvm_
An interesting "feature" of the CP14 encoding is that there is
an overlap between 32 and 64bit registers, meaning they cannot
live in the same table as we did for CP15.
Create separate tables for 64bit CP14 and CP15 registers, and
let the top level handler use the right one.
Reviewed-by: Anup Pat
Enable trapping of the debug registers, preventing the guests to
mess with the host state (and allowing guests to use the debug
infrastructure as well).
Reviewed-by: Anup Patel
Signed-off-by: Marc Zyngier
---
arch/arm64/kvm/hyp.S | 8
1 file changed, 8 insertions(+)
diff --git a/arch/
In order to be able to use the DBG_MDSCR_* macros from the KVM code,
move the relevant definitions to the obvious include file.
Also move the debug_el enum to a portion of the file that is guarded
by #ifndef __ASSEMBLY__ in order to use that file from assembly code.
Acked-by: Will Deacon
Reviewe
pm_fake doesn't quite describe what the handler does (ignoring writes
and returning 0 for reads).
As we're about to use it (a lot) in a different context, rename it
with a (admitedly cryptic) name that make sense for all users.
Reviewed-by: Anup Patel
Signed-off-by: Marc Zyngier
---
arch/arm64
We now have multiple tables for the various system registers
we trap. Make sure we check the order of all of them, as it is
critical that we get the order right (been there, done that...).
Reviewed-by: Anup Patel
Signed-off-by: Marc Zyngier
---
arch/arm64/kvm/sys_regs.c | 22 +++
Add handlers for all the AArch64 debug registers that are accessible
from EL0 or EL1. The trapping code keeps track of the state of the
debug registers, allowing for the switch code to implement a lazy
switching strategy.
Reviewed-by: Anup Patel
Signed-off-by: Marc Zyngier
---
arch/arm64/includ
On Tue, May 20, 2014 at 12:24:58PM +0100, James Hogan wrote:
> On 19/05/14 17:53, Andreas Herrmann wrote:
> > This is is usually 0 for most archs. On mips we have two types.
> > TE (type 0) and MIPS-VZ (type 1). Default to 1 on mips.
>
> Minor thing I didn't spot with v1 (sorry).
> I think this pa
The driver_override field allows us to specify the driver for a device
rather than relying on the driver to provide a positive match of the
device. This shortcuts the existing process of looking up the vendor
and device ID, adding them to the driver new_id, binding the device,
then removing the ID
From: David Daney
Signed-off-by: David Daney
Signed-off-by: Andreas Herrmann
---
arch/mips/Kconfig|1 +
arch/mips/paravirt/Kconfig |6 ++
arch/mips/pci/Makefile |2 +-
arch/mips/pci/pci-virtio-guest.c | 140 ++
4
From: David Daney
Signed-off-by: David Daney
Signed-off-by: Andreas Herrmann
---
arch/mips/configs/mips_paravirt_defconfig | 1524 +
1 file changed, 1524 insertions(+)
create mode 100644 arch/mips/configs/mips_paravirt_defconfig
diff --git a/arch/mips/configs/mips
Signed-off-by: Andreas Herrmann
---
arch/mips/paravirt/setup.c |7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/mips/paravirt/setup.c b/arch/mips/paravirt/setup.c
index f80c3bc..6d2781c 100644
--- a/arch/mips/paravirt/setup.c
+++ b/arch/mips/paravirt/setup.c
@@ -8,6 +8,7 @@
#
From: David Daney
For para-virtualized guests running under KVM or other equivalent
hypervisor.
Signed-off-by: David Daney
Signed-off-by: Andreas Herrmann
---
.../asm/mach-paravirt/cpu-feature-overrides.h | 36 ++
arch/mips/include/asm/mach-paravirt/irq.h | 19 +
.../include
From: David Daney
Signed-off-by: David Daney
Signed-off-by: Andreas Herrmann
---
arch/mips/Kbuild.platforms |1 +
arch/mips/Kconfig | 19 +++
2 files changed, 20 insertions(+)
diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms
index 6e23912..f5
Change CPU selection, enable SMP, enable almost all virtio options.
Signed-off-by: Andreas Herrmann
---
arch/mips/configs/mips_paravirt_defconfig | 69 ++---
1 file changed, 33 insertions(+), 36 deletions(-)
diff --git a/arch/mips/configs/mips_paravirt_defconfig
b/arc
From: David Daney
Signed-off-by: David Daney
Signed-off-by: Andreas Herrmann
---
arch/mips/include/asm/mipsregs.h | 67 ++
1 file changed, 67 insertions(+)
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index f110d48..e12
Otherwise __builtin_unreachable might be called.
Signed-off-by: Andreas Herrmann
---
arch/mips/include/asm/cpu-type.h |1 +
1 file changed, 1 insertion(+)
diff --git a/arch/mips/include/asm/cpu-type.h b/arch/mips/include/asm/cpu-type.h
index 72190613..0bd77a0 100644
--- a/arch/mips/include/
From: David Daney
This returns the CPUNum from the low order Ebase bits.
Signed-off-by: David Daney
Signed-off-by: Andreas Herrmann
---
arch/mips/include/asm/mipsregs.h |5 +
1 file changed, 5 insertions(+)
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsreg
From: David Daney
These are needed to boot a generic mips64r2 kernel on OCTEONIII.
Signed-off-by: David Daney
Signed-off-by: Andreas Herrmann
---
arch/mips/include/asm/r4kcache.h |2 ++
arch/mips/mm/c-r4k.c | 32
2 files changed, 34 insertion
From: David Daney
The TLB handlers cannot handle this case, so disable it for now.
Signed-off-by: David Daney
Signed-off-by: Andreas Herrmann
---
arch/mips/include/asm/cpu-features.h |9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/mips/include/asm/cpu-featu
From: David Daney
CVMSEG is related to the CPU core not the SoC system. So needs to be
configurable there.
Signed-off-by: David Daney
Signed-off-by: Andreas Herrmann
---
arch/mips/cavium-octeon/Kconfig | 30 --
1 file changed, 20 insertions(+), 10 deletions(-)
From: David Daney
They are a property of the SoC not the CPU itself.
Signed-off-by: David Daney
Signed-off-by: Andreas Herrmann
---
arch/mips/Kconfig | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 5cd695f..de32ab5 1
From: David Daney
The fast handler only supports 64-bit kernels.
Signed-off-by: David Daney
Signed-off-by: Andreas Herrmann
---
arch/mips/mm/tlbex.c |8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index ee88367..781e18
From: David Daney
Some versions of the assembler will not assemble CFC1 for OCTEON, so
override the ISA for these.
Add r4k_fpu.o to handle low level FPU initialization.
Modify octeon_switch.S to save the FPU registers. And include
r4k_switch.S to pick up more FPU support.
Get rid of "#define
Hi,
Following patches add support for paravirtualized guest on mips
(mips_paravirt). Some of the patches add basic support to run it on
octeon3.
The core of mips_paravirt is David's work.
I rebased his code, rearranged it somewhat (e.g. split it into the
current patches) and added some minor modi
On 20.05.2014, at 11:59, Paul Mackerras wrote:
> On Mon, May 19, 2014 at 03:09:07PM +0200, Alexander Graf wrote:
>>
>> On 17.05.14 08:20, Paul Mackerras wrote:
>>> On Tue, Apr 29, 2014 at 06:17:42PM +0200, Alexander Graf wrote:
POWER8 introduces transactional memory which brings along a nu
On 19/05/14 17:53, Andreas Herrmann wrote:
> This is is usually 0 for most archs. On mips we have two types.
> TE (type 0) and MIPS-VZ (type 1). Default to 1 on mips.
Minor thing I didn't spot with v1 (sorry).
I think this patch should probably be moved before patch 6 with the mips
part squashed i
On 19/05/14 17:53, Andreas Herrmann wrote:
> Hi,
>
> These patches contain changes that I am currently using on top of
> git://github.com/penberg/linux-kvm.git (as of v3.13-rc1-1427-gd9147fb)
> to run lkvm on MIPS.
>
> The core is David's work for mips support and loading elf binaries.
>
> I reb
https://bugzilla.kernel.org/show_bug.cgi?id=65561
Paolo Bonzini changed:
What|Removed |Added
CC||bonz...@gnu.org
--- Comment #3 from Paolo
https://bugzilla.kernel.org/show_bug.cgi?id=53601
Bug 53601 depends on bug 45931, which changed state.
Bug 45931 Summary: Nested Virt: VMX can't be initialized in L1 Xen ("Xen on
KVM")
https://bugzilla.kernel.org/show_bug.cgi?id=45931
What|Removed |Added
-
https://bugzilla.kernel.org/show_bug.cgi?id=45931
Paolo Bonzini changed:
What|Removed |Added
Status|NEW |RESOLVED
CC|
On 20.05.14 12:02, Michael Mueller wrote:
On Mon, 19 May 2014 22:14:00 +0200
Alexander Graf wrote:
On 19.05.14 19:03, Michael Mueller wrote:
On Mon, 19 May 2014 16:49:28 +0200
Alexander Graf wrote:
[...]
What user and thus also user space wants depends on other factors:
1. reliability
On Mon, 19 May 2014 22:14:00 +0200
Alexander Graf wrote:
>
> On 19.05.14 19:03, Michael Mueller wrote:
> > On Mon, 19 May 2014 16:49:28 +0200
> > Alexander Graf wrote:
> >
> >> On 19.05.14 16:18, Michael Mueller wrote:
> >>> On Mon, 19 May 2014 13:48:08 +0200
> >>> Alexander Graf wrote:
> >>>
On Mon, May 19, 2014 at 03:09:07PM +0200, Alexander Graf wrote:
>
> On 17.05.14 08:20, Paul Mackerras wrote:
> >On Tue, Apr 29, 2014 at 06:17:42PM +0200, Alexander Graf wrote:
> >>POWER8 introduces transactional memory which brings along a number of new
> >>registers and MSR bits.
> >>
> >>Impleme
https://bugzilla.kernel.org/show_bug.cgi?id=75981
Zhou, Chao changed:
What|Removed |Added
Status|RESOLVED|VERIFIED
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Zhou, Chao changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|---
https://bugzilla.kernel.org/show_bug.cgi?id=75981
--- Comment #5 from Zhou, Chao ---
this commit fixed the bug:
commit d9f89b88f5102ce235b75a5907838e3c7ed84b97
Author: Jan Kiszka
Date: Sat May 10 09:24:34 2014 +0200
KVM: x86: Fix CR3 reserved bits check in long mode
Regression of 346
https://bugzilla.kernel.org/show_bug.cgi?id=75981
--- Comment #4 from Zhou, Chao ---
kvm.git + qemu.git: d9f89b88_e5bfd640
host kernel:3.15.0_rc1
test on Romley_EP, create a 64bit rhel6u5 guest as L2 guest, the L2 guest boots
up fine.
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Zhou, Chao changed:
What|Removed |Added
CC||chao.z...@intel.com
--- Comment #2 from Zhou
https://bugzilla.kernel.org/show_bug.cgi?id=65561
--- Comment #2 from Jatin Kumar ---
Hello Jidong, thanks for the info. I will try and let you know.
While you are at this, can you please help me another single stepping issue and
the issue is:
1. While single stepping, the instruction immediatel
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