Wanpeng Li wrote:
> 2015-11-20 10:52 GMT+08:00 Wanpeng Li :
>> Hi Paolo,
>> 2015-02-09 17:03 GMT+08:00 Paolo Bonzini :
>>> NoWrite instructions (e.g. cmp or test) never set the "write access"
>>> bit in the error code, even if one of the operands is treated as a
>>> destination.
>>
>> Sorry to r
Here are my 5 cents. Note that vmx_vcpu_reset calls:
vmcs_writel(GUEST_RFLAGS, 0x02);
(And the RFLAGS value is not cached by KVM, so no consistency problem should
occur.)
You may want to change the value into constant or call a wrapper function
for setting RFLAGS, but I don’t see somethi
Looking at the patch again, there two points you may want to change, see
inline.
If you want, I’ll send a v2.
Nadav
Nadav Amit wrote:
> From: Nadav Amit
>
> This adds support for guest data and I/O breakpoints during instruction
> emulation.
>
> Watchpoints are examined
From: Rami Burstein& Anrey Isakov
This adds a test for data and port watchpoints during instruction emulation.
Signed-off-by: Rami Burstein
Signed-off-by: Andrey Isakov
---
This unit tests are based on old kvm-unit-tests version and are only delivered
for reference. They are certainly bloate
From: Nadav Amit
This adds support for guest data and I/O breakpoints during instruction
emulation.
Watchpoints are examined during data and io interceptions: segmented_read,
segmented_write, em_in, em_out, segmented_read_std and kvm_fast_pio_out.
When such a breakpoint is triggered, trap is
From: Rami Burstein
Add DR_RW_PROT for I/O watchponts.
Signed-off-by: Andrey Isakov
Signed-off-by: Rami Burstein
Signed-off-by: Nadav Amit
---
arch/x86/include/uapi/asm/debugreg.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/include/uapi/asm/debugreg.h
b/arch/x86/include
some concerns about their
impact on performance, so it is possible to add a fast-patch for the case all
breakpoints are disabled. In addition, these patches do not handle watchpoints
that are set by the host debugger.
Nadav Amit (1):
KVM: x86: Guest watchpoints during emulation.
Rami Burstein
Sorry for misleading. I forgot there are several issues with the patches, so
I cannot send them. If I find the time (and you don’t implement it first),
I’ll fix and send them.
Nadav
Paolo Bonzini wrote:
>
>
> On 21/09/2015 14:26, Nadav Amit wrote:
>> Paolo,
>>
Paolo,
Two students here implemented emulated I/O and data breakpoints support for
KVM under my supervision. I mistakenly graded their project before they
actually sent the patches, and at this point (surprisingly) they
disappeared. The patches are relatively ok and include unit-tests. I also
ran
On Mon, 2015-04-13 at 02:32 +0300, Nadav Amit wrote:
>>>> Due to old Seabios bug, QEMU reenable LINT0 after reset. This bug is long
>>>> gone
>>>> and therefore this hack is no longer needed. Since it violates the
>>>> specifications, it is re
Bandan Das wrote:
>
> If get_free_page() fails for nested bitmap area, it's evident that
> we are gonna get screwed anyway but returning failure because we failed
> allocating memory for a nested structure seems like an unnecessary big
> hammer. Also, save the call for later; after we are done
Jan Kiszka wrote:
> Am 2015-04-28 um 13:43 schrieb Paolo Bonzini:
>> On 28/04/2015 13:42, Nadav Amit wrote:
>>> It seems strange that the guest is allowed to set IA32_DEBUGCTL MSR for the
>>> nested VM and get this value to the physical IA32_DEBUGCTL (see
>>>
It seems strange that the guest is allowed to set IA32_DEBUGCTL MSR for the
nested VM and get this value to the physical IA32_DEBUGCTL (see
prepare_vmcs02), while it cannot set IA32_DEBUGCTL for itself (see
kvm_set_msr_common).
Am I missing something?
Regards,
Nadav
--
To unsubscribe from this li
VMware appears to get it right.
Thanks for reviewing the patches.
Nadav Amit (2):
KVM: x86: Fix update RCX/RDI/RSI on REP-string
KVM: x86: Fix zero iterations REP-string
arch/x86/kvm/emulate.c | 33 +++--
1 file changed, 27 insertions(+), 6 deletions(-)
--
2.1.4
quot;);
TEST("0xa4");
TEST("0xa5");
TEST("0xa6");
TEST("0xa7");
TEST("0xaa");
TEST("0xab");
TEST("0xae");
TEST("0xaf");
}
Signed-off-by: Nadav Amit
---
: Nadav Amit
---
arch/x86/kvm/emulate.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c
index c1bc650..296d58e 100644
--- a/arch/x86/kvm/emulate.c
+++ b/arch/x86/kvm/emulate.c
@@ -524,13 +524,9 @@ static void masked_increment
The emulation of CMPXCHG with two register operands in 64-bit mistakenly masks
the high 32-bits as it performs assignment. Fix it.
Fixes: 2fcf5c8ae244b4c298d2111a288d410a719ac626
Signed-off-by: Nadav Amit
---
arch/x86/kvm/emulate.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/x86
instead of the one that was previously used. As a
bonus, the update of DR7 will now be effective for AMD as well.
Signed-off-by: Nadav Amit
---
v1 -> v2:
- Move the setting to emulate.c instead of x86.c
- Shorten title
---
arch/x86/kvm/emulate.c | 6 +-
arch/x86/kvm/vmx.c | 3 ---
2 fi
Paolo Bonzini wrote:
>
>
> On 19/04/2015 14:18, Nadav Amit wrote:
>> If the host sets hardware breakpoints to debug the guest, and a task-switch
>> occurs in the guest, the architectural DR7 will not be updated. The effective
>> DR7 would be updated instead.
>&g
Brad Campbell wrote:
>
> On 13/04/15 22:02, Paolo Bonzini wrote:
>> On 13/04/2015 14:45, Brad Campbell wrote:
>>> G'day Paolo,
>>>
>>> Yes, on AMD and I've tried hard to reproduce it on Intel and been unable
>>> to thus far.
>>>
>>> Now you mention it may be AMD specific, I have a spare mother
Hi,
I would appreciate if someone briefly explains the design choice that leaded
to separating the x86 emulator from the rest of x86 code, i.e., making it
oblivious to VCPUs and using the x86_emulate_ops as an interface.
Thanks,
Nadav
--
To unsubscribe from this list: send the line "unsubscribe k
update of DR7 will now be effective for AMD as
well.
Signed-off-by: Nadav Amit
---
arch/x86/kvm/vmx.c | 3 ---
arch/x86/kvm/x86.c | 3 +++
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index f7a0a7f..8f731c0 100644
--- a/arch/x86/kvm/vmx.c
Wanpeng Li wrote:
> Hi Nadav,
> On Thu, Apr 02, 2015 at 03:10:38AM +0300, Nadav Amit wrote:
>> CR2 is not cleared as it should after reset. See Intel SDM table named
>> "IA-32
>> Processor States Following Power-up, Reset, or INIT".
>
> How you trigger
Paolo Bonzini wrote:
>
>
> On 13/04/2015 16:17, Nadav Amit wrote:
>> Paolo Bonzini wrote:
>>
>>> On 13/04/2015 01:32, Nadav Amit wrote:
>>>> +if (kvm_check_extension(s, KVM_CAP_ENABLE_CAP_VM)) {
>>>
>>> The r
Paolo Bonzini wrote:
>
>
> On 13/04/2015 01:32, Nadav Amit wrote:
>> +if (kvm_check_extension(s, KVM_CAP_ENABLE_CAP_VM)) {
>
> The right capability to check here is KVM_CAP_DISABLE_QUIRKS, not
> KVM_CAP_ENABLE_CAP_VM.
>
> Paolo
>
>
Paolo,
I hope I am not misleading or interrupting, and I am obviously very biased —
but couldn’t it be related to the issue that patch f210f7572bed ("KVM: x86:
Fix lost interrupt on irr_pending race”) deals with?
I got this issue first when I upgraded to 3.17 in my testing environment,
since appa
Thanks. If you want a test-case you can apply/try the following on top of
the previous kvm-unit-tests patch-set I sent
( http://www.spinics.net/lists/kvm/msg115525.html ).
Regards,
Nadav
-- >8 --
From: Nadav Amit
Subject: [PATCH kvm-unit-tests] x86: Test LINT0 is disabled after re
t; [10.4.7.3: Local APIC State After an INIT Reset
(“Wait-for-SIPI” State)]
Signed-off-by: Nadav Amit
---
v3:
- Leave EFER unchanged on INIT. Instead, set cr0 correctly so vmx_set_cr0 would
recognize that paging was changed from on to off and clear LMA.
- Clean the surrounding from unneca
Due to old Seabios bug, QEMU reenable LINT0 after reset. This bug is long gone
and therefore this hack is no longer needed. Since it violates the
specifications, it is removed.
Signed-off-by: Nadav Amit
---
hw/intc/apic_common.c | 9 -
1 file changed, 9 deletions(-)
diff --git a/hw
NW from
CR0 after reset.
Thanks for reviewing these patches.
Nadav Amit (2):
target-i386: disable LINT0 after reset
target-i386: kvm: Disable KVM quirks
hw/intc/apic_common.c | 9 -
linux-headers/asm-x86/kvm.h | 4
linux-headers/linux/kvm.h | 1 +
target-i386/kvm.c
KVM has quirks to overcome legacy QEMU bugs that are already resolved. Using a
new KVM feature for disabling these quirks.
Signed-off-by: Nadav Amit
---
linux-headers/asm-x86/kvm.h | 4
linux-headers/linux/kvm.h | 1 +
target-i386/kvm.c | 8
3 files changed, 13
. KVM_QUIRK_CD_NW_CLEARED - CD and NW are cleared after boot
These two issues are already resolved in recent releases of QEMU, and would
therefore be disabled by QEMU.
Signed-off-by: Nadav Amit
---
Documentation/virtual/kvm/api.txt | 3 ++-
arch/x86/include/asm/kvm_host.h | 2 ++
arch/x86/include/uapi
kvm_init_msr_list is currently called before hardware_setup. As a result,
vmx_mpx_supported always returns false when kvm_init_msr_list checks whether to
save MSR_IA32_BNDCFGS.
Move kvm_init_msr_list after vmx_hardware_setup is called to fix this issue.
Signed-off-by: Nadav Amit
---
Note that
Paolo Bonzini wrote:
>
>
> On 09/04/2015 21:17, Bandan Das wrote:
>>> Excluding (1) all of the other issues are related to the VM BIOS. Perhaps
>>> KVM should somehow realize which VM BIOS runs? (yes, it sounds just as bad.)
>>
>> How about renaming the toggle Avi mentioned above to something
Avi Kivity wrote:
> On 04/09/2015 09:21 PM, Nadav Amit wrote:
>> Bandan Das wrote:
>>
>>> Nadav Amit writes:
>>>
>>>> Jan Kiszka wrote:
>>>>
>>>>> On 2015-04-08 19:40, Nadav Amit wrote:
>>>>>> Jan
Bandan Das wrote:
> Nadav Amit writes:
>
>> Jan Kiszka wrote:
>>
>>> On 2015-04-08 19:40, Nadav Amit wrote:
>>>> Jan Kiszka wrote:
>>>>
>>>>> On 2015-04-08 18:59, Nadav Amit wrote:
>>>>>> J
Jan Kiszka wrote:
> On 2015-04-08 19:40, Nadav Amit wrote:
>> Jan Kiszka wrote:
>>
>>> On 2015-04-08 18:59, Nadav Amit wrote:
>>>> Jan Kiszka wrote:
>>>>
>>>>> On 2015-04-08 18:40, Nadav Amit wrote:
>>>>>>
Jan Kiszka wrote:
> On 2015-04-08 18:59, Nadav Amit wrote:
>> Jan Kiszka wrote:
>>
>>> On 2015-04-08 18:40, Nadav Amit wrote:
>>>> Hi,
>>>>
>>>> I would appreciate if someone explains the reason for enabling LINT0 during
>>
Jan Kiszka wrote:
> On 2015-04-08 18:40, Nadav Amit wrote:
>> Hi,
>>
>> I would appreciate if someone explains the reason for enabling LINT0 during
>> APIC reset. This does not correspond with Intel SDM Figure 10-8: “Local
>> Vector Table” that says all L
Hi,
I would appreciate if someone explains the reason for enabling LINT0 during
APIC reset. This does not correspond with Intel SDM Figure 10-8: “Local
Vector Table” that says all LVT registers are reset to 0x1.
In kvm_lapic_reset, I see:
apic_set_reg(apic, APIC_LVT0,
Sorry for that - fixes 0efb04406de834d820f7ba150a00d1d3194aa8a6 ("KVM: x86:
removing redundant eflags bits definitions”).
Nadav
Wanpeng Li wrote:
> Guest can't be booted w/ ept=0, there is a message dumped as below:
>
> If you're running a guest on an Intel machine without unrestricted mode
>
Checking the reset values of dr0, cr2 and sysenter_eip after reset. Since INIT
does not initialize certain registers, we keep for each state whether it is
INIT or not. It is also required for the next patch.
Signed-off-by: Nadav Amit
---
x86/init.c | 55
Testing whether changing the BSP, followed by INIT works correctly. The APIC ID
is saved after resume and compared. For this test to pass, a fix of QEMU is
needed in addition to a KVM fix.
Signed-off-by: Nadav Amit
---
x86/init.c| 77
Reenabling init tests. Disabling the tests of port 0x92 since it currently
fails.
Signed-off-by: Nadav Amit
---
x86/init.c| 6 ++
x86/unittests.cfg | 4 ++--
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/x86/init.c b/x86/init.c
index 344dc1c..717bd12 100644
--- a
Reenabling the init tests in order to check whether the registers are set
correctly after reset, and to check whether the BSP can be changed from the VM.
Thanks for reviewing the patches.
Nadav Amit (4):
x86: move some common functions to processor.h
x86: Reenable init tests
x86: check
Moving some code for reading/writing drs to processor.h. The names of the
functions are changed to be consistent with others. While we are at it, fixing
lldt so it would work.
Signed-off-by: Nadav Amit
---
lib/x86/processor.h | 19 ++-
x86/debug.c | 36
CR2 is not cleared as it should after reset. See Intel SDM table named "IA-32
Processor States Following Power-up, Reset, or INIT".
Signed-off-by: Nadav Amit
---
arch/x86/kvm/x86.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
ind
o not cause the MP
protocol to be repeated."
[Intel SDM 8.4.2: MP Initialization Protocol Requirements and Restrictions]
Signed-off-by: Nadav Amit
---
arch/x86/kvm/lapic.c | 2 --
arch/x86/kvm/svm.c | 2 +-
arch/x86/kvm/vmx.c | 2 +-
arch/x86/kvm/x86.c | 2 +-
inc
QEMU initiates
the RESET) and CR2 not cleared after INIT.
The second patch regarding BSP requires an additional fix for QEMU, as
otherwise reset fails. A separate patch was submitted to QEMU mailing-list.
Thanks for reviewing the patches.
Nadav Amit (4):
KVM: x86: INIT and reset sequences are
DR0-DR3 are not cleared as they should during reset and when they are set from
userspace. It appears to be caused by c77fb5fe6f03 ("KVM: x86: Allow the guest
to run with dirty debug registers").
Force their reload on these situations.
Signed-off-by: Nadav Amit
---
arch/x86/i
7 FPU INITIALIZATION]
"The state of the local APIC following an INIT reset is the same as it is after
a power-up or hardware reset, except that the APIC ID and arbitration ID
registers are not affected." [10.4.7.3: Local APIC State After an INIT Reset
(“Wait-for-SIPI” State)]
Signed-off
Paolo Bonzini wrote:
> On 30/03/2015 16:40, Nadav Amit wrote:
>> Paolo,
>>
>> It appears you are right and I have not tested 4 and 5 well enough. I’ll
>> repost them (the others were tested presumably well enough).
>>
>> Two short questions:
>> Can
Paolo,
It appears you are right and I have not tested 4 and 5 well enough. I’ll
repost them (the others were tested presumably well enough).
Two short questions:
Can I use init.c in the kvm-unit-tests ?
Why is it disabled?
Nadav
Paolo Bonzini wrote:
>
>
> On 30/03/2015 14:39, N
If the source of BSF and BSR is zero, the destination register should not
change. That is how real hardware behaves. If we set the destination even with
the same value that we had before, we may clear bits [63:32] unnecassarily.
Signed-off-by: Nadav Amit
---
arch/x86/kvm/emulate.c | 19
o not cause the MP
protocol to be repeated."
[Intel SDM 8.4.2: MP Initialization Protocol Requirements and Restrictions]
Signed-off-by: Nadav Amit
---
arch/x86/kvm/lapic.c | 2 --
arch/x86/kvm/svm.c | 2 +-
arch/x86/kvm/vmx.c | 2 +-
include/linux/kvm_host.h | 7 ++-
4 files
On legacy mode CMOV emulation should still clear bits [63:32] even if the
assignment is not done. The previous fix 140bad89fd ("KVM: x86: emulation of
dword cmov on long-mode should clear [63:32]") was incomplete.
Signed-off-by: Nadav Amit
---
arch/x86/kvm/emulate.c | 3 +--
1 file
t; [10.4.7.3: Local APIC State After an INIT Reset
(“Wait-for-SIPI” State)]
Signed-off-by: Nadav Amit
---
arch/x86/include/asm/kvm_host.h | 6 +++---
arch/x86/kvm/lapic.c| 11 ++-
arch/x86/kvm/lapic.h| 2 +-
arch/x86/kvm/svm.c | 2 +-
arch/x
This patch-set handles 2 issues. Patches 1-3 deal with some more cases in which
bits [63:32] are not cleared when using dword opsize. Patches 4-5 handle
anomalies with INIT/BSP (INIT does not behave exactly as reset).
Thanks for reviewing the patches.
Nadav Amit (5):
KVM: x86: CMOV emulation
POPA should assign the values to the registers as usual registers are assigned.
In other words, 32-bits register assignments should clear bits [63:32] of the
register.
Split the code of register assignments that will be used by future changes as
well.
Signed-off-by: Nadav Amit
---
arch/x86/kvm
There are several redundant definitions in processor-flags.h and emulator.c.
Slowly, but surely they will get mixed, so removing those of emulator.c seems
like a reasonable move (unless I am missing something, e.g., kvm-kmod
consideration).
Nadav Amit (2):
KVM: x86: removing redundant eflags
Some constants are redfined in emulate.c. Avoid it.
s/SELECTOR_RPL_MASK/SEGMENT_RPL_MASK
s/SELECTOR_TI_MASK/SEGMENT_TI_MASK
No functional change.
Signed-off-by: Nadav Amit
---
arch/x86/include/asm/kvm_host.h | 3 ---
arch/x86/kvm/emulate.c | 6 +++---
arch/x86/kvm/vmx.c
The eflags are redefined (using other defines) in emulate.c.
Use the definition from processor-flags.h as some mess already started.
No functional change.
Signed-off-by: Nadav Amit
---
arch/x86/include/asm/kvm_host.h | 2 -
arch/x86/kvm/emulate.c | 105
Avi Kivity wrote:
> On 03/09/2015 07:51 PM, Nadav Amit wrote:
>> Avi Kivity wrote:
>>
>>> On 03/03/2015 11:52 AM, Paolo Bonzini wrote:
>>>>> In this
>>>>> case, the VM might expect exceptions when PTE bits which are higher than
>>&g
Avi Kivity wrote:
> On 03/03/2015 11:52 AM, Paolo Bonzini wrote:
>>> In this
>>> case, the VM might expect exceptions when PTE bits which are higher than the
>>> maximum (reported) address width are set, and it would not get such
>>> exceptions. This problem can easily be experienced by small cha
Paolo,
Thanks for the feedback. One small comment below.
Paolo Bonzini wrote:
>
>
> On 03/03/2015 09:34, Nadav Amit wrote:
>> I got two conformance issues in x86/KVM. For the first one I have no
>> solution. For the latter, my solution is not “great”. Ideas and
I got two conformance issues in x86/KVM. For the first one I have no
solution. For the latter, my solution is not “great”. Ideas and feedback
would be appreciated.
The first problem is caused by the deprecating of FPU CS/DS in new Intel
CPUs. Assume the VM executes a floating point instruction in
Marcello, Radim,
As you know - I can run some tests on the patches and whether they comply
with real hardware. Please let me know which version to test and I’ll try to
do next week.
Regards,
Nadav
Marcelo Tosatti wrote:
> Radim,
>
> On Thu, Feb 12, 2015 at 07:41:30PM +0100, Radim Krčmář wrote
ination.
>
> Fixes: c205fb7d7d4f81e46fc577b707ceb9e356af1456
> Cc: Nadav Amit
> Signed-off-by: Paolo Bonzini
> ---
> arch/x86/kvm/emulate.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c
> index 81dcf7964701..a943bf0c06d0 10064
Unnecassary define was left after commit 7d882ffa81d5 ("KVM: x86: Revert
NoBigReal patch in the emulator”).
Commit 39f062ff51b2 ("KVM: x86: Generate #UD when memory operand is required”)
was missing undef.
Fix it.
Signed-off-by: Nadav Amit
---
arch/x86/kvm/emulate.c | 2 +-
1 file
).
Introduce a group to the emulator to handle instructions according to execution
mode (32/64 bits). Note: in order not to make changes that may affect
performance, the new ModeDual can only be applied to instructions with ModRM.
Signed-off-by: Nadav Amit
---
arch/x86/kvm/emulate.c | 32
The IRET instruction should clear NMI masking, but the current implementation
does not do so.
Signed-off-by: Nadav Amit
---
arch/x86/include/asm/kvm_emulate.h | 1 +
arch/x86/kvm/emulate.c | 1 +
arch/x86/kvm/x86.c | 6 ++
3 files changed, 8 insertions(+)
diff
On long-mode, when far call that changes cs.l takes place, the stack size is
determined by the new mode. For instance, if we go from 32-bit mode to 64-bit
mode, the stack-size if 64. KVM uses the old stack size.
Fix it.
Signed-off-by: Nadav Amit
---
arch/x86/kvm/emulate.c | 25
chg failed.
Signed-off-by: Nadav Amit
---
arch/x86/kvm/emulate.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c
index ef23c1e..aa27254 100644
--- a/arch/x86/kvm/emulate.c
+++ b/arch/x86/kvm/emulate.c
@@ -2205,12 +2205,15 @@
If we got a wraparound of 32-bit operand, and the limit is 0x, read and
writes should be successful. It just needs to be done in two segments.
Signed-off-by: Nadav Amit
---
arch/x86/kvm/emulate.c | 10 +++---
arch/x86/kvm/x86.c | 2 ++
2 files changed, 9 insertions(+), 3
ca 14 00lret $0x14
4004f4: 48 cb lretq
4004f6: 48 ca 14 00 lretq $0x14
Therefore, remove the Stack flag from far-ret instructions.
Signed-off-by: Nadav Amit
---
arch/x86/kvm/emulate.c | 4 ++--
1 file changed, 2 insertions(+), 2
Sorry for sending patches at the last minute. There is nothing critical in this
patch-set. Yet, if you may want to incorporate something in 3.20 -
specifically 5 (small define mistakes) or 7 (which is somewhat affected by
recent changes).
Thanks for reviewing the patches.
Nadav Amit (7):
KVM
Radim Kr?má? wrote:
> 2015-01-14 01:27+, Wu, Feng:
>>> the new
hardware even doesn't consider the TPR for lowest priority interrupts
>>> delivery.
>>>
>>> A bold move ... what hardware was the first to do so?
>>
>> I think it was starting with Nehalem.
>
> Thanks, (Could be that QPI
Feng wrote:
>
>
>> -Original Message-
>> From: kvm-ow...@vger.kernel.org [mailto:kvm-ow...@vger.kernel.org] On
>> Behalf Of Nadav Amit
>> Sent: Thursday, December 25, 2014 5:55 PM
>> To: Chen, Tiejun
>> Cc: Paolo Bonzini; kvm list
>> Subj
Feng wrote:
>
>
>> -Original Message-
>> From: kvm-ow...@vger.kernel.org [mailto:kvm-ow...@vger.kernel.org] On
>> Behalf Of Nadav Amit
>> Sent: Thursday, December 25, 2014 8:52 AM
>> To: pbonz...@redhat.com
>> Cc: kvm@vger.kernel.org; Nadav
Tiejun wrote:
> On 2014/12/25 8:52, Nadav Amit wrote:
>> Although pop sreg updates RSP according to the operand size, only 2 bytes are
>> read. The current behavior may result in incorrect #GP or #PF exceptions.
>>
>> Signed-off-by: Nadav Amit
>> ---
>>
: Nadav Amit
---
arch/x86/kvm/emulate.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c
index 702da5e..19923e7 100644
--- a/arch/x86/kvm/emulate.c
+++ b/arch/x86/kvm/emulate.c
@@ -86,6 +86,7 @@
#define DstAcc (OpAcc
When segment is loaded, the segment access bit is set unconditionally. In
fact, it should be set conditionally, based on whether the segment had the
accessed bit set before. In addition, it can improve performance.
Signed-off-by: Nadav Amit
---
arch/x86/kvm/emulate.c | 11 +++
1 file
es (64-bit mode and
compatibility mode)."
So in other cases, we need to truncate. Creating new function to return a
pointer to descriptor table to avoid too much code duplication.
Signed-off-by: Nadav Amit
---
arch/x86/kvm/emulate.c | 45 -
d to waste another
of the precious instruction flags and to check the flag in decode_modrm.
Signed-off-by: Nadav Amit
---
arch/x86/kvm/emulate.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c
index 7f80f01..7bf3548 100644
---
Currently, if em_call_far fails it returns success instead of the resulting
error-code. Fix it.
Signed-off-by: Nadav Amit
---
arch/x86/kvm/emulate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c
index fd89471..7f80f01 100644
better one.
The fourth (JMP/CALL using call- or task-gate) is not a fix, but returns an
error instead of emulating the wrong (#GP) exception.
Thanks for reviewing the patches.
Nadav Amit (8):
KVM: x86: #PF error-code on R/W operations is wrong
KVM: x86: pop sreg accesses only 2 bytes
KVM: x86
the exception
is a write one. This does not conform with real hardware, and may cause the VM
to enter the page-fault handler twice for no reason (once for read, once for
write).
Signed-off-by: Nadav Amit
---
arch/x86/include/asm/kvm_host.h | 12
arch/x86/kvm/emulate.c | 6
The KVM emulator does not emulate JMP and CALL that target a call gate or a
task gate. This patch does not try to implement these scenario as they are
presumably rare; yet it returns X86EMUL_UNHANDLEABLE error in such cases
instead of generating an exception.
Signed-off-by: Nadav Amit
---
arch
Although pop sreg updates RSP according to the operand size, only 2 bytes are
read. The current behavior may result in incorrect #GP or #PF exceptions.
Signed-off-by: Nadav Amit
---
arch/x86/kvm/emulate.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kvm
I encountered an interesting and annoying problem when KVM uses
XSAVES/XRSTORS.
The problem results from the fact XSAVES does not save the exact value of
XINUSE[1]. See Intel SDM 13.10 “Operation of XSAVES”: “...if RFBM[1] = 1 and
MXCSR does not have the value 1F80H, XSAVEC writes XSTATE_BV[1] as
The pushf instruction does not push eflags.VM, so emulation should not do so as
well. Although eflags.RF should not be pushed as well, it is already cleared
by the time pushf is executed.
Signed-off-by: Nadav Amit
---
arch/x86/kvm/emulate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion
Two minor fixes for emulation of instructions on VM86.
Thanks for reviewing them.
Nadav Amit (2):
KVM: x86: Do not push eflags.vm on pushf
KVM: x86: Emulate should check #UD before #GP
arch/x86/kvm/emulate.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
--
1.9.1
Intel SDM table 6-2 ("Priority Among Simultaneous Exceptions and Interrupts")
shows that faults from decoding the next instruction got higher priority than
general protection. Moving the protected-mode check before the CPL check to
avoid wrong exception on vm86 mode.
Signed-off-by:
The macro GP already sets the flag Prefix. Remove the redundant flag for
0f_38_f0 and 0f_38_f1 opcodes.
Signed-off-by: Nadav Amit
---
arch/x86/kvm/emulate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c
index 3817334
test_conforming_switch in the taskswitch2 tests, miss es initialization.
Fix it.
Signed-off-by: Nadav Amit
---
x86/taskswitch2.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/x86/taskswitch2.c b/x86/taskswitch2.c
index f55843c..db3e41a 100644
--- a/x86/taskswitch2.c
Wanpeng Li wrote:
> XSAVEC also use the compacted format for the extended region
> of the XSAVE area. This patch fix it by caculate the size of
> XSAVEC extended region of XSAVE area as compact format.
>
> Signed-off-by: Wanpeng Li
> ---
> arch/x86/kvm/cpuid.c | 2 +-
> 1 file changed, 1 insert
ut the kernel will pass it to XRSTORS, and we need to convert back.
>
> Fixes: f31a9f7c71691569359fa7fb8b0acaa44bce0324
> Cc: Fenghua Yu
> Cc: H. Peter Anvin
> Cc: Nadav Amit
> Signed-off-by: Paolo Bonzini
> ---
> arch/x86/kvm/x86.c | 87 +
Radim Krčmář wrote:
> 2014-11-26 19:01+0200, Nadav Amit:
>> Sorry for the late and long reply, but I got an issue with the new version
>> (and my previous version as well). Indeed, the SDM states that DFR should
>> be the same for enabled CPUs, and that the BIOS should get
Radim Krčmář wrote:
> 2014-11-27 21:53+0200, Nadav Amit:
>> Radim Krčmář wrote:
>>> - new->cid_mask = (1 << KVM_X2APIC_CID_BITS) - 1;
>>> - new->lid_mask = 0x;
>>> + new->cid_mask = ne
Radim Krčmář wrote:
> While fixing an x2apic bug,
> 17d68b7 KVM: x86: fix guest-initiated crash with x2apic (CVE-2013-6376)
> we've made only one cluster available. This means that the amount of
> logically addressible x2APICs was reduced to 16 and VCPUs kept
> overwriting themselves in that reg
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