off-by: Andrey Smetanin <asmeta...@virtuozzo.com>
> CC: Paolo Bonzini <pbonz...@redhat.com>
> CC: Gleb Natapov <g...@kernel.org>
> CC: James Hogan <james.ho...@imgtec.com>
> CC: Paolo Bonzini <pbonz...@redhat.com>
> CC: Paul Burton <paul.bur...@i
off-by: Andrey Smetanin <asmeta...@virtuozzo.com>
> CC: Paolo Bonzini <pbonz...@redhat.com>
> CC: Gleb Natapov <g...@kernel.org>
> CC: James Hogan <james.ho...@imgtec.com>
> CC: Paolo Bonzini <pbonz...@redhat.com>
> CC: Paul Burton <paul.bur...@i
Implement saving and restoring to KVM state of the Processor ID (PRid)
CP0 register. This allows QEMU to control the PRid exposed to the guest
instead of using the default set by KVM.
Signed-off-by: James Hogan <james.ho...@imgtec.com>
Reviewed-by: Leon Alrae <leon.al...@imgtec.com&g
that QEMU can
save/restore the guest modifiable bits (Config5.FRE, Config5.UFR,
Config5.UFE). The FCSR/FIR registers and the floating point registers
are now saved/restored (depending on the FR mode bit).
Signed-off-by: James Hogan <james.ho...@imgtec.com>
Cc: Paolo Bonzini <pbonz...@redha
.MSAP) and so that QEMU can
save/restore the guest modifiable bits (Config5.MSAEn). The MSACSR/MSAIR
registers and the MSA vector registers are now saved/restored. Since the
FP registers are a subset of the vector registers, they are omitted if
the guest has MSA.
Signed-off-by: James Hogan <james
Rename kvm_mips_{get,put}_one_reg64() to kvm_mips_{get,put}_one_ureg64()
since they take an int64_t pointer, and add separate signed 64-bit
accessors. These will be used for double precision floating point
registers.
Signed-off-by: James Hogan <james.ho...@imgtec.com>
Cc: Paolo Bonzini
fig4 and
Config5 in patch 5 (Leon).
- Change (1 << x) to (1U << x) in important places in patch 5, 8 & 9 to
avoid compiler undefined behaviour (Leon).
James Hogan (7):
mips/kvm: Remove a couple of noisy DPRINTFs
mips/kvm: Implement PRid CP0 register
mips/kvm: Impleme
Add KVM register access functions for the uint32_t type. This is
required for FP and MSA control registers, which are represented as
unsigned 32-bit integers.
Signed-off-by: James Hogan <james.ho...@imgtec.com>
Cc: Paolo Bonzini <pbonz...@redhat.com>
Cc: Leon Alrae <leon.al...
The DPRINTFs in cpu_mips_io_interrupts_pending() and kvm_arch_pre_run()
are particularly noisy during normal execution, and also not
particularly helpful. Remove them so that more important debug messages
can be more easily seen.
Signed-off-by: James Hogan <james.ho...@imgtec.com>
Re
them on migration/savevm.
Signed-off-by: James Hogan <james.ho...@imgtec.com>
Cc: Paolo Bonzini <pbonz...@redhat.com>
Cc: Leon Alrae <leon.al...@imgtec.com>
Cc: Aurelien Jarno <aurel...@aurel32.net>
---
Changes in v2:
- Fix line wrapping of kvm_mips_get_one_reg() calls fr
Hi Paolo.
On Thu, Dec 17, 2015 at 11:39:14AM +0100, Paolo Bonzini wrote:
>
>
> On 17/12/2015 00:49, James Hogan wrote:
> > This patchset contains a bunch of miscellaneous cleanups (which are
> > mostly trivial) for MIPS KVM & MIPS headers, such as:
> > - Style
A bunch of misc whitespace and style fixes within arch/mips/kvm/.
Signed-off-by: James Hogan <james.ho...@imgtec.com>
Cc: Paolo Bonzini <pbonz...@redhat.com>
Cc: Ralf Baechle <r...@linux-mips.org>
Cc: Gleb Natapov <g...@kernel.org>
Cc: kvm@vger.kernel.org
Cc: linux-m...@
Some definitions in the MIPS asm/kvm_host.h are completely unused, so
lets drop them.
MS_TO_NS is no longer used since commit e30492bbe95a ("MIPS: KVM:
Rewrite count/compare timer emulation"). The others don't appear ever to
have been used.
Signed-off-by: James Hogan <james.ho...@i
/ so they can be shared with the rest of
arch/mips. Specifically COP0 register bits, exception codes, cache
ops, & instruction opcodes.
- Add MAINTAINERS entry for MIPS KVM.
Due to the interaction with other arch/mips/ code, I think it makes
sense for these to go via the MIPS tree.
James H
into parts where it makes sense to do so, and
add masks for the Cache and Op field within the cache op.
Signed-off-by: James Hogan <james.ho...@imgtec.com>
Cc: Ralf Baechle <r...@linux-mips.org>
Cc: linux-m...@linux-mips.org
---
arch/mips/include/asm/cach
I've pretty much been maintaining KVM for MIPS for a while now. Lets
make it more official (and make sure I get Cc'd on relevant patches).
Signed-off-by: James Hogan <james.ho...@imgtec.com>
Cc: Ralf Baechle <r...@linux-mips.org>
Cc: Paolo Bonzini <pbonz...@redhat.com>
C
Make consistent use of uint8_t in MMIO handling code.
Signed-off-by: James Hogan <james.ho...@imgtec.com>
Cc: Paolo Bonzini <pbonz...@redhat.com>
Cc: Ralf Baechle <r...@linux-mips.org>
Cc: Gleb Natapov <g...@kernel.org>
Cc: linux-m...@linux-mips.org
Cc: kvm@vger.kerne
Drop the custom cache operation code definitions used by KVM for
emulating guest CACHE instructions, and switch to use the existing
definitions in .
Signed-off-by: James Hogan <james.ho...@imgtec.com>
Cc: Paolo Bonzini <pbonz...@redhat.com>
Cc: Gleb Natapov <g...@kernel.org>
C
manual, and wait_op was already added to inst.h in commit b0a3eae2b943
("MIPS: inst.h: define COP0 wait op"), merged in v3.16-rc1.
Signed-off-by: James Hogan <james.ho...@imgtec.com>
Cc: Ralf Baechle <r...@linux-mips.org>
Cc: Paolo Bonzini <pbonz...@redhat.com>
Cc: Gleb
the offset
of the specific register within the commpage.
Signed-off-by: James Hogan <james.ho...@imgtec.com>
Cc: Paolo Bonzini <pbonz...@redhat.com>
Cc: Ralf Baechle <r...@linux-mips.org>
Cc: Gleb Natapov <g...@kernel.org>
Cc: linux-m...@linux-mips.org
Cc: kvm@vger.kernel.org
---
The module init and exit functions have no need to be global, so make
them static.
Signed-off-by: James Hogan <james.ho...@imgtec.com>
Cc: Paolo Bonzini <pbonz...@redhat.com>
Cc: Ralf Baechle <r...@linux-mips.org>
Cc: Gleb Natapov <g...@kernel.org>
Cc: kvm@vger.kernel.
Export symbols only to GPL modules to match other KVM symbols in
virt/kvm/ and arch/*/kvm/.
Signed-off-by: James Hogan <james.ho...@imgtec.com>
Cc: Paolo Bonzini <pbonz...@redhat.com>
Cc: Ralf Baechle <r...@linux-mips.org>
Cc: Gleb Natapov <g...@kernel.org>
Cc: linux-m..
The first argument to set_except_vector is the ExcCode, which we now
have definitions for. Lets make use of them.
Signed-off-by: James Hogan <james.ho...@imgtec.com>
Cc: Ralf Baechle <r...@linux-mips.org>
Cc: linux-m...@linux-mips.org
---
arch/mips/kernel/cpu-bugs64.c | 8 +++---
Add a few missing trap codes, and drop a couple of unused definitions
for virtual coherency that aren't in the latest architecture revisions.
Signed-off-by: James Hogan <james.ho...@imgtec.com>
Cc: Ralf Baechle <r...@linux-mips.org>
Cc: linux-m...@linux-mips.org
---
arch/mips
Add missing newline to end of kvm_err string when guest PMAP couldn't be
allocated.
Signed-off-by: James Hogan <james.ho...@imgtec.com>
Cc: Gleb Natapov <g...@kernel.org>
Cc: Paolo Bonzini <pbonz...@redhat.com>
Cc: Ralf Baechle <r...@linux-mips.org>
Cc: kvm@vger.kernel.
Move the Cause.ExcCode trap code definitions from kvm_host.h to
mipsregs.h, since they describe architectural bits rather than KVM
specific constants, and change the prefix from T_ to EXCCODE_.
Signed-off-by: James Hogan <james.ho...@imgtec.com>
Cc: Ralf Baechle <r...@linux-mips.org&g
The function kvm_mips_host_tlb_inv_index() is unused, so drop it
completely.
Signed-off-by: James Hogan <james.ho...@imgtec.com>
Cc: Ralf Baechle <r...@linux-mips.org>
Cc: Gleb Natapov <g...@kernel.org>
Cc: Paolo Bonzini <pbonz...@redhat.com>
Cc: linux-m...@linux-mips.org
The CAUSEB_DC and CAUSEF_DC definitions used by KVM are defined in
asm/kvm_host.h, but all the other Cause register field definitions are
found in asm/mipsregs.h.
Lets reunite the DC bit definitions with its friends in mipsregs.h.
Signed-off-by: James Hogan <james.ho...@imgtec.com>
Cc
. Note, this assembly is specific to the trap &
emulate implementation of KVM, so it doesn't need to check the
supervisor bit as that mode is not implemented in the guest.
Fixes: b680f70fc111 ("KVM/MIPS32: Entry point for trampolining to...")
Signed-off-by: James Hogan <james.ho...@img
("KVM/MIPS32: MIPS arch specific APIs for KVM")
Signed-off-by: James Hogan <james.ho...@imgtec.com>
Cc: Ralf Baechle <r...@linux-mips.org>
Cc: Paolo Bonzini <pbonz...@redhat.com>
Cc: Gleb Natapov <g...@kernel.org>
Cc: linux-m...@linux-mips.org
Cc: kvm@vger.kerne
ranch
emulation.")
Signed-off-by: James Hogan <james.ho...@imgtec.com>
Cc: Ralf Baechle <r...@linux-mips.org>
Cc: Paolo Bonzini <pbonz...@redhat.com>
Cc: Gleb Natapov <g...@kernel.org>
Cc: linux-m...@linux-mips.org
Cc: kvm@vger.kernel.org
Signed-off-by: Paolo Bonzin
. Note, this assembly is specific to the trap &
emulate implementation of KVM, so it doesn't need to check the
supervisor bit as that mode is not implemented in the guest.
Fixes: b680f70fc111 ("KVM/MIPS32: Entry point for trampolining to...")
Signed-off-by: James Hogan <james.ho...@img
Hi Paolo,
On Wed, Nov 11, 2015 at 03:43:14PM +0100, Paolo Bonzini wrote:
> On 11/11/2015 15:21, James Hogan wrote:
> > A few misc MIPS KVM fixes for issues that have been around since the
> > code was merged in v3.10.
> >
> > James Hogan (3):
> > MIPS
A few misc MIPS KVM fixes for issues that have been around since the
code was merged in v3.10.
James Hogan (3):
MIPS: KVM: Fix ASID restoration logic
MIPS: KVM: Fix CACHE immediate offset sign extension
MIPS: KVM: Uninit VCPU in vcpu_create error path
arch/mips/kvm/emulate.c | 2 +-
arch
The immediate field of the CACHE instruction is signed, so ensure that
it gets sign extended by casting it to an int16_t rather than just
masking the low 16 bits.
Fixes: e685c689f3a8 ("KVM/MIPS32: Privileged instruction/target branch
emulation.")
Signed-off-by: James Hogan
Signed-off-by: James Hogan <james.ho...@imgtec.com>
Cc: Ralf Baechle <r...@linux-mips.org>
Cc: Paolo Bonzini <pbonz...@redhat.com>
Cc: Gleb Natapov <g...@kernel.org>
Cc: linux-m...@linux-mips.org
Cc: kvm@vger.kernel.org
Cc: <sta...@vger.kernel.org> # 3.10.x-
---
arch/mips
late implementation of KVM, so it doesn't need to check the
supervisor bit as that mode is not implemented in the guest.
Fixes: b680f70fc111 ("KVM/MIPS32: Entry point for trampolining to...")
Signed-off-by: James Hogan <james.ho...@imgtec.com>
Cc: Ralf Baechle <r...@linux-mips.org>
to need to be used from assembly code.
Fixes: "MIPS: CPS: Early debug using an ns16550-compatible UART"
Signed-off-by: James Hogan <james.ho...@imgtec.com>
Cc: Ralf Baechle <r...@linux-mips.org>
Cc: Paul Burton <paul.bur...@imgtec.com>
Cc: Paolo Bonzini <pbonz...@red
After make lkvm-static & make clean, the dependency files for static
objects (.xxx.static.o.d) are not removed.
Signed-off-by: Xiaochen Shen <xiaochen.s...@intel.com>
Signed-off-by: Dimitri John Ledkov <dimitri.j.led...@intel.com>
Signed-off-by: James Hunt <james.o.h...@intel
+++ b/kvm-all.c
> @@ -1757,6 +1757,7 @@ static void do_kvm_cpu_synchronize_post_init(void *arg)
> {
> CPUState *cpu = arg;
>
> +kvm_arch_setup_tsc_khz(cpu);
Sorry if this is a stupid question, but why aren't you doing this from
the i386 kvm_arch_put_registers when level =
on the stack - so these mapped areas are always allocated, and
always leaked.
Pass this argument as a pointer instead.
Fixes: 6e3f26456009 "vfio/platform: read and write support for the device fd"
Signed-off-by: James Morse <james.mo...@arm.com>
---
drivers/vfio/platform/vfio_platfo
These two patches fix build errors for the MIPS TCG backend and MIPS
KVM.
Please could they be applied for v2.4.
James Hogan (2):
tcg/mips: Fix build error from merged memop+mmu_idx parameter
mips/kvm: Sync with newer MIPS KVM headers
target-mips/kvm.c | 15 ++-
tcg/mips
{32,64} macros to utilise definitions more
recently added to the asm-mips/kvm.h header.
Signed-off-by: James Hogan james.ho...@imgtec.com
Cc: Paolo Bonzini pbonz...@redhat.com
Cc: Leon Alrae leon.al...@imgtec.com
Cc: Aurelien Jarno aurel...@aurel32.net
Cc: kvm@vger.kernel.org
---
target-mips/kvm.c
On 09/07/15 14:59, Peter Maydell wrote:
On 9 July 2015 at 12:52, Leon Alrae leon.al...@imgtec.com wrote:
On 09/07/2015 10:17, James Hogan wrote:
These two patches fix build errors for the MIPS TCG backend and MIPS
KVM.
Please could they be applied for v2.4.
James Hogan (2):
tcg/mips
From: Nicholas Mc Guire hof...@osadl.org
commit ed9244e6c534612d2b5ae47feab2f55a0d4b4ced upstream.
Fix possible unintended sign extension in unsigned MMIO loads by casting
to uint16_t in the case of mmio_needed != 2.
Signed-off-by: Nicholas Mc Guire hof...@osadl.org
Reviewed-by: James Hogan
Hi Paolo,
On 24/04/15 11:26, James Hogan wrote:
A couple of small fixes for accessing 32-bit KVM registers on big
endian, and to sign extend struct kvm_regs registers so as to work on
MIPS64 hosts.
James Hogan (2):
mips/kvm: Fix Big endian 32-bit register access
mips/kvm: Sign extend
Hi stable folk,
On 08/05/15 15:16, James Hogan wrote:
On 07/05/15 13:47, Nicholas Mc Guire wrote:
Fix possible unintended sign extension in unsigned MMIO loads by casting
to uint16_t in the case of mmio_needed != 2.
Signed-off-by: Nicholas Mc Guire hof...@osadl.org
Looks good to me. I
Fix access to 32-bit registers on big endian targets. The pointer passed
to the kernel must be for the actual 32-bit value, not a temporary
64-bit value, otherwise on big endian systems the kernel will only
interpret the upper half.
Signed-off-by: James Hogan james.ho...@imgtec.com
Cc: Paolo
In case we're running on a 64-bit host, be sure to sign extend the
general purpose registers and hi/lo/pc before writing them to KVM, so as
to take advantage of MIPS32/MIPS64 compatibility.
Signed-off-by: James Hogan james.ho...@imgtec.com
Cc: Paolo Bonzini pbonz...@redhat.com
Cc: Leon Alrae
A couple of small fixes for accessing 32-bit KVM registers on big
endian, and to sign extend struct kvm_regs registers so as to work on
MIPS64 hosts.
James Hogan (2):
mips/kvm: Fix Big endian 32-bit register access
mips/kvm: Sign extend registers written to KVM
target-mips/kvm.c | 21
On 03/24/2015 08:03 AM, Radim Krčmář wrote:
2015-03-23 16:46-0600, James Sullivan:
On 03/23/2015 03:13 PM, Radim Krčmář wrote:
I meant if the delivery mode from data register isn't ignored with RH=1,
and the message delivered as if lowest-priority was set there.
(Decided by having something
about the 3.13.y-ckt tree, see
https://wiki.ubuntu.com/Kernel/Dev/ExtendedStable
Thanks.
-Kamal
--
From 7adee277d64254de602234e7e53691d729f5e50c Mon Sep 17 00:00:00 2001
From: James Hogan james.ho...@imgtec.com
Date: Tue, 10 Feb 2015 10:02:59 +
Subject: MIPS: Export FP functions
Hi Paolo, Marcelo,
Here is the MIPS guest FPU SIMD (MSA) work. I've based this on
kvm/queue as of Friday, and it also pulls in some MIPS FP/MSA fixes from
a branch in Ralf's MIPS tree. Hope that's okay.
Please pull
Thanks
James
The following changes since commit
On 03/17/2015 02:19 AM, Jan Kiszka wrote:
On 2015-03-17 02:30, James Sullivan wrote:
Changes Since v1:
* Reworked patches into two commits:
1) [Patch v2 1/2] Extended struct kvm_lapic_irq with bool
msi_redir_hint
* Initialize msi_redir_hint = true
-bit half native endian as
the kernel uses internally.
Signed-off-by: James Hogan james.ho...@imgtec.com
Cc: Paolo Bonzini pbonz...@redhat.com
Cc: Paul Burton paul.bur...@imgtec.com
Cc: Ralf Baechle r...@linux-mips.org
Cc: Gleb Natapov g...@kernel.org
Cc: Jonathan Corbet cor...@lwn.net
Cc: linux-m
if the hardware supports MSA vector
partitioning, since the extra support cannot be tested yet and it
extends the state that the userland program would have to save.
Signed-off-by: James Hogan james.ho...@imgtec.com
Acked-by: Paolo Bonzini pbonz...@redhat.com
Cc: Ralf Baechle r...@linux-mips.org
Cc
Now that the code is in place for KVM to support FPU in MIPS KVM guests,
wire up the new KVM_CAP_MIPS_FPU capability.
For backwards compatibility, the capability must be explicitly enabled
in order to detect or make use of the FPU from the guest.
Signed-off-by: James Hogan james.ho...@imgtec.com
.
- Patches 16..20 add the main guest MSA support (structured like 11.15).
James Hogan (20):
MIPS: KVM: Handle MSA Disabled exceptions from guest
MIPS: Clear [MSA]FPE CSR.Cause after notify_die()
MIPS: KVM: Handle TRAP exceptions from guest kernel
MIPS: KVM: Implement PRid CP0 register access
On 26/03/15 13:58, Paolo Bonzini wrote:
On 11/03/2015 15:44, James Hogan wrote:
Now that the code is in place for KVM to support MIPS SIMD Architecutre
(MSA) in MIPS guests, wire up the new KVM_CAP_MIPS_MSA capability.
For backwards compatibility, the capability must be explicitly enabled
that QEMU can
save/restore the guest modifiable bits (Config5.FRE, Config5.UFR,
Config5.UFE). The FCSR/FIR registers and the floating point registers
are now saved/restored (depending on the FR mode bit).
Signed-off-by: James Hogan james.ho...@imgtec.com
Cc: Paolo Bonzini pbonz...@redhat.com
Cc: Leon
Add KVM register access functions for the uint32_t type. This is
required for FP and MSA control registers, which are represented as
unsigned 32-bit integers.
Signed-off-by: James Hogan james.ho...@imgtec.com
Cc: Paolo Bonzini pbonz...@redhat.com
Cc: Leon Alrae leon.al...@imgtec.com
Cc: Aurelien
/20] MIPS: KVM: Wire up FPU capability
https://patchwork.kernel.org/patch/5986201/
- [PATCH 19/20] MIPS: KVM: Expose MSA registers
https://patchwork.kernel.org/patch/5986191/
- [PATCH 20/20] MIPS: KVM: Wire up MSA capability
https://patchwork.kernel.org/patch/5986151/
Signed-off-by: James
.MSAP) and so that QEMU can
save/restore the guest modifiable bits (Config5.MSAEn). The MSACSR/MSAIR
registers and the MSA vector registers are now saved/restored. Since the
FP registers are a subset of the vector registers, they are omitted if
the guest has MSA.
Signed-off-by: James Hogan james.ho
definitions more
recently added to the asm-mips/kvm.h header.
Signed-off-by: James Hogan james.ho...@imgtec.com
Cc: Paolo Bonzini pbonz...@redhat.com
Cc: Leon Alrae leon.al...@imgtec.com
Cc: Aurelien Jarno aurel...@aurel32.net
---
Changes in v2:
- Add the changes to MIPS_CP0_{32,64} macros from v1
Implement saving and restoring to KVM state of the Processor ID (PRid)
CP0 register. This allows QEMU to control the PRid exposed to the guest
instead of using the default set by KVM.
Signed-off-by: James Hogan james.ho...@imgtec.com
Reviewed-by: Leon Alrae leon.al...@imgtec.com
Cc: Paolo Bonzini
them on migration/savevm.
Signed-off-by: James Hogan james.ho...@imgtec.com
Cc: Paolo Bonzini pbonz...@redhat.com
Cc: Leon Alrae leon.al...@imgtec.com
Cc: Aurelien Jarno aurel...@aurel32.net
---
Changes in v2:
- Fix line wrapping of kvm_mips_get_one_reg() calls from Config4 and
Config5 (Leon
Rename kvm_mips_{get,put}_one_reg64() to kvm_mips_{get,put}_one_ureg64()
since they take an int64_t pointer, and add separate signed 64-bit
accessors. These will be used for double precision floating point
registers.
Signed-off-by: James Hogan james.ho...@imgtec.com
Cc: Paolo Bonzini pbonz
The DPRINTFs in cpu_mips_io_interrupts_pending() and kvm_arch_pre_run()
are particularly noisy during normal execution, and also not
particularly helpful. Remove them so that more important debug messages
can be more easily seen.
Signed-off-by: James Hogan james.ho...@imgtec.com
Reviewed-by: Leon
of kvm_mips_get_one_reg() calls from Config4 and
Config5 in patch 5 (Leon).
- Change (1 x) to (1U x) in important places in patch 5, 8 9 to
avoid compiler defined behaviour (Leon).
James Hogan (9):
DONT APPLY: linux-headers: Update MIPS KVM headers
mips/kvm: Sync with newer MIPS KVM headers
mips/kvm
On 03/24/2015 08:03 AM, Radim Krčmář wrote:
2015-03-23 16:46-0600, James Sullivan:
On 03/23/2015 03:13 PM, Radim Krčmář wrote:
I meant if the delivery mode from data register isn't ignored with RH=1,
and the message delivered as if lowest-priority was set there.
(Decided by having something
On 03/23/2015 03:13 PM, Radim Krčmář wrote:
2015-03-20 11:50-0600, James Sullivan:
On 03/20/2015 09:22 AM, James Sullivan wrote:
On 03/20/2015 09:15 AM, Radim Krčmář wrote:
2015-03-19 16:51-0600, James Sullivan:
I played around with native_compose_msi_msg and discovered the following:
* dm
On 03/20/2015 09:15 AM, Radim Krčmář wrote:
2015-03-19 16:51-0600, James Sullivan:
I played around with native_compose_msi_msg and discovered the following:
* dm=0, rh=0 = Physical Destination Mode
* dm=0, rh=1 = Failed delivery
* dm=1, rh=0 = Logical Destination Mode, No Redirection
* dm=1
On 03/20/2015 09:22 AM, James Sullivan wrote:
On 03/20/2015 09:15 AM, Radim Krčmář wrote:
2015-03-19 16:51-0600, James Sullivan:
I played around with native_compose_msi_msg and discovered the following:
* dm=0, rh=0 = Physical Destination Mode
* dm=0, rh=1 = Failed delivery
* dm=1, rh=0
the restrictions are if you
set it on.
The default config for PCI devices seems to be DM=1,RH=1.
-James
--
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to true when RH=1 in kvm_set_msi_irq(), and initialized
to false in all other cases.
Added value of msi_redir_hint to a debug message dump of an IRQ in
apic_send_ipi().
Signed-off-by: James Sullivan sullivan.jame...@gmail.com
---
Changes since v1:
* Squashed a number of smaller commits
to
kvm_lowest_prio_delivery().
Changed a check in kvm_irq_delivery_to_apic_fast() from
irq-delivery_mode == APIC_DM_LOWPRI to kvm_is_dm_lowest_prio().
Signed-off-by: James Sullivan sullivan.jame...@gmail.com
---
Changes since v1:
* Squashed a number of smaller commits into this one commit,
which
and
virtio sourced MSIs, but I haven't done experiments with passing through
PCI hardware (intend to start working on this).
-James
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is probably desirable for the time being. If I can get closure on the matter
I'll re-submit that change, but for the time being I will undo it.
-James
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N.B. This patch has been re-submitted in a larger patch, see
1426555822-3280-1-git-send-email-sullivan.jame...@gmail.com
(The new patch relies on changes made in this patch, and as such
it makes more sense to bundle them)
On 03/13/2015 09:14 AM, James Sullivan wrote:
This patch adds a check
to participate in GSoC working on shunting some interrupt
handling devices out of the KVM and into QEMU, so that's definitely something
I'll start to look into.
-James
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(), and initialized
to false in all other cases.
Added value of msi_redir_hint to a debug message dump of an IRQ in
apic_send_ipi().
Signed-off-by: James Sullivan sullivan.jame...@gmail.com
---
Changes since v1:
* Squashed a number of smaller commits into this one commit,
which adds and initializes
to
kvm_lowest_prio_delivery().
Changed a check in kvm_irq_delivery_to_apic_fast() from
irq-delivery_mode == APIC_DM_LOWPRI to kvm_is_dm_lowest_prio().
Signed-off-by: James Sullivan sullivan.jame...@gmail.com
---
Changes since v1:
* Squashed a number of smaller commits into this one commit,
which
guest and
virtio sourced MSIs, but I haven't done experiments with passing through
PCI hardware (intend to start working on this).
-James
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the body of a message to majord...@vger.kernel.org
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Signed-off-by: James Sullivan sullivan.jame...@gmail.com
---
The following changes are added in this patch:
* Initialize msi_redir_hint = true in kvm_set_msi_irq when RH=1
* Initialize msi_redir_hint = false otherwise
* Added value of msi_redir_hint to debug message dump of IRQ
MSIs, but I haven't done experiments with passing through
PCI hardware (intend to start working on this).
Let me know your thoughts.
-James
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Signed-off-by: James Sullivan sullivan.jame...@gmail.com
---
The following changes are added in this patch:
* Move kvm_is_dm_lowest_prio() - lapic.h, rename to
kvm_lowest_prio_delivery, set condition to
(APIC_DM_LOWPRI || msi_redir_hint)
* Change check
Signed-off-by: James Sullivan sullivan.jame...@gmail.com
---
arch/x86/kvm/irq_comm.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/arch/x86/kvm/irq_comm.c b/arch/x86/kvm/irq_comm.c
index 36d2ca3a..f993f2f 100644
--- a/arch/x86/kvm/irq_comm.c
+++ b/arch/x86/kvm/irq_comm.c
@@ -103,12
Signed-off-by: James Sullivan sullivan.jame...@gmail.com
---
arch/x86/include/asm/kvm_host.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
index a236e39..77feaf4 100644
--- a/arch/x86/include/asm/kvm_host.h
+++ b/arch/x86
Signed-off-by: James Sullivan sullivan.jame...@gmail.com
---
arch/x86/kvm/irq_comm.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/x86/kvm/irq_comm.c b/arch/x86/kvm/irq_comm.c
index f2887ea..7e0f469 100644
--- a/arch/x86/kvm/irq_comm.c
+++ b/arch/x86/kvm/irq_comm.c
Signed-off-by: James Sullivan sullivan.jame...@gmail.com
---
arch/x86/kvm/x86.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index bd7a70b..03e9b09 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -5902,6 +5902,7 @@ static void
Signed-off-by: James Sullivan sullivan.jame...@gmail.com
---
arch/x86/kvm/lapic.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index c26afc9..c946470 100644
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -702,7 +702,8
to start working on this).
Let me know your thoughts.
-James
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Signed-off-by: James Sullivan sullivan.jame...@gmail.com
---
arch/x86/kvm/lapic.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index c946470..bced6d5 100644
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -903,10
Signed-off-by: James Sullivan sullivan.jame...@gmail.com
---
arch/x86/kvm/irq_comm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/kvm/irq_comm.c b/arch/x86/kvm/irq_comm.c
index 7e0f469..36d2ca3a 100644
--- a/arch/x86/kvm/irq_comm.c
+++ b/arch/x86/kvm/irq_comm.c
Signed-off-by: James Sullivan sullivan.jame...@gmail.com
---
arch/x86/kvm/lapic.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index bd4e34d..c26afc9 100644
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -892,6 +892,7 @@ static void
Signed-off-by: James Sullivan sullivan.jame...@gmail.com
---
arch/x86/kvm/ioapic.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/kvm/ioapic.c b/arch/x86/kvm/ioapic.c
index b1947e0..61f0874 100644
--- a/arch/x86/kvm/ioapic.c
+++ b/arch/x86/kvm/ioapic.c
@@ -347,6 +347,7 @@ static int
it is too clever :)
For the error message, how does:
kvm: MSI RH=1 unsupported, use low-priority delivery mode
Sit with you?
-James
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Perfect, thanks for the feedback. I'll get v5 out shortly.
On 03/13/2015 09:08 AM, Radim Krčmář wrote:
2015-03-13 08:47-0600, James Sullivan:
On 03/13/2015 08:39 AM, Radim Krčmář wrote:
...
The warning message is very clever:
- it contains the magical may qualifier and being protected only
-by: James Sullivan sullivan.jame...@gmail.com
---
Changes since v2:
* Added one time warning message when RH=1
* Documented conflict between RH=1 and delivery mode
* Tidied code to check RH=1/DM=1 (remove bool phys, use if/else)
Changes since v3:
* Fixed logical error in RH=1/DM=1
for when Status.CU1 is set while FR=0 and
the MSA state is live. In this case we are at risk of getting reserved
instruction exceptions if we try and save the MSA state, so we lose the
MSA state sooner while MSA is still usable.
Signed-off-by: James Hogan james.ho...@imgtec.com
Cc: Paolo Bonzini pbonz
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