RE: [PATCH v9 13/16] ARM: KVM: Emulation framework and CP15 emulation

2012-07-17 Thread Min-gyu Kim
Why does the cache operation need to happen on the same CPU while the L1 caches between cores are coherent? As you know, cache operations usually operate for a range and it iterates without disabling preemption. Therefore, though you enclose the vcpu_run and handle_exit with preemption disable,

Re: [PATCH v9 13/16] ARM: KVM: Emulation framework and CP15 emulation

2012-07-16 Thread Christoffer Dall
On Thu, Jul 12, 2012 at 7:35 AM, 김민규 wrote: > + /* > +* Make sure preemption is disabled while calling handle_exit > +* as exit handling touches CPU-specific resources, such as > +* caches, and we must stay on the same CPU. > +

RE: [PATCH v9 13/16] ARM: KVM: Emulation framework and CP15 emulation

2012-07-11 Thread 김민규
+ /* +* Make sure preemption is disabled while calling handle_exit +* as exit handling touches CPU-specific resources, such as +* caches, and we must stay on the same CPU. +* +* Code that might sleep must