On 30/12/2015 17:26, David Matlack wrote:
> The comment had the meaning of mmu.gva_to_gpa and nested_mmu.gva_to_gpa
> swapped. Fix that, and also add some details describing how each translation
> works.
>
> Signed-off-by: David Matlack
> ---
> arch/x86/kvm/mmu.c | 10
On 22/12/15 08:08, Shannon Zhao wrote:
> From: Shannon Zhao
>
> These kind of registers include PMEVCNTRn, PMCCNTR and PMXEVCNTR which
> is mapped to PMEVCNTRn.
>
> The access handler translates all aarch32 register offsets to aarch64
> ones and uses vcpu_sys_reg() to
On 24/12/2015 12:12, Marc Zyngier wrote:
> Hi Paolo,
>
> THis is the first pull request for the 4.5 merge window. Not much in
> terms of features, but a rewrite of our 64bit world switch, making it
> a lot nicer, maintainable, and much more likely to cope with things
> like VHE. Also support
On 01/05/2016 05:20 PM, Michael S. Tsirkin wrote:
> smp_mb on vcpu destroy isn't paired with anything, violating pairing
> rules, and seems to be useless.
>
> Drop it.
>
> Signed-off-by: Michael S. Tsirkin
Applied.
(I had to fix this up a little to match kvm/next)
Thanks
>
On 30/12/2015 19:08, Nicholas Krause wrote:
> This makes sure that kvm_write_guest successes for the first call
> in order to make sure that the wall clock is successfully written
> to the host system before being calucated as required by the
> guest system.
>
> Signed-off-by: Nicholas Krause
On Tue, 5 Jan 2016 18:43:02 +0200
"Michael S. Tsirkin" wrote:
> On Tue, Jan 05, 2016 at 05:30:25PM +0100, Igor Mammedov wrote:
> > > > bios-linker-loader is a great interface for initializing some
> > > > guest owned data and linking it together but I think it adds
> > > >
On 22/12/15 08:07, Shannon Zhao wrote:
> From: Shannon Zhao
>
> Add reset handler which gets host value of PMCR_EL0 and make writable
> bits architecturally UNKNOWN except PMCR.E which is zero. Add an access
> handler for PMCR.
>
> Signed-off-by: Shannon Zhao
On 22/12/15 08:08, Shannon Zhao wrote:
> From: Shannon Zhao
>
> Since the reset value of PMINTENSET and PMINTENCLR is UNKNOWN, use
> reset_unknown for its reset handler. Add a handler to emulate writing
> PMINTENSET or PMINTENCLR register.
>
> Signed-off-by: Shannon
On 2016/1/7 18:14, Marc Zyngier wrote:
> On 22/12/15 08:08, Shannon Zhao wrote:
>> > From: Shannon Zhao
>> >
>> > This register resets as unknown in 64bit mode while it resets as zero
>> > in 32bit mode. Here we choose to reset it as zero for consistency.
>> >
>> >
On 2015/12/22 16:08, Shannon Zhao wrote:
> From: Shannon Zhao
>
> These kind of registers include PMEVTYPERn, PMCCFILTR and PMXEVTYPER
> which is mapped to PMEVTYPERn or PMCCFILTR.
>
> The access handler translates all aarch32 register offsets to aarch64
> ones and
On 22/12/15 08:07, Shannon Zhao wrote:
> From: Shannon Zhao
>
> To use the ARMv8 PMU related register defines from the KVM code,
> we move the relevant definitions to asm/pmu.h header file.
>
> Signed-off-by: Anup Patel
> Signed-off-by: Shannon
On 22/12/15 08:08, Shannon Zhao wrote:
> From: Shannon Zhao
>
> Add access handler which gets host value of PMCEID0 or PMCEID1 when
> guest access these registers. Writing action to PMCEID0 or PMCEID1 is
> UNDEFINED.
>
> Signed-off-by: Shannon Zhao
On 22/12/15 08:08, Shannon Zhao wrote:
> From: Shannon Zhao
>
> Since the reset value of PMSELR_EL0 is UNKNOWN, use reset_unknown for
> its reset handler. When reading PMSELR, return the PMSELR.SEL field to
> guest.
>
> Signed-off-by: Shannon Zhao
On 2016/1/7 19:03, Marc Zyngier wrote:
> On 22/12/15 08:08, Shannon Zhao wrote:
>> > From: Shannon Zhao
>> >
>> > These kind of registers include PMEVTYPERn, PMCCFILTR and PMXEVTYPER
>> > which is mapped to PMEVTYPERn or PMCCFILTR.
>> >
>> > The access handler
On 22/12/15 08:08, Shannon Zhao wrote:
> From: Shannon Zhao
>
> Add access handler which emulates writing and reading PMSWINC
> register and add support for creating software increment event.
>
> Signed-off-by: Shannon Zhao
> ---
>
On 22/12/15 08:08, Shannon Zhao wrote:
> From: Shannon Zhao
>
> This register resets as unknown in 64bit mode while it resets as zero
> in 32bit mode. Here we choose to reset it as zero for consistency.
>
> PMUSERENR_EL0 holds some bits which decide whether PMU
On 22/12/15 08:07, Shannon Zhao wrote:
> From: Shannon Zhao
>
> We are about to trap and emulate accesses to each PMU register
> individually. This adds the context offsets for the AArch64 PMU
> registers.
>
> Signed-off-by: Shannon Zhao
On Thu, Jan 07, 2016 at 11:30:25AM +0100, Igor Mammedov wrote:
> On Tue, 5 Jan 2016 18:43:02 +0200
> "Michael S. Tsirkin" wrote:
>
> > On Tue, Jan 05, 2016 at 05:30:25PM +0100, Igor Mammedov wrote:
> > > > > bios-linker-loader is a great interface for initializing some
> > > > >
On 2016/1/7 18:43, Marc Zyngier wrote:
> On 22/12/15 08:07, Shannon Zhao wrote:
>> > From: Shannon Zhao
>> >
>> > Add reset handler which gets host value of PMCR_EL0 and make writable
>> > bits architecturally UNKNOWN except PMCR.E which is zero. Add an access
>> >
On 07/01/16 12:09, Shannon Zhao wrote:
>
>
> On 2015/12/22 16:08, Shannon Zhao wrote:
>> From: Shannon Zhao
>>
>> These kind of registers include PMEVTYPERn, PMCCFILTR and PMXEVTYPER
>> which is mapped to PMEVTYPERn or PMCCFILTR.
>>
>> The access handler translates all
On Tue, 5 Jan 2016 02:52:07 +0800
Xiao Guangrong wrote:
> If dsm memory is successfully patched, we let qemu fully emulate
> the dsm method
>
> This patch saves _DSM input parameters into dsm memory, tell dsm
> memory address to QEMU, then fetch the result from
On 22 December 2015 at 08:08, Shannon Zhao wrote:
> From: Shannon Zhao
>
> Add a new kvm device type KVM_DEV_TYPE_ARM_PMU_V3 for ARM PMU. Implement
> the kvm_device_ops for it.
>
> Signed-off-by: Shannon Zhao
> ---
>
On 01/07/2016 03:17 PM, Paolo Bonzini wrote:
> Leave room for 4 more arch-independent requests.
>
The patch subject is wrong.
"renumber architecture-dependent requests"
--> "renumber kvm requests"
as we also renumber the architecture independent ones.
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To unsubscribe from this list: send
+-- On Thu, 7 Jan 2016, Paolo Bonzini wrote --+
| > Will this trigger the same issue like CVE-2015-7513 ?
| >
https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=0185604c2d82c560dab2f2933a18f797e74ab5a8
|
| I am not sure (--verbose please :))
IIUC, it shouldn't, because
On Tue, 22 Dec 2015 16:08:14 +0800
Shannon Zhao wrote:
> From: Shannon Zhao
>
> When KVM frees VCPU, it needs to free the perf_event of PMU.
>
> Signed-off-by: Shannon Zhao
Reviewed-by: Marc Zyngier
On Mon, 4 Jan 2016 21:17:31 +0100
Laszlo Ersek wrote:
> Michael CC'd me on the grandparent of the email below. I'll try to add
> my thoughts in a single go, with regard to OVMF.
>
> On 12/30/15 20:52, Michael S. Tsirkin wrote:
> > On Wed, Dec 30, 2015 at 04:55:54PM +0100,
On Tue, 5 Jan 2016 02:52:02 +0800
Xiao Guangrong wrote:
> This patchset is against commit 5530427f0ca (acpi: extend aml_and() to
> accept target argument) on pci branch of Michael's git tree
> and can be found at:
> https://github.com/xiaogr/qemu.git
On 07/01/2016 12:43, Takuya Yoshikawa wrote:
> Signed-off-by: Takuya Yoshikawa
> ---
> include/linux/kvm_host.h | 45 ++---
> 1 file changed, 22 insertions(+), 23 deletions(-)
>
> diff --git a/include/linux/kvm_host.h
On 2016/1/7 20:32, P J P wrote:
From: P J P
While setting the KVM PIT counters in 'kvm_pit_load_count', if
'hpet_legacy_start' is set, the function disables the timer on
channel[0], instead of the respective index 'channel'. Update it
to use 'channel' index parameter.
On 2016/1/7 19:03, Marc Zyngier wrote:
> On 22/12/15 08:08, Shannon Zhao wrote:
>> > From: Shannon Zhao
>> >
>> > These kind of registers include PMEVTYPERn, PMCCFILTR and PMXEVTYPER
>> > which is mapped to PMEVTYPERn or PMCCFILTR.
>> >
>> > The access handler
On Tue, 22 Dec 2015 16:08:02 +0800
Shannon Zhao wrote:
> From: Shannon Zhao
>
> When we use tools like perf on host, perf passes the event type and the
> id of this event type category to kernel, then kernel will map them to
> hardware event
On 07/01/16 14:12, Will Deacon wrote:
> On Thu, Jan 07, 2016 at 02:10:38PM +, Marc Zyngier wrote:
>> On 22/12/15 08:07, Shannon Zhao wrote:
>>> From: Shannon Zhao
>>>
>>> This patchset adds guest PMU support for KVM on ARM64. It takes
>>> trap-and-emulate approach.
On 7 January 2016 at 14:49, Shannon Zhao wrote:
>
>
> On 2016/1/7 22:36, Peter Maydell wrote:
>> On 22 December 2015 at 08:08, Shannon Zhao wrote:
>>> From: Shannon Zhao
>>>
>>> Add a new kvm device type
On Wed, 30 Dec 2015 22:05:25 +0800
Geliang Tang wrote:
> Use dev_to_virtio() instead of open-coding it.
>
> Signed-off-by: Geliang Tang
> ---
> drivers/s390/virtio/virtio_ccw.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
Thanks, added
On 07/01/2016 16:27, Christian Borntraeger wrote:
> On 01/07/2016 03:17 PM, Paolo Bonzini wrote:
>> Leave room for 4 more arch-independent requests.
>
> The patch subject is wrong.
>
> "renumber architecture-dependent requests"
>
> --> "renumber kvm requests"
>
> as we also renumber the
On 07/01/2016 16:54, Christian Borntraeger wrote:
> On 01/07/2016 03:17 PM, Paolo Bonzini wrote:
>
> Can you add at least a one line patch description?
Yes, and it will be more than one line. :)
"Since the numbers now overlap, it makes sense to enumerate
them in asm/kvm_host.h rather than
On 23/12/2015 12:28, Andrey Smetanin wrote:
> During testing of Windows 2012R2 guest migration with
> Hyper-V SynIC timers enabled we found several bugs
> which lead to restoring guest in a hung state.
>
> This patch series provides several fixes to make the
> migration of guest with Hyper-V
On 01/07/2016 03:17 PM, Paolo Bonzini wrote:
Can you add at least a one line patch description?
> Signed-off-by: Paolo Bonzini
Reviewed-by: Christian Borntraeger
> ---
> arch/powerpc/include/asm/kvm_host.h | 4
>
On 28/12/2015 16:27, Andrey Smetanin wrote:
> This will be used in future to start Hyper-V SynIC timer
> in several places by one logic in one function.
>
> Changes v2:
> * drop stimer->count == 0 check inside stimer_start()
> * comment stimer_start() assumptions
Can you replace comments with
On 01/06/2016 12:48 AM, Peter Hornyack wrote:
On Thu, Dec 24, 2015 at 1:33 AM, Andrey Smetanin
wrote:
Lately tsc page was implemented but filled with empty
values. This patch setup tsc page scale and offset based
on vcpu tsc, tsc_khz and HV_X64_MSR_TIME_REF_COUNT
On 2016/1/5 5:42, Benjamin Herrenschmidt wrote:
On Mon, 2016-01-04 at 14:07 -0700, Alex Williamson wrote:
On Thu, 2015-12-31 at 16:50 +0800, Yongji Xie wrote:
Current vfio-pci implementation disallows to mmap MSI-X
table in case that user get to touch this directly.
However, EEH mechanism can
On Tue, 5 Jan 2016 18:22:33 +0100
Laszlo Ersek wrote:
> On 01/05/16 18:08, Igor Mammedov wrote:
> > On Mon, 4 Jan 2016 21:17:31 +0100
> > Laszlo Ersek wrote:
> >
> >> Michael CC'd me on the grandparent of the email below. I'll try to add
> >> my thoughts
On 01/06/2016 11:23 PM, Igor Mammedov wrote:
On Tue, 5 Jan 2016 02:52:05 +0800
Xiao Guangrong wrote:
The dsm memory is used to save the input parameters and store
the dsm result which is filled by QEMU.
The address of dsm memory is decided by bios and
On 01/06/16 14:39, Igor Mammedov wrote:
> On Tue, 5 Jan 2016 18:22:33 +0100
> Laszlo Ersek wrote:
>
>> On 01/05/16 18:08, Igor Mammedov wrote:
>>> On Mon, 4 Jan 2016 21:17:31 +0100
>>> Laszlo Ersek wrote:
>>>
Michael CC'd me on the grandparent of
On Tue, 5 Jan 2016 02:52:05 +0800
Xiao Guangrong wrote:
> The dsm memory is used to save the input parameters and store
> the dsm result which is filled by QEMU.
>
> The address of dsm memory is decided by bios and patched into
> int64 object returned by "MEMA"
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> "Paolo" == Paolo Bonzini writes:
>> This is v3 of the series to provide an "official" sg.h header (and
>> scsi_ioctl.h too, though it's basically obsolete) together with the
>> other userspace API definitions. The change from v2 to v3 is that
>> defaults for sg.c are
On Mon, Jan 04, 2016 at 07:11:25PM -0800, Alexander Duyck wrote:
> >> The two mechanisms referenced above would likely require coordination with
> >> QEMU and as such are open to discussion. I haven't attempted to address
> >> them as I am not sure there is a consensus as of yet. My personal
>
* Michael S. Tsirkin (m...@redhat.com) wrote:
> On Mon, Jan 04, 2016 at 07:11:25PM -0800, Alexander Duyck wrote:
> > >> The two mechanisms referenced above would likely require coordination
> > >> with
> > >> QEMU and as such are open to discussion. I haven't attempted to address
> > >> them as
On Tue, Jan 05, 2016 at 10:01:04AM +, Dr. David Alan Gilbert wrote:
> * Michael S. Tsirkin (m...@redhat.com) wrote:
> > On Mon, Jan 04, 2016 at 07:11:25PM -0800, Alexander Duyck wrote:
> > > >> The two mechanisms referenced above would likely require coordination
> > > >> with
> > > >> QEMU
On Tue, Jan 5, 2016 at 1:40 AM, Michael S. Tsirkin wrote:
> On Mon, Jan 04, 2016 at 07:11:25PM -0800, Alexander Duyck wrote:
>> >> The two mechanisms referenced above would likely require coordination with
>> >> QEMU and as such are open to discussion. I haven't attempted to
On Wed, 30 Dec 2015 21:52:32 +0200
"Michael S. Tsirkin" wrote:
> On Wed, Dec 30, 2015 at 04:55:54PM +0100, Igor Mammedov wrote:
> > On Mon, 28 Dec 2015 14:50:15 +0200
> > "Michael S. Tsirkin" wrote:
> >
> > > On Mon, Dec 28, 2015 at 10:39:04AM +0800, Xiao
On Mon, 4 Jan 2016 21:17:31 +0100
Laszlo Ersek wrote:
> Michael CC'd me on the grandparent of the email below. I'll try to add
> my thoughts in a single go, with regard to OVMF.
>
> On 12/30/15 20:52, Michael S. Tsirkin wrote:
> > On Wed, Dec 30, 2015 at 04:55:54PM +0100,
On 01/06/2016 12:43 AM, Michael S. Tsirkin wrote:
Yes - if address is static, you need to put it outside
the table. Can come right before or right after this.
Also if OperationRegion() is used, then one has to patch
DefOpRegion directly as RegionOffset must be Integer,
using variable names
On 01/05/16 18:08, Igor Mammedov wrote:
> On Mon, 4 Jan 2016 21:17:31 +0100
> Laszlo Ersek wrote:
>
>> Michael CC'd me on the grandparent of the email below. I'll try to add
>> my thoughts in a single go, with regard to OVMF.
>>
>> On 12/30/15 20:52, Michael S. Tsirkin wrote:
On Tue, Jan 05, 2016 at 05:30:25PM +0100, Igor Mammedov wrote:
> > > bios-linker-loader is a great interface for initializing some
> > > guest owned data and linking it together but I think it adds
> > > unnecessary complexity and is misused if it's used to handle
> > > device owned data/on device
On 01/05/16 17:43, Michael S. Tsirkin wrote:
> On Tue, Jan 05, 2016 at 05:30:25PM +0100, Igor Mammedov wrote:
bios-linker-loader is a great interface for initializing some
guest owned data and linking it together but I think it adds
unnecessary complexity and is misused if it's used
On Fri, Sep 18, 2015 at 11:06:44PM +0800, Fengguang Wu wrote:
> [CC sparse people]
>
> On Fri, Sep 18, 2015 at 04:41:56PM +0200, Paolo Bonzini wrote:
> >
> >
> > On 18/09/2015 16:40, Roman Kagan wrote:
> > > typedef unsigned long __nocast cputime_t;
> > >
> > > extern void
On Sat, Dec 26, 2015 at 01:54:55PM -0800, Mario Smarduch wrote:
> Add helper functions to enable access to fp/smid on guest entry and save host
> fpexc on vcpu put, check if fp/simd registers are dirty and add new vcpu
> fields.
>
> Signed-off-by: Mario Smarduch
> ---
>
On 1/5/2016 7:00 AM, Christoffer Dall wrote:
> On Sat, Dec 26, 2015 at 01:54:55PM -0800, Mario Smarduch wrote:
>> Add helper functions to enable access to fp/smid on guest entry and save host
>> fpexc on vcpu put, check if fp/simd registers are dirty and add new vcpu
>> fields.
>>
>>
On 01/05/2016 11:18 AM, Yang Zhang wrote:
> On 2016/1/4 14:22, Jason Wang wrote:
>>
>>
>> On 01/04/2016 09:39 AM, Yang Zhang wrote:
>>> On 2015/12/31 15:13, Jason Wang wrote:
This patch tries to implement an device IOTLB for vhost. This could be
used with for co-operation with
On Wed, Dec 16, 2015 at 10:55:12PM +0100, Paolo Bonzini wrote:
>
>
> On 16/12/2015 20:15, Alex Williamson wrote:
> > The consumers would be, for instance, Intel PI + the threaded handler
> > added in this series. These run independently, the PI bypass simply
> > makes the interrupt disappear
On Wed, Dec 16, 2015 at 12:15:23PM -0700, Alex Williamson wrote:
> On Wed, 2015-12-16 at 18:56 +0100, Paolo Bonzini wrote:
> > Alex,
> >
> > can you take a look at the extension to the irq bypass interface in
> > patch 2? I'm not sure I understand what is the case where you have
> > multiple
* Michael S. Tsirkin (m...@redhat.com) wrote:
> On Tue, Jan 05, 2016 at 10:01:04AM +, Dr. David Alan Gilbert wrote:
> > * Michael S. Tsirkin (m...@redhat.com) wrote:
> > > On Mon, Jan 04, 2016 at 07:11:25PM -0800, Alexander Duyck wrote:
> > > > >> The two mechanisms referenced above would
On Tue, Jan 05, 2016 at 10:45:25AM +, Dr. David Alan Gilbert wrote:
> * Michael S. Tsirkin (m...@redhat.com) wrote:
> > On Tue, Jan 05, 2016 at 10:01:04AM +, Dr. David Alan Gilbert wrote:
> > > * Michael S. Tsirkin (m...@redhat.com) wrote:
> > > > On Mon, Jan 04, 2016 at 07:11:25PM -0800,
gnore firmware setup and force re-assigning all
resources if we want to use the option "pci=resource_page_aligned=on"?
For the default value of this parameter, we think it should be
arch-independent, so we add a macro PCI_RESOURCE_PAGE_ALIGNED
to change it. And we define this macro to en
On Tue, Jan 05, 2016 at 12:59:54PM +0200, Michael S. Tsirkin wrote:
> On Tue, Jan 05, 2016 at 10:45:25AM +, Dr. David Alan Gilbert wrote:
> > * Michael S. Tsirkin (m...@redhat.com) wrote:
> > > On Tue, Jan 05, 2016 at 10:01:04AM +, Dr. David Alan Gilbert wrote:
> > > > * Michael S. Tsirkin
On 24/12/2015 15:51, Alex Williamson wrote:
> No. A privileged entity needs to grant a user ownership of a group and
> sufficient locked memory limits to make it useful, but then use of the
> group does not require root permission.
So we're thinking how we can force the VFs in these cases to be
2016-01-05 10:20 GMT+03:00 Bandan Das :
> "Matwey V. Kornilov" writes:
>
>> Hello,
>>
>> According to WikiPedia VIA claims x86 hardware assisted virtualization
>> for VIA Eden X4 CPU.
>> Does anybody know if it is supported by Linux KVM?
>>
>
> I can't
On Tue, Jan 05, 2016 at 10:45:25AM +, Dr. David Alan Gilbert wrote:
> * Michael S. Tsirkin (m...@redhat.com) wrote:
> > On Tue, Jan 05, 2016 at 10:01:04AM +, Dr. David Alan Gilbert wrote:
> > > * Michael S. Tsirkin (m...@redhat.com) wrote:
> > > > On Mon, Jan 04, 2016 at 07:11:25PM -0800,
* Michael S. Tsirkin (m...@redhat.com) wrote:
> On Tue, Jan 05, 2016 at 10:45:25AM +, Dr. David Alan Gilbert wrote:
> > * Michael S. Tsirkin (m...@redhat.com) wrote:
> > > On Tue, Jan 05, 2016 at 10:01:04AM +, Dr. David Alan Gilbert wrote:
> > > > * Michael S. Tsirkin (m...@redhat.com)
On Tue, Jan 05, 2016 at 11:03:38AM +, Dr. David Alan Gilbert wrote:
> * Michael S. Tsirkin (m...@redhat.com) wrote:
> > On Tue, Jan 05, 2016 at 10:45:25AM +, Dr. David Alan Gilbert wrote:
> > > * Michael S. Tsirkin (m...@redhat.com) wrote:
> > > > On Tue, Jan 05, 2016 at 10:01:04AM +,
On Thu, Dec 24, 2015 at 1:33 AM, Andrey Smetanin
wrote:
> Lately tsc page was implemented but filled with empty
> values. This patch setup tsc page scale and offset based
> on vcpu tsc, tsc_khz and HV_X64_MSR_TIME_REF_COUNT value.
>
> The valid tsc page drops
On Tue, Jan 05, 2016 at 12:43:03PM +, Dr. David Alan Gilbert wrote:
> * Michael S. Tsirkin (m...@redhat.com) wrote:
> > On Tue, Jan 05, 2016 at 10:45:25AM +, Dr. David Alan Gilbert wrote:
> > > * Michael S. Tsirkin (m...@redhat.com) wrote:
> > > > On Tue, Jan 05, 2016 at 10:01:04AM +,
* Michael S. Tsirkin (m...@redhat.com) wrote:
> On Tue, Jan 05, 2016 at 10:45:25AM +, Dr. David Alan Gilbert wrote:
> > * Michael S. Tsirkin (m...@redhat.com) wrote:
> > > On Tue, Jan 05, 2016 at 10:01:04AM +, Dr. David Alan Gilbert wrote:
> > > > * Michael S. Tsirkin (m...@redhat.com)
On Sun, Dec 20, 2015 at 03:05:41AM -0800, Andy Lutomirski wrote:
> From: Andy Lutomirski
>
> The pvclock vdso code was too abstracted to understand easily and
> excessively paranoid. Simplify it for a huge speedup.
>
> This opens the door for additional simplifications, as
Michael CC'd me on the grandparent of the email below. I'll try to add
my thoughts in a single go, with regard to OVMF.
On 12/30/15 20:52, Michael S. Tsirkin wrote:
> On Wed, Dec 30, 2015 at 04:55:54PM +0100, Igor Mammedov wrote:
>> On Mon, 28 Dec 2015 14:50:15 +0200
>> "Michael S. Tsirkin"
On Thu, 2015-12-31 at 16:50 +0800, Yongji Xie wrote:
> Current vfio-pci implementation disallows to mmap MSI-X
> table in case that user get to touch this directly.
>
> However, EEH mechanism can ensure that a given pci device
> can only shoot the MSIs assigned for its PE. So we think
> it's safe
On Thu, 2015-12-31 at 16:50 +0800, Yongji Xie wrote:
> When vfio passthrough a PCI device of which MMIO BARs
> are smaller than PAGE_SIZE, guest will not handle the
> mmio accesses to the BARs which leads to mmio emulations
> in host.
>
> This is because vfio will not allow to passthrough one
>
Happy new year !
On Wed, 16 Dec 2015 18:24:03 +0100
Greg Kurz wrote:
> The get and set operations got exchanged by mistake when moving the
> code from book3s.c to powerpc.c.
>
> Fixes: 3840edc8033ad5b86deee309c1c321ca54257452
> Signed-off-by: Greg Kurz
Happy new year !
On Wed, 16 Dec 2015 18:24:03 +0100
Greg Kurz wrote:
> The get and set operations got exchanged by mistake when moving the
> code from book3s.c to powerpc.c.
>
> Fixes: 3840edc8033ad5b86deee309c1c321ca54257452
> Signed-off-by: Greg Kurz
On Mon, 2016-01-04 at 14:07 -0700, Alex Williamson wrote:
> On Thu, 2015-12-31 at 16:50 +0800, Yongji Xie wrote:
> > Current vfio-pci implementation disallows to mmap MSI-X
> > table in case that user get to touch this directly.
> >
> > However, EEH mechanism can ensure that a given pci device
>
On Mon, Jan 04, 2016 at 02:33:12PM -0800, Andy Lutomirski wrote:
> On Mon, Jan 4, 2016 at 12:26 PM, Marcelo Tosatti wrote:
> > On Sun, Dec 20, 2015 at 03:05:41AM -0800, Andy Lutomirski wrote:
> >> From: Andy Lutomirski
> >>
> >> The pvclock vdso code was
On Mon, Jan 4, 2016 at 12:26 PM, Marcelo Tosatti wrote:
> On Sun, Dec 20, 2015 at 03:05:41AM -0800, Andy Lutomirski wrote:
>> From: Andy Lutomirski
>>
>> The pvclock vdso code was too abstracted to understand easily and
>> excessively paranoid. Simplify
On Wed, 2015-12-23 at 13:08 +0100, Pierre Morel wrote:
> The flags entry is there to tell the user that some
> optional information is available.
>
> Since we report the iova_pgsizes signal it to the user
> by setting the flags to VFIO_IOMMU_INFO_PGSIZES.
>
> Signed-off-by: Pierre Morel
On Mon, Jan 4, 2016 at 12:41 PM, Konrad Rzeszutek Wilk
wrote:
> On Sun, Dec 13, 2015 at 01:28:09PM -0800, Alexander Duyck wrote:
>> This patch set is meant to be the guest side code for a proof of concept
>> involving leaving pass-through devices in the guest during the
On 2016/1/4 14:22, Jason Wang wrote:
On 01/04/2016 09:39 AM, Yang Zhang wrote:
On 2015/12/31 15:13, Jason Wang wrote:
This patch tries to implement an device IOTLB for vhost. This could be
used with for co-operation with userspace(qemu) implementation of
iommu for a secure DMA environment in
"Matwey V. Kornilov" writes:
> Hello,
>
> According to WikiPedia VIA claims x86 hardware assisted virtualization
> for VIA Eden X4 CPU.
> Does anybody know if it is supported by Linux KVM?
>
I can't say for sure but my guess is that it should work since VIA implements
On 2015/12/31 15:13, Jason Wang wrote:
This patch tries to implement an device IOTLB for vhost. This could be
used with for co-operation with userspace(qemu) implementation of
iommu for a secure DMA environment in guest.
The idea is simple. When vhost meets an IOTLB miss, it will request
the
On 2015年12月30日 00:46, Michael S. Tsirkin wrote:
> Interesting. So you sare saying merely ifdown/ifup is 100ms?
> This does not sound reasonable.
> Is there a chance you are e.g. getting IP from dhcp?
>
> If so that is wrong - clearly should reconfigure the old IP
> back without playing with dhcp.
> -Original Message-
> From: Radim Krčmář [mailto:rkrc...@redhat.com]
> Sent: Thursday, December 24, 2015 1:22 AM
> To: Wu, Feng <feng...@intel.com>
> Cc: pbonz...@redhat.com; kvm@vger.kernel.org; linux-
> ker...@vger.kernel.org
> Subject: Re: [PATCH v2 2/2] KV
On 01/04/2016 09:39 AM, Yang Zhang wrote:
> On 2015/12/31 15:13, Jason Wang wrote:
>> This patch tries to implement an device IOTLB for vhost. This could be
>> used with for co-operation with userspace(qemu) implementation of
>> iommu for a secure DMA environment in guest.
>>
>> The idea is
On 12/31/2015 07:17 PM, Michael S. Tsirkin wrote:
> On Thu, Dec 31, 2015 at 03:13:45PM +0800, Jason Wang wrote:
>> This patch tries to implement an device IOTLB for vhost. This could be
>> used with for co-operation with userspace(qemu) implementation of
>> iommu for a secure DMA environment in
On 12/22/2015 05:07 PM, Stefan Hajnoczi wrote:
> This series is based on v4.4-rc2 and the "virtio: make find_vqs()
> checkpatch.pl-friendly" patch I recently submitted.
>
> v4:
> * Addressed code review comments from Alex Bennee
> * MAINTAINERS file entries for new files
> * Trace events
On Thu, Dec 31, 2015 at 03:13:45PM +0800, Jason Wang wrote:
> This patch tries to implement an device IOTLB for vhost. This could be
> used with for co-operation with userspace(qemu) implementation of
> iommu for a secure DMA environment in guest.
>
> The idea is simple. When vhost meets an IOTLB
On Wed, Dec 30, 2015 at 04:55:54PM +0100, Igor Mammedov wrote:
> On Mon, 28 Dec 2015 14:50:15 +0200
> "Michael S. Tsirkin" wrote:
>
> > On Mon, Dec 28, 2015 at 10:39:04AM +0800, Xiao Guangrong wrote:
> > >
> > > Hi Michael, Paolo,
> > >
> > > Now it is the time to return to
On Mon, 28 Dec 2015 14:50:15 +0200
"Michael S. Tsirkin" wrote:
> On Mon, Dec 28, 2015 at 10:39:04AM +0800, Xiao Guangrong wrote:
> >
> > Hi Michael, Paolo,
> >
> > Now it is the time to return to the challenge that how to reserve guest
> > physical region internally used by
On 29/12/2015 17:37, David Matlack wrote:
>> > Yes, it's correct.
s/it's/you're/ :)
Paolo
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On Wed, Dec 30, 2015 at 3:36 AM, Paolo Bonzini wrote:
>
>
> On 29/12/2015 17:37, David Matlack wrote:
>>> > Yes, it's correct.
>
> s/it's/you're/ :)
Ah ok. Thanks for your help!
I will send a patch to fix the comment then.
>
> Paolo
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