. On systems with two threads per core this patch halves
the size of the lpid pool that the allocator sees and use two lpids per VM.
Use even numbers to speedup vcpu lpid computation with consecutive lpids
per VM: vm1 will use lpids 2 and 3, vm2 lpids 4 and 5, and so on.
Signed-off-by: Mihai Caraman
Now that AltiVec and hardware thread support is in place enable e6500 core.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v2:
- new patch
arch/powerpc/kvm/e500mc.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/powerpc/kvm/e500mc.c b/arch/powerpc/kvm
We currently decide at compile-time which of the SPE or AltiVec units to
support exclusively. Guard kernel defines with CONFIG_SPE_POSSIBLE and
CONFIG_PPC_E500MC and remove shared defines.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
arch/powerpc/include/asm/kvm_asm.h | 20
Powerpc timer implementation is a copycat version of s390. Now that they removed
the tasklet with commit ea74c0ea1b24a6978a6ebc80ba4dbc7b7848b32d follow this
optimization.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
Signed-off-by: Bogdan Purcareata bogdan.purcare...@freescale.com
Now that AltiVec and hardware threading support are in place enable e6500 core.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
arch/powerpc/kvm/e500mc.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/powerpc/kvm/e500mc.c b/arch/powerpc/kvm/e500mc.c
index
SPE exception handlers are now defined for 32-bit e500mc cores even though
SPE unit is not present and CONFIG_SPE is undefined.
Restrict SPE exception handlers to e200/e500 cores adding CONFIG_SPE_POSSIBLE
and consequently guard __stup_ivors and __setup_cpu functions.
Signed-off-by: Mihai
readability
especially in KVM.
Use distinct defines to identify SPE/AltiVec interrupt numbers, reverting
c58ce397 and 6b310fc5 patches that added common defines.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
Cc: Scott Wood scottw...@freescale.com
Cc: Alexander Graf ag...@suse.de
---
arch
into account feedback
Mihai Caraman (6):
KVM: PPC: Book3E: Increase FPU laziness
KVM: PPC: Book3e: Add AltiVec support
KVM: PPC: Make ONE_REG powerpc generic
KVM: PPC: Move ONE_REG AltiVec support to powerpc
KVM: PPC: Booke: Add setter functions for IVPR, IVOR2 and IVOR8
emulation
KVM: PPC
Add ONE_REG support for IVPR and IVORs registers. Implement IVPR, IVORs 0-15
and 35 in booke common layer.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v4:
- add ONE_REG IVPR
- use IVPR, IVOR2 and IVOR8 setters
- add api documentation for ONE_REG IVPR and IVORs
v3:
- new
Make ONE_REG generic for server and embedded architectures by moving
kvm_vcpu_ioctl_get_one_reg() and kvm_vcpu_ioctl_set_one_reg() functions
to powerpc layer.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v4:
- split ONE_REG powerpc generic and ONE_REG AltiVec
v3:
- make ONE_REG
Move ONE_REG AltiVec support to powerpc generic layer.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v4:
- split ONE_REG powerpc generic and ONE_REG AltiVec
v3:
- make ONE_REG AltiVec support powerpc generic
v2:
- add comment describing VCSR register representation in KVM vs
AltiVec, so we always need to support
AltiVec in KVM and implicitly in host to reflect interrupts and to save/restore
the unit context. KVM will be loaded on cores with AltiVec unit only if
CONFIG_ALTIVEC is defined. Use this define to guard KVM AltiVec logic.
Signed-off-by: Mihai Caraman mihai.cara
Increase FPU laziness by loading the guest state into the unit before entering
the guest instead of doing it on each vcpu schedule. Without this improvement
an interrupt may claim floating point corrupting guest state.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v4:
- update
Add setter functions for IVPR, IVOR2 and IVOR8 emulation in preparation
for ONE_REG support.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v4:
- new patch
- add api documentation for ONE_REG IVPR and IVORs
arch/powerpc/kvm/booke.c | 24
arch
Though SPE/AltiVec shares interrupts numbers on BookE cores, use distinct
defines to identify these numbers. This improves code readability especially
in KVM.
Revert c58ce397 and 6b310fc5 patches that added common defines.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
arch
SPE exception handlers are now defined for 32-bit e500mc cores even though
SPE unit is not present and CONFIG_SPE is undefined.
Restrict SPE exception handlers to e200/e500 cores adding CONFIG_SPE_POSSIBLE
and consequently guard __stup_ivors and __setup_cpu functions.
Signed-off-by: Mihai
moves lpid to vcpu level and allocates a pool
of lpids (equal to the number of threads per core) per VM.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
Please rebase this patch before
[PATCH v3 5/5] KVM: PPC: Book3E: Enable e6500 core
to proper handle SMP guests.
arch/powerpc
into account feedback
Mihai Caraman (5):
KVM: PPC: Book3e: Increase FPU laziness
KVM: PPC: Book3e: Add AltiVec support
KVM: PPC: Move ONE_REG AltiVec support to powerpc
KVM: PPC: Booke: Add ONE_REG IVORs support
KVM: PPC: Book3e: Enable e6500 core
arch/powerpc/include/uapi/asm/kvm.h | 29
Add KVM Book3e AltiVec support. KVM Book3e FPU support gracefully reuse host
infrastructure so follow the same approach for AltiVec.
Keep SPE/AltiVec exception handlers distinct using CONFIG_KVM_E500V2.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v3:
- use distinct SPE/AltiVec
Make ONE_REG AltiVec support common across server and embedded implementations
moving kvm_vcpu_ioctl_get_one_reg() and kvm_vcpu_ioctl_set_one_reg() functions
to powerpc layer.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v3:
- make ONE_REG AltiVec support powerpc generic
v2
Now that AltiVec support is in place enable e6500 core.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v2-v3:
- no changes
arch/powerpc/kvm/e500mc.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/powerpc/kvm/e500mc.c b/arch/powerpc/kvm/e500mc.c
index 19dd927
Add ONE_REG IVORs support, with IVORs 0-15 and 35 booke common.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v3:
- new patch
arch/powerpc/include/uapi/asm/kvm.h | 24 +++
arch/powerpc/kvm/booke.c| 132
arch/powerpc/kvm/e500
Increase FPU laziness by calling kvmppc_load_guest_fp() just before
returning to guest instead of each sched in. Without this improvement
an interrupt may also claim floting point corrupting guest state.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v3:
- no changes
v2:
- remove
exception handled in the host and the TODO for execute-but-not-read entries
and TLB eviction.
Mihai Caraman (5):
KVM: PPC: e500mc: Revert add load inst fixup
KVM: PPC: Book3e: Add TLBSEL/TSIZE defines for MAS0/1
KVM: PPC: Book3s: Remove kvmppc_read_inst() function
KVM: PPC: Alow
-by: Mihai Caraman mihai.cara...@freescale.com
---
v6:
- rewrite kvmppc_get_last_inst() swap code to be understood at a glimpse :)
- use inst in kvmppc_load_last_inst
- these changes compile on book3s, please validate the functionality and
do the necessary changes!
v5:
- don't swap when load
the interrupt vector from host. This imposes additional
synchronizations
for cores like FSL e6500 that shares host IVOR registers between hardware
threads.
This optimized solution can be later developed on top of this patch.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v6:
- no change
v5
-by: Mihai Caraman mihai.cara...@freescale.com
---
v5
- don't swap when load fail
- convert the return value space of kvmppc_ld()
v4:
- these changes compile on book3s, please validate the functionality and
do the necessary adaptations!
- common declaration and enum for kvmppc_load_last_inst
the execution returns to the lwepx instruction instead of the
fixup, the host ending up in an infinite loop.
Revert the commit add load inst fixup. lwepx issue will be addressed
in a subsequent patch without needing fixup code.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v5-v2
.
With an error returning kvmppc_get_last_inst we can just use completely
get rid of kvmppc_read_inst() and only use kvmppc_get_last_inst() instead.
As a intermediate step get rid of kvmppc_read_inst() and only use kvmppc_ld()
instead.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v5
exception handled in the host and the TODO for execute-but-not-read entries
and TLB eviction.
Mihai Caraman (5):
KVM: PPC: e500mc: Revert add load inst fixup
KVM: PPC: Book3e: Add TLBSEL/TSIZE defines for MAS0/1
KVM: PPC: Book3s: Remove kvmppc_read_inst() function
KVM: PPC: Alow
the interrupt vector from host. This imposes additional
synchronizations
for cores like FSL e6500 that shares host IVOR registers between hardware
threads.
This optimized solution can be later developed on top of this patch.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v5:
- return
Add mising defines MAS0_GET_TLBSEL() and MAS1_GET_TSIZE() for Book3E.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v5-v2:
- no change
arch/powerpc/include/asm/mmu-book3e.h | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/include/asm/mmu
guest request
as a general store.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v2:
- treat the operation as a general store
arch/powerpc/include/asm/kvm_host.h | 1 +
arch/powerpc/kvm/e500_emulate.c | 12
2 files changed, 13 insertions(+)
diff --git a/arch/powerpc
KVM Book3E support for Hardware Page Tablewalk enabled guests.
Mihai Caraman (4):
powerpc/booke64: Add LRAT next and max entries to tlb_core_data
structure
KVM: PPC: Book3E: Handle LRAT error exception
KVM: PPC: e500: TLB emulation for IND entries
KVM: PPC: e500mc: Advertise E.PT
LRAT (Logical to Real Address Translation) is shared between hw threads.
Add LRAT next and max entries to tlb_core_data structure and initialize them.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
arch/powerpc/include/asm/mmu-book3e.h | 7 +++
arch/powerpc/include/asm
is not available just invalidate guest's ea and
report a tlbsx miss. This patch only implements the invalidation and let a TODO
note for searching HW TLB0.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
arch/powerpc/include/asm/mmu-book3e.h | 2 +
arch/powerpc/kvm/e500.h | 81
Handle LRAT error exception with support for lrat mapping and invalidation.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
arch/powerpc/include/asm/kvm_host.h | 1 +
arch/powerpc/include/asm/kvm_ppc.h| 2 +
arch/powerpc/include/asm/mmu-book3e.h | 3 +
arch/powerpc
Enable E.PT for vcpus with MMU MAV 2.0 to support Hardware Page Tablewalk (HTW)
in guests.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
arch/powerpc/kvm/e500_mmu.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/arch/powerpc/kvm/e500_mmu.c b/arch/powerpc
Tlb search operation used for victim hint relies on the default tlb set by the
host. When hardware tablewalk support is enabled in the host, the default tlb is
TLB1 which leads KVM to evict the bolted entry. Set and restore the default tlb
when searching for victim hint.
Signed-off-by: Mihai
guest request
as nop.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
arch/powerpc/kvm/e500_emulate.c | 8
1 file changed, 8 insertions(+)
diff --git a/arch/powerpc/kvm/e500_emulate.c b/arch/powerpc/kvm/e500_emulate.c
index 002d517..98a22e5 100644
--- a/arch/powerpc/kvm
Now that AltiVec support is in place enable e6500 core.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v2:
- no changes
arch/powerpc/kvm/e500mc.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/powerpc/kvm/e500mc.c b/arch/powerpc/kvm/e500mc.c
index c60b653
Add ONE_REG support for AltiVec on Book3E.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v2:
- add comment describing VCSR register representation in KVM vs kernel
arch/powerpc/include/uapi/asm/kvm.h | 5 +
arch/powerpc/kvm/booke.c| 34
-by: Mihai Caraman mihai.cara...@freescale.com
---
v2:
- enable SPE only if !HV SPE
arch/powerpc/kvm/booke.c | 93 +++-
1 file changed, 60 insertions(+), 33 deletions(-)
diff --git a/arch/powerpc/kvm/booke.c b/arch/powerpc/kvm/booke.c
index 3c86d9b..80cd8df
Use common BOOKE_IRQPRIO and BOOKE_INTERRUPT defines for SPE/FP/AltiVec
which share the same interrupt numbers.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v2:
- remove outdated definitions
arch/powerpc/include/asm/kvm_asm.h| 8
arch/powerpc/kvm/booke.c
Add KVM Book3E AltiVec support. KVM Book3E FPU support gracefully reuse host
infrastructure so follow the same approach for AltiVec.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v2:
- integrate Paul's FP/VMX/VSX changes
arch/powerpc/kvm/booke.c | 67
Add KVM Book3E AltiVec support and enable e6500 core.
Integrates Paul's FP/VMX/VSX changes that landed in kvm-ppc-queue in January
and take into account feedback.
Mihai Caraman (6):
KVM: PPC: Book3E: Use common defines for SPE/FP/AltiVec int numbers
KVM: PPC: Book3E: Refactor SPE/FP exit
Increase FPU laziness by calling kvmppc_load_guest_fp() just before
returning to guest instead of each sched in. Without this improvement
an interrupt may also claim floting point corrupting guest state.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v2:
- remove fpu_active
- add
Add mising defines MAS0_GET_TLBSEL() and MAS1_GET_TSIZE() for Book3E.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v4-v2:
- no change
arch/powerpc/include/asm/mmu-book3e.h | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/include/asm/mmu
.
With an error returning kvmppc_get_last_inst we can just use completely
get rid of kvmppc_read_inst() and only use kvmppc_get_last_inst() instead.
As a intermediate step get rid of kvmppc_read_inst() and only use kvmppc_ld()
instead.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v4
vector from host. Some cores share host IVOR registers
between hardware threads, which is the case of FSL e6500, which impose
additional
synchronization logic for this solution to work. The optimization can be
addressed
later on top of this patch.
Signed-off-by: Mihai Caraman mihai.cara
-by: Mihai Caraman mihai.cara...@freescale.com
---
v4:
- these changes compile on book3s, please validate the functionality and
do the necessary adaptations!
- common declaration and enum for kvmppc_load_last_inst()
- remove kvmppc_read_inst() in a preceding patch
v3:
- rework patch
the execution returns to the lwepx instruction instead of the
fixup, the host ending up in an infinite loop.
Revert the commit add load inst fixup. lwepx issue will be addressed
in a subsequent patch without needing fixup code.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v4-v2
exception handled in the host and the TODO for execute-but-not-read entries
and TLB eviction.
Mihai Caraman (5):
KVM: PPC: e500mc: Revert add load inst fixup
KVM: PPC: Book3e: Add TLBSEL/TSIZE defines for MAS0/1
KVM: PPC: Book3s: Remove kvmppc_read_inst() function
KVM: PPC: Alow
;
for (i = 0; i ITERATIONS; i++)
for (j = 0; j ENTRIES; j++)
bar = foo[j][0];
return 0;
}
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
Cc: Scott Wood scottw...@freescale.com
---
v4:
- rename last_vcpu_on_cpu to last_vcpu_of_lpid
- use
.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
Cc: Bharat Bhushan bharat.bhus...@freescale.com
---
arch/powerpc/kvm/e500_mmu_host.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/kvm/e500_mmu_host.c b/arch/powerpc/kvm/e500_mmu_host.c
index 0528fe5
;
for (i = 0; i ITERATIONS; i++)
for (j = 0; j ENTRIES; j++)
bar = foo[j][0];
return 0;
}
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
Cc: Scott Wood scottw...@freescale.com
---
v2:
- improve patch name and description
- add performance
;
for (i = 0; i ITERATIONS; i++)
for (j = 0; j ENTRIES; j++)
bar = foo[j][0];
return 0;
}
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
Cc: Scott Wood scottw...@freescale.com
---
v3:
- use existing logic while keeping
Add mising defines MAS0_GET_TLBSEL() and MAS1_GET_TSIZE() for Book3E.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v3:
- no change
v2:
- no change
arch/powerpc/include/asm/mmu-book3e.h | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc
vector from host. Some cores share host IVOR registers
between hardware threads, which is the case of FSL e6500, which impose
additional
synchronization logic for this solution to work. This optimized solution can
be developed later on top of this patch.
Signed-off-by: Mihai Caraman mihai.cara
-by: Mihai Caraman mihai.cara...@freescale.com
---
v3:
- these changes compile on book3s, please validate the functionality and
do the necessary adaptations!
- rework patch description
- add common definition for kvmppc_get_last_inst()
- check return values in book3s code
v2:
- integrated
the execution returns to the lwepx instruction instead of the
fixup, the host ending up in an infinite loop.
Revert the commit add load inst fixup. lwepx issue will be addressed
in a subsequent patch without needing fixup code.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v3:
- no change
exception handled in the host and the TODO for execute-but-not-read entries
and TLB eviction.
Mihai Caraman (4):
KVM: PPC: e500mc: Revert add load inst fixup
KVM: PPC: Book3e: Add TLBSEL/TSIZE defines for MAS0/1
KVM: PPC: Alow kvmppc_get_last_inst() to fail
KVM: PPC: Bookehv: Get vcpu's
Add defines MAS0_GET_TLBSEL() and MAS1_GET_TSIZE() to Book3E.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v2:
- no change
arch/powerpc/include/asm/mmu-book3e.h | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/include/asm/mmu-book3e.h
b
Add mising defines MAS0_GET_TLBSEL() and MAS1_GET_TSIZE() for Book3E.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
arch/powerpc/include/asm/mmu-book3e.h |6 +-
1 files changed, 5 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/include/asm/mmu-book3e.h
b/arch
address and kmap it. This fixes an
infinite loop caused by lwepx's data TLB miss handled in the host
and the TODO for TLB eviction and execute-but-not-read entries.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
arch/powerpc/kvm/bookehv_interrupts.S | 37 +++--
arch/powerpc/kvm
to Booke3E 64-bit kernel and the basic KVM
handler to avoid build breakage. This is a prerequisite for KVM LRAT support
that will follow.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v2
- squash patches for bisectability
- set IVOR42 from setup_cpu
arch/powerpc/include/asm/kvm_asm.h
Add KVM Book3E AltiVec support. KVM Book3E FPU support gracefully reuse host
infrastructure so follow the same approach for AltiVec.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
arch/powerpc/kvm/booke.c | 72 -
1 files changed, 70
Add ONE_REG support for AltiVec on Book3E.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
arch/powerpc/kvm/booke.c | 32
1 files changed, 32 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/kvm/booke.c b/arch/powerpc/kvm/booke.c
index
Use common BOOKE_IRQPRIO and BOOKE_INTERRUPT defines for SPE/FP/AltiVec
which share the same interrupts numbers.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
arch/powerpc/kvm/booke.c | 16
arch/powerpc/kvm/booke.h |4 ++--
arch
Add KVM Book3E AltiVec support and enable e6500 core.
Mihai Caraman (6):
KVM: PPC: Book3E: Use common defines for SPE/FP/AltiVec int numbers
KVM: PPC: Book3E: Refactor SPE/FP exit handling
KVM: PPC: Book3E: Increase FPU laziness
KVM: PPC: Book3E: Add AltiVec support
KVM: PPC: Book3E
SPE/FP/AltiVec interrupts share the same numbers. Refactor SPE/FP exit handling
to accommodate AltiVec later. Detect the targeted unit at run time since it can
be configured in the kernel but not featured on hardware.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
arch/powerpc/kvm
Increase FPU laziness by calling kvmppc_load_guest_fp() just before
returning to guest instead of each sched in. Without this improvement
an interrupt may also claim floting point corrupting guest state.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
arch/powerpc/kvm/booke.c
Now that AltiVec support is in place enable e6500 core.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
arch/powerpc/kvm/e500mc.c | 10 ++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/kvm/e500mc.c b/arch/powerpc/kvm/e500mc.c
index 09da1ac
Some guests are making use of return from machine check instruction
to do crazy things even though the 64-bit kernel doesn't handle yet
this interrupt. Emulate MCSRR0/1 SPR and rfmci instruction accordingly.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
arch/powerpc/include/asm
Some exit ids where left out from kvm_exit_names array.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
arch/powerpc/kvm/timing.c |4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/kvm/timing.c b/arch/powerpc/kvm/timing.c
index 07b6110..c392d26
Add LRAT (Logical to Real Address Translation) error exception handler to
Booke3E 64-bit kernel. LRAT support in KVM will follow afterwards.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
arch/powerpc/include/asm/kvm_asm.h |1 +
arch/powerpc/include/asm/reg_booke.h |1
With LRAT (Logical to Real Address Translation) error exception handler in
kernel
KVM needs to add the counterpart otherwise will break the build.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
arch/powerpc/kvm/bookehv_interrupts.S |2 ++
1 files changed, 2 insertions(+), 0
On Book3E some SPE/FP/AltiVec interrupts share the same number. Use
common defines to indentify these numbers.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
arch/powerpc/kernel/head_fsl_booke.S | 12 ++--
1 files changed, 6 insertions(+), 6 deletions(-)
diff --git
On Book3E some SPE/FP/AltiVec interrupts share the same number. Use
common defines to indentify these numbers.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
arch/powerpc/kernel/exceptions-64e.S |5 +++--
1 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch
-but-not-read entries.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
Resend this pacth for Alex G. he was unsubscribed from kvm-ppc mailist
for a while.
arch/powerpc/include/asm/mmu-book3e.h |6 ++-
arch/powerpc/kvm/booke.c |6 +++
arch/powerpc/kvm/booke.h
fixup. We will address lwepx
issue in a subsequent patch without the need of fixups.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
Resend this patch for Alex G. he was unsubscribed from kvm-ppc mailist
for a while.
arch/powerpc/kvm/bookehv_interrupts.S | 26
-but-not-read entries.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
arch/powerpc/include/asm/mmu-book3e.h |6 ++-
arch/powerpc/kvm/booke.c |6 +++
arch/powerpc/kvm/booke.h |2 +
arch/powerpc/kvm/bookehv_interrupts.S | 32 ++-
arch
Mihai Caraman (6):
KVM: PPC: Book3E: Fix AltiVec interrupt numbers and build breakage
KVM: PPC: Book3E: Refactor SPE_FP exit handling
KVM: PPC: Book3E: Rename IRQPRIO names to accommodate ALTIVEC
KVM: PPC: Book3E: Add AltiVec support
KVM: PPC: Book3E: Add ONE_REG AltiVec support
KVM
Add ONE_REG support for AltiVec on Book3E.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
arch/powerpc/kvm/booke.c | 32
1 files changed, 32 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/kvm/booke.c b/arch/powerpc/kvm/booke.c
index
Rename BOOKE_IRQPRIO_SPE_UNAVAIL and BOOKE_IRQPRIO_SPE_FP_DATA names
to accommodate ALTIVEC. Replace BOOKE_INTERRUPT_SPE_UNAVAIL and
BOOKE_INTERRUPT_SPE_FP_DATA with the common version.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
arch/powerpc/kvm/booke.c | 12
SPE_FP interrupts are shared with ALTIVEC. Refactor SPE_FP exit handling
to detect KVM support for the featured unit at run-time, in order to
accommodate ALTIVEC later.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
arch/powerpc/kvm/booke.c | 80
Interrupt numbers defined for Book3E follows IVORs definition. Align
BOOKE_INTERRUPT_ALTIVEC_UNAVAIL and BOOKE_INTERRUPT_ALTIVEC_ASSIST to this
rule which also fixes the build breakage.
IVORs 32 and 33 are shared so reflect this in the interrupts naming.
Signed-off-by: Mihai Caraman mihai.cara
not guarantees to hard enable interrupts. To do so replace exception
function calls like timer_interrupt() with irq_happened flags. The
local_irq_enable() call takes care of replaying them and lets the interrupts
hard enabled.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
arch/powerpc/kvm
Add support for TLBnPS registers available in MMU Architecture Version
(MAV) 2.0.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v3:
- Add vcpu_ftr enum
v2:
- Add vcpu generic function has_feature()
Documentation/virtual/kvm/api.txt |4
arch/powerpc/include/asm
MMU registers were exposed to user-space using sregs interface. Add them
to ONE_REG interface using kvmppc_get_one_reg/kvmppc_set_one_reg delegation
mechanism.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v3:
- Fix case breaks
v2:
- Restrict set_one_reg operation for MMU
Embedded.Page Table (E.PT) category is not supported yet in e6500 kernel.
Configure TLBnCFG to remove E.PT and E.HV.LRAT categories from VCPUs.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v3:
- No change
arch/powerpc/kvm/e500_mmu.c |4
1 files changed, 4 insertions
Vcpu's MMU default configuration and geometry update logic was buried in
a chunk of code. Move them to dedicated functions to add more clarity.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v3:
- No change
v2:
- Add better patch description
arch/powerpc/kvm/e500_mmu.c | 60
EPTCFG register defined by E.PT is accessed unconditionally by Linux guests
in the presence of MAV 2.0. Emulate it now.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v3:
- Initialize EPTCFG to 0 since E.PT is not supported now
Documentation/virtual/kvm/api.txt |1 +
arch
Enable basic support for Freescale e6500 core, adding MAV 2.0 support.
Validated on T4240QDS platfrom. Altivec, Multithreading and HW Tablewalk
are not addressed by this patchset.
Mihai Caraman (8):
KVM: PPC: Book3E: Refactor ONE_REG ioctl implementation
KVM: PPC: e500: Expose MMU registers
Refactor Book3E ONE_REG ioctl implementation to use kvmppc_get_one_reg/
kvmppc_set_one_reg delegation interface introduced by Book3S. This is
necessary for MMU SPRs which are platform specifics.
Get rid of useless case braces in the process.
Signed-off-by: Mihai Caraman mihai.cara
EPTCFG register defined by E.PT is accessed unconditionally by Linux guests
in the presence of MAV 2.0. Support it now.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v2:
- Use has_feature() function
Documentation/virtual/kvm/api.txt |1 +
arch/powerpc/include/asm
Extend processor compatibility names to e6500 cores.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
Reviewed-by: Alexander Graf ag...@suse.de
---
v2:
- No change
arch/powerpc/kvm/e500mc.c |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/kvm
Add e6500 core to Kconfig description.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v2:
- New patch
arch/powerpc/kvm/Kconfig |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/kvm/Kconfig b/arch/powerpc/kvm/Kconfig
index 63c67ec..4489520
Add support for TLBnPS registers available in MMU Architecture Version
(MAV) 2.0.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v2:
- Add vcpu generic function has_feature()
Documentation/virtual/kvm/api.txt |4
arch/powerpc/include/asm/kvm_host.h |1 +
arch
Vcpu's MMU default configuration and geometry update logic was buried in
a chunk of code. Move them to dedicated functions to add more clarity.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v2:
- Add better patch description. Hopefully :)
arch/powerpc/kvm/e500_mmu.c | 60
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