On 13.08.14 11:09, Bharat Bhushan wrote:
This patch emulates debug registers and debug exception
to support guest using debug resource. This enables running
gdb/kgdb etc in guest.
On BOOKE architecture we cannot share debug resources between QEMU and
guest because:
When QEMU is using
On 20.08.14 15:36, Mihai Caraman wrote:
Add setter functions for IVPR, IVOR2 and IVOR8 emulation in preparation
for ONE_REG support.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
What about the other GIVORs?
Also, I would prefer to have a common helper for IVOR setting that
On Wed, 2014-08-27 at 13:23 +0200, Alexander Graf wrote:
On 13.08.14 11:09, Bharat Bhushan wrote:
This patch emulates debug registers and debug exception
to support guest using debug resource. This enables running
gdb/kgdb etc in guest.
On BOOKE architecture we cannot share debug
On Thursday 21 August 2014 02:40 PM, Alexander Graf wrote:
On 20.08.14 07:52, Madhavan Srinivasan wrote:
This patch adds kernel side support for software breakpoint.
Design is that, by using an illegal instruction, we trap to hypervisor
via Emulation Assistance interrupt, where we check
Am 23.08.2014 um 12:17 schrieb Madhavan Srinivasan ma...@linux.vnet.ibm.com:
On Thursday 21 August 2014 02:40 PM, Alexander Graf wrote:
On 20.08.14 07:52, Madhavan Srinivasan wrote:
This patch adds kernel side support for software breakpoint.
Design is that, by using an illegal
On 20.08.14 07:52, Madhavan Srinivasan wrote:
This patch adds kernel side support for software breakpoint.
Design is that, by using an illegal instruction, we trap to hypervisor
via Emulation Assistance interrupt, where we check for the illegal instruction
and accordingly we return to Host
SPE exception handlers are now defined for 32-bit e500mc cores even though
SPE unit is not present and CONFIG_SPE is undefined.
Restrict SPE exception handlers to e200/e500 cores adding CONFIG_SPE_POSSIBLE
and consequently guard __stup_ivors and __setup_cpu functions.
Signed-off-by: Mihai
Book3E specification defines shared interrupt numbers for SPE and AltiVec
units. Still SPE is present in e200/e500v2 cores while AltiVec is present in
e6500 core. So we can currently decide at compile-time which unit to support
exclusively. As Alexander Graf suggested, this will improve code
Add KVM Book3e AltiVec support.
Changes:
v4:
- use CONFIG_SPE_POSSIBLE and a new ifdef for CONFIG_ALTIVEC
- remove SPE handlers from bookehv
- split ONE_REG powerpc generic and ONE_REG AltiVec
- add setters for IVPR, IVOR2 and IVOR8
- add api documentation for ONE_REG IVPR and IVORs
-
Add ONE_REG support for IVPR and IVORs registers. Implement IVPR, IVORs 0-15
and 35 in booke common layer.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v4:
- add ONE_REG IVPR
- use IVPR, IVOR2 and IVOR8 setters
- add api documentation for ONE_REG IVPR and IVORs
v3:
- new
Make ONE_REG generic for server and embedded architectures by moving
kvm_vcpu_ioctl_get_one_reg() and kvm_vcpu_ioctl_set_one_reg() functions
to powerpc layer.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v4:
- split ONE_REG powerpc generic and ONE_REG AltiVec
v3:
- make ONE_REG
Move ONE_REG AltiVec support to powerpc generic layer.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v4:
- split ONE_REG powerpc generic and ONE_REG AltiVec
v3:
- make ONE_REG AltiVec support powerpc generic
v2:
- add comment describing VCSR register representation in KVM vs
Add AltiVec support in KVM for Book3e. FPU support gracefully reuse host
infrastructure so follow the same approach for AltiVec.
Book3e specification defines shared interrupt numbers for SPE and AltiVec
units. Still SPE is present in e200/e500v2 cores while AltiVec is present in
e6500 core. So we
Increase FPU laziness by loading the guest state into the unit before entering
the guest instead of doing it on each vcpu schedule. Without this improvement
an interrupt may claim floating point corrupting guest state.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v4:
- update
Add setter functions for IVPR, IVOR2 and IVOR8 emulation in preparation
for ONE_REG support.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v4:
- new patch
- add api documentation for ONE_REG IVPR and IVORs
arch/powerpc/kvm/booke.c | 24
On Wed, 2014-08-20 at 16:09 +0300, Mihai Caraman wrote:
SPE exception handlers are now defined for 32-bit e500mc cores even though
SPE unit is not present and CONFIG_SPE is undefined.
Restrict SPE exception handlers to e200/e500 cores adding CONFIG_SPE_POSSIBLE
and consequently guard
On Wed, 2014-08-20 at 16:09 +0300, Mihai Caraman wrote:
Book3E specification defines shared interrupt numbers for SPE and AltiVec
units. Still SPE is present in e200/e500v2 cores while AltiVec is present in
e6500 core. So we can currently decide at compile-time which unit to support
On Thu, Aug 14, 2014 at 03:03:07PM +1000, Alexey Kardashevskiy wrote:
fc95ca7284bc54953165cba76c3228bd2cdb9591 claims that there is no
functional change but this is not true as it calls get_order() (which
takes bytes) where it should have called ilog2() and the kernel stops
on VM_BUG_ON().
This patch adds kernel side support for software breakpoint.
Design is that, by using an illegal instruction, we trap to hypervisor
via Emulation Assistance interrupt, where we check for the illegal instruction
and accordingly we return to Host or Guest. Patch also adds support for
software
This cleans up kvmppc_load/save_fp. It removes unnecessary isyncs. It also
removes the unnecessary resetting of the MSR bits on exit of kvmppc_save_fp.
Signed-off-by: Michael Neuling mi...@neuling.org
Signed-off-by: Paul Mackerras pau...@samba.org
---
arch/powerpc/kvm/book3s_hv_rmhandlers.S |
On Tue, Aug 19, 2014 at 02:59:29PM +1000, Michael Neuling wrote:
This cleans up kvmppc_load/save_fp. It removes unnecessary isyncs.
NAK - they are necessary on PPC970, which we (still) support. You
could put them in a feature section if they are really annoying you.
It also
removes the
On Tue, 2014-08-19 at 15:24 +1000, Paul Mackerras wrote:
On Tue, Aug 19, 2014 at 02:59:29PM +1000, Michael Neuling wrote:
This cleans up kvmppc_load/save_fp. It removes unnecessary isyncs.
NAK - they are necessary on PPC970, which we (still) support. You
could put them in a feature
On 14.08.14 07:13, Aneesh Kumar K.V wrote:
Alexey Kardashevskiy a...@ozlabs.ru writes:
fc95ca7284bc54953165cba76c3228bd2cdb9591 claims that there is no
functional change but this is not true as it calls get_order() (which
takes bytes) where it should have called ilog2() and the kernel stops
On 08/14/2014 11:40 PM, Alexander Graf wrote:
On 14.08.14 07:13, Aneesh Kumar K.V wrote:
Alexey Kardashevskiy a...@ozlabs.ru writes:
fc95ca7284bc54953165cba76c3228bd2cdb9591 claims that there is no
functional change but this is not true as it calls get_order() (which
takes bytes) where it
This patch emulates debug registers and debug exception
to support guest using debug resource. This enables running
gdb/kgdb etc in guest.
On BOOKE architecture we cannot share debug resources between QEMU and
guest because:
When QEMU is using debug resources then debug exception must
be
This was missed in respective one_reg implementation patch.
Signed-off-by: Bharat Bhushan bharat.bhus...@freescale.com
---
Documentation/virtual/kvm/api.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/virtual/kvm/api.txt
b/Documentation/virtual/kvm/api.txt
index
Alexey Kardashevskiy a...@ozlabs.ru writes:
fc95ca7284bc54953165cba76c3228bd2cdb9591 claims that there is no
functional change but this is not true as it calls get_order() (which
takes bytes) where it should have called ilog2() and the kernel stops
on VM_BUG_ON().
This replaces get_order()
fc95ca7284bc54953165cba76c3228bd2cdb9591 claims that there is no
functional change but this is not true as it calls get_order() (which
takes bytes) where it should have called ilog2() and the kernel stops
on VM_BUG_ON().
This replaces get_order() with order_base_2() (round-up version of ilog2).
Alexey Kardashevskiy a...@ozlabs.ru writes:
fc95ca7284bc54953165cba76c3228bd2cdb9591 claims that there is no
functional change but this is not true as it calls get_order() (which
takes bytes) where it should have called ilog2() and the kernel stops
on VM_BUG_ON().
This replaces get_order()
On 06.08.14 08:38, Bharat Bhushan wrote:
Signed-off-by: Bharat Bhushan bharat.bhus...@freescale.com
---
v2-v3
- New patch
arch/powerpc/include/uapi/asm/kvm.h | 1 +
arch/powerpc/kvm/booke.c| 6 ++
2 files changed, 7 insertions(+)
diff --git
On 06.08.14 08:38, Bharat Bhushan wrote:
This patchset adds debug register and interrupt emulation
support for guest, which enables running gdb/kgdb etc in guest.
v2-v3
- Added One-reg interface for DBSR
- removed arch-shadow_dbg_reg
- Addressed some more comments on v2 (detail in
-Original Message-
From: Alexander Graf [mailto:ag...@suse.de]
Sent: Tuesday, August 12, 2014 3:55 PM
To: Bhushan Bharat-R65777; kvm-ppc@vger.kernel.org
Cc: k...@vger.kernel.org; Wood Scott-B07421; Yoder Stuart-B08248
Subject: Re: [PATCH 0/7 v3] Guest debug emulation
On
On 05.08.14 12:39, Mihai Caraman wrote:
Make ONE_REG AltiVec support common across server and embedded implementations
moving kvm_vcpu_ioctl_get_one_reg() and kvm_vcpu_ioctl_set_one_reg() functions
to powerpc layer.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
Please split this
On 05.08.14 12:39, Mihai Caraman wrote:
Add ONE_REG IVORs support, with IVORs 0-15 and 35 booke common.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v3:
- new patch
arch/powerpc/include/uapi/asm/kvm.h | 24 +++
arch/powerpc/kvm/booke.c| 132
On 12.08.14 13:35, Madhavan Srinivasan wrote:
On Tuesday 12 August 2014 04:49 PM, Alexander Graf wrote:
On 12.08.14 07:17, Madhavan Srinivasan wrote:
On Monday 11 August 2014 02:45 PM, Alexander Graf wrote:
On 11.08.14 10:51, Benjamin Herrenschmidt wrote:
On Mon, 2014-08-11 at 09:26 +0200,
On Tuesday 12 August 2014 05:45 PM, Alexander Graf wrote:
On 12.08.14 13:35, Madhavan Srinivasan wrote:
On Tuesday 12 August 2014 04:49 PM, Alexander Graf wrote:
On 12.08.14 07:17, Madhavan Srinivasan wrote:
On Monday 11 August 2014 02:45 PM, Alexander Graf wrote:
On 11.08.14 10:51,
On Tue, 2014-08-12 at 02:36 -0500, Bhushan Bharat-R65777 wrote:
-Original Message-
From: Wood Scott-B07421
Sent: Tuesday, August 12, 2014 5:30 AM
To: Bhushan Bharat-R65777
Cc: ag...@suse.de; kvm-ppc@vger.kernel.org; k...@vger.kernel.org; Yoder
Stuart-
B08248
Subject: Re:
fc95ca7284bc54953165cba76c3228bd2cdb9591 claims that there is no
functional change but this is not true as it calls get_order() (which
takes bytes) where it should have called ilog2() and the kernel stops
on VM_BUG_ON().
This replaces get_order() with ilog2().
Suggested-by: Paul Mackerras
On 01.08.14 06:50, Madhavan Srinivasan wrote:
This patch adds kernel side support for software breakpoint.
Design is that, by using an illegal instruction, we trap to hypervisor
via Emulation Assistance interrupt, where we check for the illegal instruction
and accordingly we return to Host or
On Mon, 2014-08-11 at 09:26 +0200, Alexander Graf wrote:
diff --git a/arch/powerpc/kvm/emulate.c b/arch/powerpc/kvm/emulate.c
index da86d9b..d95014e 100644
--- a/arch/powerpc/kvm/emulate.c
+++ b/arch/powerpc/kvm/emulate.c
This should be book3s_emulate.c.
Any reason we can't make that
On 11.08.14 10:51, Benjamin Herrenschmidt wrote:
On Mon, 2014-08-11 at 09:26 +0200, Alexander Graf wrote:
diff --git a/arch/powerpc/kvm/emulate.c b/arch/powerpc/kvm/emulate.c
index da86d9b..d95014e 100644
--- a/arch/powerpc/kvm/emulate.c
+++ b/arch/powerpc/kvm/emulate.c
This should be
On 06.08.14 18:33, Mihai Caraman wrote:
ePAPR represents hardware threads as cpu node properties in device tree.
So with existing QEMU, hardware threads are simply exposed as vcpus with
one hardware thread.
The e6500 core shares TLBs between hardware threads. Without tlb write
conditional
On Wed, 2014-08-06 at 11:39 +0300, Mihai Caraman wrote:
SPE exception handlers are now defined for 32-bit e500mc cores even though
SPE unit is not present and CONFIG_SPE is undefined.
Restrict SPE exception handlers to e200/e500 cores adding CONFIG_SPE_POSSIBLE
and consequently guard
On Wed, 2014-08-06 at 19:33 +0300, Mihai Caraman wrote:
@@ -390,19 +400,30 @@ static void kvmppc_core_vcpu_free_e500mc(struct
kvm_vcpu *vcpu)
static int kvmppc_core_init_vm_e500mc(struct kvm *kvm)
{
- int lpid;
+ int i, lpid;
- lpid = kvmppc_alloc_lpid();
- if
Am 12.08.2014 um 01:36 schrieb Scott Wood scottw...@freescale.com:
On Wed, 2014-08-06 at 19:33 +0300, Mihai Caraman wrote:
@@ -390,19 +400,30 @@ static void kvmppc_core_vcpu_free_e500mc(struct
kvm_vcpu *vcpu)
static int kvmppc_core_init_vm_e500mc(struct kvm *kvm)
{
-int lpid;
+
On Tue, 2014-08-12 at 01:53 +0200, Alexander Graf wrote:
Am 12.08.2014 um 01:36 schrieb Scott Wood scottw...@freescale.com:
On Wed, 2014-08-06 at 19:33 +0300, Mihai Caraman wrote:
@@ -390,19 +400,30 @@ static void kvmppc_core_vcpu_free_e500mc(struct
kvm_vcpu *vcpu)
static int
On Wed, 2014-08-06 at 12:08 +0530, Bharat Bhushan wrote:
@@ -1249,6 +1284,7 @@ int kvmppc_subarch_vcpu_init(struct kvm_vcpu *vcpu)
setup_timer(vcpu-arch.wdt_timer, kvmppc_watchdog_func,
(unsigned long)vcpu);
+ kvmppc_clear_dbsr();
return 0;
This could use
On Wed, Aug 06, 2014 at 02:35:29PM +0200, Paolo Bonzini wrote:
This doesn't build without CONFIG_KVM_XICS, so I had to apply a fixup
patch to move some code from being under CONFIG_HAVE_KVM_IRQCHIP or
unconditional, to being conditional on CONFIG_HAVE_KVM_IRQFD. I'll send
the patch shortly.
This patchset adds debug register and interrupt emulation
support for guest, which enables running gdb/kgdb etc in guest.
v2-v3
- Added One-reg interface for DBSR
- removed arch-shadow_dbg_reg
- Addressed some more comments on v2 (detail in individual patch)
Bharat Bhushan (7):
KVM: PPC:
This patch adds rfdi instruction emulation which is required for
guest debug hander on BOOKE-HV
Signed-off-by: Bharat Bhushan bharat.bhus...@freescale.com
---
v2-v3
- No change
arch/powerpc/include/asm/kvm_host.h | 1 +
arch/powerpc/kvm/booke_emulate.c| 13 +
2 files changed,
Debug interrupt can be either critical level or debug level.
There are separate set of save/restore registers used for different level.
Example: DSRR0/DSRR1 are used for debug level and CSRR0/CSRR1
are used for critical level debug interrupt.
Using CPU_FTR_DEBUG_LVL_EXC to decide which interrupt
Dbsr is not visible to userspace and we do not think any need to
expose this to userspace because:
Userspace cannot inject debug interrupt to guest (as this
does not know guest ability to handle debug interrupt), so
userspace will always clear DBSR.
Now if userspace has to always clear
This patch emulates debug registers and debug exception
to support guest using debug resource. This enables running
gdb/kgdb etc in guest.
On BOOKE architecture we cannot share debug resources between QEMU and
guest because:
When QEMU is using debug resources then debug exception must
be
Guest visible debug register and hardware visible debug registers are
same, so ther is no need to have arch-shadow_dbg_reg, instead use
arch-dbg_reg.
Signed-off-by: Bharat Bhushan bharat.bhus...@freescale.com
---
v2-v3
- New Patch ( As per comment we are now using arch-dbg_reg only)
Signed-off-by: Bharat Bhushan bharat.bhus...@freescale.com
---
v2-v3
- New patch
arch/powerpc/include/uapi/asm/kvm.h | 1 +
arch/powerpc/kvm/booke.c| 6 ++
2 files changed, 7 insertions(+)
diff --git a/arch/powerpc/include/uapi/asm/kvm.h
b/arch/powerpc/include/uapi/asm/kvm.h
Though SPE/AltiVec shares interrupts numbers on BookE cores, use distinct
defines to identify these numbers. This improves code readability especially
in KVM.
Revert c58ce397 and 6b310fc5 patches that added common defines.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
SPE exception handlers are now defined for 32-bit e500mc cores even though
SPE unit is not present and CONFIG_SPE is undefined.
Restrict SPE exception handlers to e200/e500 cores adding CONFIG_SPE_POSSIBLE
and consequently guard __stup_ivors and __setup_cpu functions.
Signed-off-by: Mihai
Il 05/08/2014 14:27, Paolo Bonzini ha scritto:
Il 30/06/2014 12:51, Paul Mackerras ha scritto:
This series of patches provides a way to implement IRQFD support
without having to implement IRQ routing, and adds IRQFD support for
the XICS interrupt controller emulation. (XICS is the interrupt
ePAPR represents hardware threads as cpu node properties in device tree.
So with existing QEMU, hardware threads are simply exposed as vcpus with
one hardware thread.
The e6500 core shares TLBs between hardware threads. Without tlb write
conditional instruction, the Linux kernel uses per core
Commit 29577fc00ba4 (KVM: PPC: HV: Remove generic instruction emulation)
caused a build failure:
arch/powerpc/kvm/kvm-pr.o:(__tracepoints+0xa8): multiple definition of
`__tracepoint_kvm_ppc_instr'
arch/powerpc/kvm/kvm.o:(__tracepoints+0x1c0): first defined here
due to a duplicate definition of
Add KVM Book3e AltiVec support and enable e6500 core.
Changes:
v3:
- use distinct SPE/AltiVec exception handlers
- make ONE_REG AltiVec support powerpc generic
- add ONE_REG IVORs support
v2:
- integrate Paul's FP/VMX/VSX changes that landed in kvm-ppc-queue
in January and take into
Add KVM Book3e AltiVec support. KVM Book3e FPU support gracefully reuse host
infrastructure so follow the same approach for AltiVec.
Keep SPE/AltiVec exception handlers distinct using CONFIG_KVM_E500V2.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v3:
- use distinct SPE/AltiVec
Make ONE_REG AltiVec support common across server and embedded implementations
moving kvm_vcpu_ioctl_get_one_reg() and kvm_vcpu_ioctl_set_one_reg() functions
to powerpc layer.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v3:
- make ONE_REG AltiVec support powerpc generic
v2:
-
Now that AltiVec support is in place enable e6500 core.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v2-v3:
- no changes
arch/powerpc/kvm/e500mc.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/powerpc/kvm/e500mc.c b/arch/powerpc/kvm/e500mc.c
index
Add ONE_REG IVORs support, with IVORs 0-15 and 35 booke common.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v3:
- new patch
arch/powerpc/include/uapi/asm/kvm.h | 24 +++
arch/powerpc/kvm/booke.c| 132
Increase FPU laziness by calling kvmppc_load_guest_fp() just before
returning to guest instead of each sched in. Without this improvement
an interrupt may also claim floting point corrupting guest state.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
v3:
- no changes
v2:
- remove
Il 30/06/2014 12:51, Paul Mackerras ha scritto:
This series of patches provides a way to implement IRQFD support
without having to implement IRQ routing, and adds IRQFD support for
the XICS interrupt controller emulation. (XICS is the interrupt
controller defined for the pSeries machine type,
Il 05/08/2014 12:35, Paolo Bonzini ha scritto:
diff --git a/arch/powerpc/kvm/emulate.c b/arch/powerpc/kvm/emulate.c
index e96b50d0bdab..2325168ad1ff 100644
--- a/arch/powerpc/kvm/emulate.c
+++ b/arch/powerpc/kvm/emulate.c
@@ -300,3 +300,5 @@ int kvmppc_emulate_instruction(struct kvm_run *run,
On Mon, 2014-08-04 at 22:41 -0500, Bhushan Bharat-R65777 wrote:
-Original Message-
From: Wood Scott-B07421
Sent: Tuesday, August 05, 2014 4:23 AM
To: Bhushan Bharat-R65777
Cc: ag...@suse.de; kvm-ppc@vger.kernel.org; k...@vger.kernel.org; Yoder
Stuart-
B08248
Subject: Re:
Dbsr is not visible to userspace and we do not think any need to
expose this to userspace because:
Userspace cannot inject debug interrupt to guest (as this
does not know guest ability to handle debug interrupt), so
userspace will always clear DBSR.
Now if userspace has to always clear
This patch adds rfdi instruction emulation which is required for
guest debug hander on BOOKE-HV
Signed-off-by: Bharat Bhushan bharat.bhus...@freescale.com
---
arch/powerpc/include/asm/kvm_host.h | 1 +
arch/powerpc/kvm/booke_emulate.c| 13 +
2 files changed, 14 insertions(+)
Debug interrupt can be either critical level or debug level.
There are separate set of save/restore registers used for different level.
Example: DSRR0/DSRR1 are used for debug level and CSRR0/CSRR1
are used for critical level debug interrupt.
Using CPU_FTR_DEBUG_LVL_EXC to decide which interrupt
This patch emulates debug registers and debug exception
to support guest using debug resource. This enables running
gdb/kgdb etc in guest.
On BOOKE architecture we cannot share debug resources between QEMU and
guest because:
When QEMU is using debug resources then debug exception must
be
This patch changes the default behavior of MSRP_DEP, that is
guest is not allowed to change the MSR_DE, to guest can change
MSR_DE. When userspace is debugging guest then it override the
default behavior and set MSRP_DEP. This stops guest to change
MSR_DE when userspace is debugging guest.
This patch emulates debug registers and debug exception
to support guest using debug resource. This enables running
gdb/kgdb etc in guest.
On BOOKE architecture we cannot share debug resources between QEMU and
guest because:
When QEMU is using debug resources then debug exception must
be
This patchset adds debug register and interrupt emulation support
for guest, which enables running gdb/kgdb etc in guest.
Bharat Bhushan (5):
KVM: PPC: BOOKE: allow debug interrupt at debug level
KVM: PPC: BOOKE : Emulate rfdi instruction
KVM: PPC: BOOKE: Allow guest to change MSR_DE
KVM:
This patch adds rfdi instruction emulation which is required for
guest debug hander on BOOKE-HV
Signed-off-by: Bharat Bhushan bharat.bhus...@freescale.com
---
v1-v2
-msr update based on guest_debug done under _set_msr(); so removed same check
here
arch/powerpc/include/asm/kvm_host.h | 1 +
Debug interrupt can be either critical level or debug level.
There are separate set of save/restore registers used for different level.
Example: DSRR0/DSRR1 are used for debug level and CSRR0/CSRR1
are used for critical level debug interrupt.
Using CPU_FTR_DEBUG_LVL_EXC to decide which interrupt
Dbsr is not visible to userspace and we do not think any need to
expose this to userspace because:
Userspace cannot inject debug interrupt to guest (as this
does not know guest ability to handle debug interrupt), so
userspace will always clear DBSR.
Now if userspace has to always clear
On Mon, 2014-08-04 at 13:22 +0530, Bharat Bhushan wrote:
Dbsr is not visible to userspace and we do not think any need to
expose this to userspace because:
Userspace cannot inject debug interrupt to guest (as this
does not know guest ability to handle debug interrupt), so
userspace will
On Mon, 2014-08-04 at 13:32 +0530, Bharat Bhushan wrote:
@@ -735,7 +745,27 @@ static int kvmppc_handle_debug(struct kvm_run *run,
struct kvm_vcpu *vcpu)
struct debug_reg *dbg_reg = (vcpu-arch.shadow_dbg_reg);
u32 dbsr = vcpu-arch.dbsr;
- /* Clear guest dbsr
-Original Message-
From: Wood Scott-B07421
Sent: Tuesday, August 05, 2014 4:17 AM
To: Bhushan Bharat-R65777
Cc: ag...@suse.de; kvm-ppc@vger.kernel.org; k...@vger.kernel.org; Yoder
Stuart-
B08248
Subject: Re: [PATCH 4/5] KVM: PPC: BOOKE: Clear guest dbsr in userspace exit
On Mon, 2014-08-04 at 22:33 -0500, Bhushan Bharat-R65777 wrote:
-Original Message-
From: Wood Scott-B07421
Sent: Tuesday, August 05, 2014 4:17 AM
To: Bhushan Bharat-R65777
Cc: ag...@suse.de; kvm-ppc@vger.kernel.org; k...@vger.kernel.org; Yoder
Stuart-
B08248
Subject: Re:
-Original Message-
From: Wood Scott-B07421
Sent: Tuesday, August 05, 2014 4:23 AM
To: Bhushan Bharat-R65777
Cc: ag...@suse.de; kvm-ppc@vger.kernel.org; k...@vger.kernel.org; Yoder
Stuart-
B08248
Subject: Re: [PATCH 5/5 v2] KVM: PPC: BOOKE: Emulate debug registers and
exception
+/*
+ * KVMPPC_INST_BOOK3S_DEBUG is debug Instruction for supporting Software
Breakpoint.
+ * Based on PowerISA v2.07, Instruction with opcode 0s will be treated as
illegal
+ * instruction.
+ */
primary opcode 0 instead?
+#define OP_ZERO 0x0
Using 0x0 where you mean 0,
When we're using PR KVM we must not allow the CPU to take interrupts
in virtual mode, as the SLB does not contain host kernel mappings
when running inside the guest context.
To make sure we get good performance for non-KVM tasks but still
properly functioning PR KVM, let's just disable AIL
Some data structures are always stored in big endian. Among those are the LPPACA
fields as well as the shadow slb. These structures might be shared with a
hypervisor.
So whenever we access those fields, make sure we do so in big endian byte order.
Signed-off-by: Alexander Graf ag...@suse.de
---
The magic page is defined as a 4k page of per-vCPU data that is shared
between the guest and the host to accelerate accesses to privileged
registers.
However, when the host is using 64k page size granularity we weren't quite
as strict about that rule anymore. Instead, we partially treated all of
From: Anton Blanchard an...@samba.org
To establish addressability quickly, ABIv2 requires the target
address of the function being called to be in r12.
Signed-off-by: Anton Blanchard an...@samba.org
Signed-off-by: Alexander Graf ag...@suse.de
---
arch/powerpc/kvm/book3s_hv_rmhandlers.S | 4 ++--
When building KVM with a lot of vcores (NR_CPUS is big), we can potentially
get out of the ld immediate range for dereferences inside that struct.
Move the array to the end of our kvm_arch struct. This fixes compilation
issues with NR_CPUS=2048 for me.
Signed-off-by: Alexander Graf ag...@suse.de
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
When calculating the lower bits of AVA field, use the shift
count based on the base page size. Also add the missing segment
size and remove stale comment.
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
Acked-by: Paul
From: Bharat Bhushan bharat.bhus...@freescale.com
There are shadow registers like, GSPRG[0-3], GSRR0, GSRR1 etc on
BOOKE-HV and these shadow registers are guest accessible.
So these shadow registers needs to be updated on BOOKE-HV.
This patch adds new macro for get/set helper of shadow register .
We're going to implement guest code interpretation in KVM for some rare
corner cases. This code needs to be able to inject data and instruction
faults into the guest when it encounters them.
Expose generic APIs to do this in a reasonably subarch agnostic fashion.
Signed-off-by: Alexander Graf
We have a proper define for invalid HVA numbers. Use those instead of the
ppc specific kvmppc_bad_hva().
Signed-off-by: Alexander Graf ag...@suse.de
---
arch/powerpc/kvm/powerpc.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/arch/powerpc/kvm/powerpc.c
From assembly code we might not only have to explicitly BE access 64bit values,
but sometimes also 32bit ones. Add helpers that allow for easy use of lwzx/stwx
in their respective byte-reverse or native form.
Signed-off-by: Alexander Graf ag...@suse.de
CC: Benjamin Herrenschmidt
From: Paul Mackerras pau...@samba.org
This does for PR KVM what c9438092cae4 (KVM: PPC: Book3S HV: Take SRCU
read lock around kvm_read_guest() call) did for HV KVM, that is,
eliminate a suspicious rcu_dereference_check() usage! warning by
taking the SRCU lock around the call to
The 440 target hasn't been properly functioning for a few releases and
before I was the only one who fixes a very serious bug that indicates to
me that nobody used it before either.
Furthermore KVM on 440 is slow to the extent of unusable.
We don't have to carry along completely unused code.
The KVM_CHECK_EXTENSION is only available on the kvm fd today. Unfortunately
on PPC some of the capabilities change depending on the way a VM was created.
So instead we need a way to expose capabilities as VM ioctl, so that we can
see which VM type we're using (HV or PR). To enable this, add the
From: Bharat Bhushan bharat.bhus...@freescale.com
We now support SPRG9 for guest, so also add a one reg interface for same
Note: Changes are in bookehv code only as we do not have SPRG9 on booke-pr.
Signed-off-by: Bharat Bhushan bharat.bhus...@freescale.com
Signed-off-by: Alexander Graf
From: Bharat Bhushan bharat.bhus...@freescale.com
Scott Wood pointed out that We are no longer using SPRG1 for vcpu pointer,
but using SPRN_SPRG_THREAD = SPRG3 (thread-vcpu). So this comment
is not valid now.
Note: SPRN_SPRG3R is not supported (do not see any need as of now),
and if we want to
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