When we want to inject a hardware mapped IRQ into a guest, we actually
only need the virtual IRQ number from the irq_phys_map.
So let's pass this number directly from the arch timer to the VGIC
to avoid using the map as a parameter.
Signed-off-by: Andre Przywara
Reviewed-by: Eric Auger
---
incl
Hi,
another week, another rework of the new-VGIC series.
Mostly minor changes this time, some moving and streamlining of patches
(move prototypes to the same patch as the definition etc.)
The most prominent change though is the rework of the GICv2 CPU
interface access functionality. It turns out t
From: Christoffer Dall
The communication of a Linux IRQ number from outside the VGIC to the
vgic was a leftover from the day when the vgic code cared about how a
particular device injects virtual interrupts mapped to a physical
interrupt.
We can safely remove this notion, leaving all physical IR
Now that the virtual arch timer does not care about the irq_phys_map
anymore, let's rework kvm_vgic_map_phys_irq() to return an error
value instead. Any reference to that mapping can later be done by
passing the correct combination of VCPU and virtual IRQ number.
This makes the irq_phys_map handlin
We actually don't use the irq_phys_map parameter in
vgic_update_irq_pending(), so let's just remove it.
Signed-off-by: Andre Przywara
Reviewed-by: Eric Auger
---
virt/kvm/arm/vgic.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/virt/kvm/arm/vgic.c b/virt/kvm/arm/vgic.
Currently the PMU uses a member of the struct vgic_dist directly,
which not only breaks abstraction, but will fail with the new VGIC.
Abstract this access in the VGIC header file.
Signed-off-by: Andre Przywara
---
include/kvm/arm_vgic.h | 2 ++
virt/kvm/arm/pmu.c | 2 +-
2 files changed, 3 i
From: Christoffer Dall
Rename mmio_{read,write}_bus to kvm_mmio_{read,write}_bus and export
them out of mmio.c.
This will be needed later for the new VGIC implementation.
Signed-off-by: Christoffer Dall
Signed-off-by: Andre Przywara
---
arch/arm/include/asm/kvm_mmio.h | 3 +++
arch/arm/kvm
kvm_vgic_unmap_phys_irq() only needs the virtual IRQ number, so let's
just pass that between the arch timer and the VGIC to get rid of
the irq_phys_map pointer.
Signed-off-by: Andre Przywara
Reviewed-by: Eric Auger
---
include/kvm/arm_vgic.h| 2 +-
virt/kvm/arm/arch_timer.c | 2 +-
virt/k
From: Christoffer Dall
The number of list registers is a property of the underlying system, not
of emulated VGIC CPU interface.
As we are about to move this variable to global state in the new vgic
for clarity, move it from the legacy implementation as well to make the
merge of the new code easi
We implement the only one ID register that is required by the
architecture, also this is the one that Linux actually checks.
Signed-off-by: Andre Przywara
---
Changelog v1 .. v2:
- adapt to new MMIO framework
virt/kvm/arm/vgic/vgic-mmio-v3.c | 20 ++--
1 file changed, 18 inserti
The redistributor TYPER tells the OS about the associated MPIDR,
also the LAST bit is crucial to determine the number of redistributors.
Signed-off-by: Andre Przywara
---
Changelog v1 .. v2:
- adapt to new MMIO framework
virt/kvm/arm/vgic/vgic-mmio-v3.c | 44
Now that the interface between the arch timer and the VGIC does not
require passing the irq_phys_map entry pointer anymore, let's remove
it from the virtual arch timer and use the virtual IRQ number instead
directly.
The remaining pointer returned by kvm_vgic_map_phys_irq() will be
removed in the f
From: Christoffer Dall
Add a new header file for the new and improved GIC implementation.
The big change is that we now have a struct vgic_irq per IRQ instead
of spreading all the information over various bitmaps.
We include this new header conditionally from within the old header
file for the t
From: Christoffer Dall
When the kernel was handling a guest MMIO read access internally, we
need to copy the emulation result into the run->mmio structure in order
for the kvm_handle_mmio_return() function to pick it up and inject the
result back into the guest.
Currently the only user o
From: Eric Auger
This patch introduces the skeleton for the KVM device operations
associated to KVM_DEV_TYPE_ARM_VGIC_V2 and KVM_DEV_TYPE_ARM_VGIC_V3.
At that stage kvm_vgic_create is stubbed.
Signed-off-by: Eric Auger
Signed-off-by: Andre Przywara
---
Changelog v1 .. v2:
- rename vgic_kvm_de
Create vgic-mmio-v2.c to describe GICv2 emulation specific handlers
using the initializer macros provided by the VGIC MMIO framework.
Provide a function to register the GICv2 distributor registers to
the kvm_io_bus framework.
The actual handler functions are still stubs in this patch.
Signed-off-b
For getting the active state of a mapped IRQ, we actually only need
the virtual IRQ number, not the pointer to the mapping entry.
Pass the virtual IRQ number from the arch timer to the VGIC directly.
Signed-off-by: Andre Przywara
Reviewed-by: Eric Auger
---
Changelog v1 .. v2:
- rewrap phys_acti
As in the GICv2 emulation we handle those three registers in one
function.
Signed-off-by: Andre Przywara
---
Changelog RFC..v1:
- kick VCPUs if distributor gets enabled
Changelog v1 .. v2:
- rewrite write handler to use switch statement
virt/kvm/arm/vgic/vgic-mmio-v3.c | 50 +++
From: Marc Zyngier
Those three registers are v2 emulation specific, so their implementation
lives entirely in vgic-mmio-v2.c. Also they are handled in one function,
as their implementation is pretty simple.
When the guest enables the distributor, we kick all VCPUs to get
potentially pending inter
The pending register handlers are shared between the v2 and v3
emulation, so their implementation goes into vgic-mmio.c, to be easily
referenced from the v3 emulation as well later.
For level triggered interrupts the real line level is unaffected by
this write, so we keep this state separate and co
The target register handlers are v2 emulation specific, so their
implementation lives entirely in vgic-mmio-v2.c.
We copy the old VGIC behaviour of assigning an IRQ to the first VCPU
set in the target mask instead of making it possibly pending on
multiple VCPUs.
Signed-off-by: Andre Przywara
---
From: Marc Zyngier
Add an MMIO handling framework to the VGIC emulation:
Each register is described by its offset, size (or number of bits per
IRQ, if applicable) and the read/write handler functions. We provide
initialization macros to describe each GIC register later easily.
Separate dispatch
In contrast to GICv2 SGIs in a GICv3 implementation are not triggered
by a MMIO write, but with a system register write. KVM knows about
that register already, we just need to implement the handler and wire
it up to the core KVM/ARM code.
Signed-off-by: Andre Przywara
---
Changelog RFC..v1:
- add
From: Marc Zyngier
As the GICv3 virtual interface registers differ from their GICv2
siblings, we need different handlers for processing maintenance
interrupts and reading/writing to the LRs.
Implement the respective handler functions and connect them to
existing code to be called if the host is u
From: Christoffer Dall
Adds the sorting function to cover the case where you have more IRQs
to consider than you have LRs. We now consider priorities.
Signed-off-by: Christoffer Dall
Signed-off-by: Andre Przywara
---
virt/kvm/arm/vgic/vgic.c | 57 ++
From: Eric Auger
This patch implements the vgic_creation function which is
called on CREATE_IRQCHIP VM IOCTL (v2 only) or KVM_CREATE_DEVICE
Signed-off-by: Eric Auger
Signed-off-by: Andre Przywara
---
include/kvm/vgic/vgic.h | 1 +
virt/kvm/arm/vgic/vgic-init.c | 84
From: Eric Auger
This patch implements the KVM_DEV_ARM_VGIC_GRP_NR_IRQS group. This
modality is supported by both VGIC V2 and V3 KVM device as will be
other groups, hence the introduction of common helpers.
Signed-off-by: Eric Auger
Signed-off-by: Andre Przywara
---
virt/kvm/arm/vgic/vgic-kvm
From: Marc Zyngier
Processing maintenance interrupts and accessing the list registers
are dependent on the host's GIC version.
Introduce vgic-v2.c to contain GICv2 specific functions.
Implement the GICv2 specific code for syncing the emulation state
into the VGIC registers.
Signed-off-by: Marc Z
As this register is v2 specific, its implementation lives entirely
in vgic-mmio-v2.c.
This register allows setting the source mask of an IPI.
Signed-off-by: Andre Przywara
---
Changelog RFC..v1:
- remove IRQ lock from read handler
- update pending bit on setting the first / clearing the last bit
From: Eric Auger
Tell KVM whether a particular VCPU has an IRQ that needs handling
in the guest. This is used to decide whether a VCPU is runnable.
Signed-off-by: Eric Auger
Signed-off-by: Andre Przywara
---
Changelog RFC..v1:
- return false if distributor is disabled
- add vgic_kick_vcpus() i
The config register handlers are shared between the v2 and v3
emulation, so their implementation goes into vgic-mmio.c, to be
easily referenced from the v3 emulation as well later.
Signed-off-by: Andre Przywara
---
Changelog v1 .. v2:
- adapt to new MMIO framework
virt/kvm/arm/vgic/vgic-mmio-v2
Using the VMCR accessors we provide access to GIC CPU interface state
to userland by wiring it up to the existing userland interface.
[Marc: move and make VMCR accessors static, streamline MMIO handlers]
Signed-off-by: Andre Przywara
Signed-off-by: Marc Zyngier
---
Changelog v2 .. v3:
- total re
The priority register handlers are shared between the v2 and v3
emulation, so their implementation goes into vgic-mmio.c, to be
easily referenced from the v3 emulation as well later.
There is a corner case when we change the priority of a pending
interrupt which we don't handle at the moment.
Sign
Since GICv3 supports much more than the 8 CPUs the GICv2 ITARGETSR
register can handle, the new IROUTER register covers the whole range
of possible target (V)CPUs by using the same MPIDR that the cores
report themselves.
In addition to translating this MPIDR into a vcpu pointer we store
the origina
From: Marc Zyngier
Implement the framework for syncing IRQs between our emulation and
the list registers, which represent the guest's view of IRQs.
This is done in kvm_vgic_flush_hwstate and kvm_vgic_sync_hwstate,
which gets called on guest entry and exit.
The code talking to the actual GICv2/v3
The active register handlers are shared between the v2 and v3
emulation, so their implementation goes into vgic-mmio.c, to be
easily referenced from the v3 emulation as well later.
Since activation/deactivation of an interrupt may happen entirely
in the guest without it ever exiting, we need some e
From: Christoffer Dall
The new VGIC implementation centers around a struct vgic_irq instance
per virtual IRQ.
Provide a function to retrieve the right instance for a given IRQ
number and (in case of private interrupts) the right VCPU.
Signed-off-by: Christoffer Dall
Signed-off-by: Andre Przywar
Create a new file called vgic-mmio-v3.c and describe the GICv3
distributor and redistributor registers there.
This adds a special macro to deal with the split of SGI/PPI in the
redistributor and SPIs in the distributor, which allows us to reuse
the existing GICv2 handlers for those registers which
As the enable register handlers are shared between the v2 and v3
emulation, their implementation goes into vgic-mmio.c, to be easily
referenced from the v3 emulation as well later.
Signed-off-by: Andre Przywara
---
Changelog RFC..v1:
- use lower bits of address to determine IRQ number
- remove TO
From: Eric Auger
map_resources is the last initialization step. It is executed on
1st VCPU run. At that stage the code checks the userspace has provided
the base addresses for the relevant VGIC regions, which depend on
the type of VGIC that is exposed to the guest.
The function also forces the v
From: Eric Auger
This patch implements the KVM_DEV_ARM_VGIC_GRP_CTRL group API
featuring KVM_DEV_ARM_VGIC_CTRL_INIT attribute. The vgic_init
function is not yet implemented though.
Signed-off-by: Eric Auger
Signed-off-by: Andre Przywara
---
virt/kvm/arm/vgic/vgic-kvm-device.c | 22 +++
From: Eric Auger
Implements kvm_vgic_hyp_init and vgic_probe function.
The vgic_global struct is enriched with new fields populated
by those functions.
Signed-off-by: Eric Auger
Signed-off-by: Andre Przywara
---
Changelog v1 .. v2:
- rename vgic_init.c to vgic-init.c
Changelog v2 .. v3:
- in
From: Eric Auger
This patch allocates and initializes the data structures used
to model the vgic distributor and virtual cpu interfaces. At that
stage the number of IRQs and number of virtual CPUs is frozen.
The following early_init functions are kept since they are called from
arm.c. However th
From: Christoffer Dall
Provide a vgic_queue_irq() function which decides whether a given
IRQ needs to be queued to a VCPU's ap_list.
This should be called whenever an IRQ becomes pending or enabled,
either as a result of userspace injection, from in-kernel emulated
devices like the architected ti
As (some) GICv3 hosts can emulate a GICv2, some GICv2 specific masks
for the list register definition also apply to GICv3 LRs.
At the moment we have those definitions in the KVM VGICv3
implementation, so let's move them into the GICv3 header file to
have them automatically defined.
Signed-off-by:
Now that the new VGIC implementation has reached feature parity with
the old one, add the new files to the build system and add a Kconfig
option to switch between the two versions.
We set the default to the new version to get maximum test coverage,
in case people experience problems they can switch
Triggering an IPI via this register is v2 specific, so the
implementation lives entirely in vgic-mmio-v2.c.
Signed-off-by: Andre Przywara
---
Changelog RFC..v1:
- silently return on illegal TargetListFilter value (=3)
Changelog v1 .. v2:
- adapt to new MMIO framework
virt/kvm/arm/vgic/vgic-mmi
From: Eric Auger
kvm_vgic_addr is used by the userspace to set the base address of
the following register regions, as seen by the guest:
- distributor(v2 and v3),
- re-distributors (v3),
- CPU interface (v2).
Signed-off-by: Eric Auger
Signed-off-by: Andre Przywara
---
include/kvm/vgic/vgic.h
Since the GIC CPU interface is always virtualized by the hardware,
we don't have CPU interface state information readily available in our
emulation if userland wants to save or restore it.
Fortunately the GIC hypervisor interface provides the VMCR register to
access the required virtual CPU interfa
From: Eric Auger
This patch implements the KVM_DEV_ARM_VGIC_GRP_ADDR group which
enables to set the base address of GIC regions as seen by the guest.
Signed-off-by: Eric Auger
Signed-off-by: Andre Przywara
---
virt/kvm/arm/vgic/vgic-kvm-device.c | 38 +
1 f
From: Christoffer Dall
Userland can access the emulated GIC to save and restore its state
for initialization or migration purposes.
The kvm_io_bus API requires an absolute gpa, which does not fit the
KVM_DEV_ARM_VGIC_GRP_DIST_REGS user API, that only provides relative
offsets. So we provide a wra
Userland may want to save and restore the state of the in-kernel VGIC,
so we provide the code which takes a userland request and translate
that into calls to our MMIO framework.
Signed-off-by: Andre Przywara
---
virt/kvm/arm/vgic/vgic-kvm-device.c | 50 -
1 fi
From: Eric Auger
This patch implements the switches for KVM_DEV_ARM_VGIC_GRP_DIST_REGS
and KVM_DEV_ARM_VGIC_GRP_CPU_REGS API which allows the userspace to
access VGIC registers.
Signed-off-by: Eric Auger
Signed-off-by: Andre Przywara
---
virt/kvm/arm/vgic/vgic-kvm-device.c | 53 ++
Connect to the new VGIC to the irqfd framework, so that we can
inject IRQs.
GSI routing and MSI routing is not yet implemented.
Signed-off-by: Andre Przywara
---
virt/kvm/arm/vgic/vgic-irqfd.c | 52 ++
1 file changed, 52 insertions(+)
create mode 100644 v
We now store the mapped hardware IRQ number in our struct, so we
don't need the irq_phys_map for the new VGIC.
Implement the hardware IRQ mapping on top of the reworked arch
timer interface.
Signed-off-by: Andre Przywara
---
Changelog RFC..v1:
- adapt to new arch_timer mapped IRQ interface
- impl
From: Eric Auger
Enable the VGIC operation by properly initialising the registers
in the hypervisor GIC interface.
Signed-off-by: Eric Auger
Signed-off-by: Andre Przywara
---
virt/kvm/arm/vgic/vgic-v2.c | 11 ++-
virt/kvm/arm/vgic/vgic-v3.c | 23 ++-
2 files change
On 05/06/2016 04:45 AM, Andre Przywara wrote:
From: Marc Zyngier
As the GICv3 virtual interface registers differ from their GICv2
siblings, we need different handlers for processing maintenance
interrupts and reading/writing to the LRs.
Implement the respective handler functions and connect the
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