Hi james,
thanks for the mail, and sorry for my late response.
On 2017/10/7 0:46, James Morse wrote:
>>> will give you an BUS_MCEERR_AO signal for any guest memory that is
>>> affected, and a BUS_MCEERR_AR if the guest directly accesses a page of
>>> affected memory.
>>>
>>> What Qemu/kvmtoo
Hi James,
Thanks for your mail. and very sorry for my late response.
>
> Hi gengdongjiu,
>
> On 15/10/17 17:09, gengdongjiu wrote:
> >> On 13/10/17 10:25, gengdongjiu wrote:
> >>> In my first version patch [2], It sets the virtual ESR in the KVM,
> >>> but Marc and other people disagree that[
On Wed, Oct 18, 2017 at 04:00:05PM +0100, Dave Martin wrote:
> On Wed, Oct 18, 2017 at 03:23:23PM +0200, Christoffer Dall wrote:
> > On Tue, Oct 17, 2017 at 03:31:42PM +0100, Dave Martin wrote:
> > > On Tue, Oct 17, 2017 at 01:50:24PM +0200, Christoffer Dall wrote:
> > > > On Tue, Oct 10, 2017 at 0
On Wed, Oct 18, 2017 at 03:45:10PM +0100, Dave Martin wrote:
> On Wed, Oct 18, 2017 at 03:20:26PM +0200, Christoffer Dall wrote:
> > On Tue, Oct 17, 2017 at 03:08:40PM +0100, Marc Zyngier wrote:
> > > On 17/10/17 14:51, Christoffer Dall wrote:
> > > > On Tue, Oct 10, 2017 at 07:38:19PM +0100, Dave
On Wed, Oct 18, 2017 at 05:03:40PM +0100, Marc Zyngier wrote:
> On Wed, Oct 18 2017 at 3:41:45 pm BST, Christoffer Dall
> wrote:
> > On Mon, Oct 09, 2017 at 05:47:18PM +0100, Marc Zyngier wrote:
> >> On 23/09/17 01:41, Christoffer Dall wrote:
> >> > Some systems without proper firmware and/or ha
Hi Dongjiu Geng,
On 17/10/17 15:14, Dongjiu Geng wrote:
> ARMv8.2 adds a new bit HCR_EL2.TEA which controls to
> route synchronous external aborts to EL2, and adds a
> trap control bit HCR_EL2.TERR which controls to
> trap all Non-secure EL1&0 error record accesses to EL2.
The bulk of this patch
On Tue, Oct 17, 2017 at 06:44:30PM +0100, James Morse wrote:
> Private SDE events are per-cpu, and need to be registered and enabled
> on each CPU.
>
> Hide this detail from the caller by adapting our {,un}register and
> {en,dis}able calls to send an IPI to each CPU if the event is private.
>
> C
On Tue, Oct 17, 2017 at 06:44:29PM +0100, James Morse wrote:
> When a CPU enters an idle lower-power state or is powering off, we
> need to mask SDE events so that no events can be delivered while we
> are messing with the MMU as the registered entry points won't be valid.
>
> If the system reboot
Hi Catalin,
On 18/10/17 17:43, Catalin Marinas wrote:
> On Thu, Oct 05, 2017 at 08:18:05PM +0100, James Morse wrote:
>> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
>> index b68f5e93baac..29df2a93688c 100644
>> --- a/arch/arm64/Kconfig
>> +++ b/arch/arm64/Kconfig
>> @@ -989,6 +989,21 @@ co
Hi James,
On Tue, Oct 17, 2017 at 06:44:19PM +0100, James Morse wrote:
> The Software Delegated Exception Interface (SDEI) is an ARM specification
> for registering callbacks from the platform firmware into the OS.
> This is intended to be used to implement firmware-first RAS notifications,
> but
On Thu, Oct 05, 2017 at 08:17:52PM +0100, James Morse wrote:
> James Morse (18):
> arm64: explicitly mask all exceptions
> arm64: introduce an order for exceptions
> arm64: Move the async/fiq helpers to explicitly set process context
> flags
> arm64: Mask all exceptions during kernel_ex
On Wed, Oct 18 2017 at 6:47:50 pm BST, Christoffer Dall
wrote:
> On Mon, Oct 09, 2017 at 06:05:04PM +0100, Marc Zyngier wrote:
>> On 23/09/17 01:41, Christoffer Dall wrote:
>> > We are about to add an additional soft timer to the arch timer state for
>> > a VCPU and would like to be able to reus
On Wed, Oct 18, 2017 at 5:01 PM, Dave Martin wrote:
> On Wed, Oct 18, 2017 at 03:21:45PM +0200, Christoffer Dall wrote:
>> On Tue, Oct 17, 2017 at 04:47:08PM +0100, Dave Martin wrote:
>> > On Tue, Oct 17, 2017 at 03:29:36PM +0100, Marc Zyngier wrote:
>> > > On 17/10/17 15:07, Dave Martin wrote:
>>
On Mon, Oct 09, 2017 at 06:05:04PM +0100, Marc Zyngier wrote:
> On 23/09/17 01:41, Christoffer Dall wrote:
> > We are about to add an additional soft timer to the arch timer state for
> > a VCPU and would like to be able to reuse the functions to program and
> > cancel a timer, so we make them slig
On Thu, Oct 05, 2017 at 08:18:05PM +0100, James Morse wrote:
> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
> index b68f5e93baac..29df2a93688c 100644
> --- a/arch/arm64/Kconfig
> +++ b/arch/arm64/Kconfig
> @@ -989,6 +989,21 @@ config ARM64_RAS_EXTN
> and access the new registers if
On Wed, Oct 18 2017 at 3:41:45 pm BST, Christoffer Dall
wrote:
> On Mon, Oct 09, 2017 at 05:47:18PM +0100, Marc Zyngier wrote:
>> On 23/09/17 01:41, Christoffer Dall wrote:
>> > Some systems without proper firmware and/or hardware description data
>> > don't support the split EOI and deactivate
On Wed, Oct 18, 2017 at 11:32:55AM +0100, Catalin Marinas wrote:
> On Fri, Oct 13, 2017 at 05:16:39PM +0100, Dave P Martin wrote:
> > On Thu, Oct 12, 2017 at 06:06:32PM +0100, Catalin Marinas wrote:
> > > On Tue, Oct 10, 2017 at 07:38:36PM +0100, Dave P Martin wrote:
> > > > @@ -702,6 +737,211 @@ s
On Wed, Oct 18 2017 at 1:34:05 pm BST, Christoffer Dall
wrote:
> On Mon, Oct 09, 2017 at 05:21:24PM +0100, Marc Zyngier wrote:
>> On 23/09/17 01:41, Christoffer Dall wrote:
>> > Currently get_cycles() is hardwired to arch_counter_get_cntvct() on
>> > arm64, but as we move to using the physical t
Hi Vladimir,
On 11/10/17 13:19, Vladimir Murzin wrote:
> Common Not Private (CNP) is a feature of ARMv8.2 extension which
> allows translation table entries to be shared between different PEs in
> the same inner shareable domain, so the hardware can use this fact to
> optimise the caching of such
On Wed, Oct 18, 2017 at 03:21:45PM +0200, Christoffer Dall wrote:
> On Tue, Oct 17, 2017 at 04:47:08PM +0100, Dave Martin wrote:
> > On Tue, Oct 17, 2017 at 03:29:36PM +0100, Marc Zyngier wrote:
> > > On 17/10/17 15:07, Dave Martin wrote:
> > > > On Tue, Oct 17, 2017 at 06:58:16AM -0700, Christoffe
On Wed, Oct 18, 2017 at 03:23:23PM +0200, Christoffer Dall wrote:
> On Tue, Oct 17, 2017 at 03:31:42PM +0100, Dave Martin wrote:
> > On Tue, Oct 17, 2017 at 01:50:24PM +0200, Christoffer Dall wrote:
> > > On Tue, Oct 10, 2017 at 07:38:39PM +0100, Dave Martin wrote:
> > > > Until KVM has full SVE su
On Wed, Oct 18, 2017 at 03:20:26PM +0200, Christoffer Dall wrote:
> On Tue, Oct 17, 2017 at 03:08:40PM +0100, Marc Zyngier wrote:
> > On 17/10/17 14:51, Christoffer Dall wrote:
> > > On Tue, Oct 10, 2017 at 07:38:19PM +0100, Dave Martin wrote:
[...]
> > >> +/* sys_reg_desc initialiser for known c
Hi Christoffer,
On 18/10/2017 00:10, Christoffer Dall wrote:
> On Tue, Oct 17, 2017 at 09:10:04AM +0200, Eric Auger wrote:
>> At the moment vgic_its_process_commands() does not
>> check the CBASER is valid before processing any command.
>> Let's fix that.
>>
>> Also rename cbaser local variable in
On Wed, Oct 18, 2017 at 03:23:16PM +0100, Catalin Marinas wrote:
> On Thu, Oct 05, 2017 at 08:17:53PM +0100, James Morse wrote:
> > diff --git a/arch/arm64/include/asm/daifflags.h
> > b/arch/arm64/include/asm/daifflags.h
> > new file mode 100644
> > index ..fb40da8e1457
> > --- /dev/nu
On Thu, Oct 05, 2017 at 08:17:53PM +0100, James Morse wrote:
> diff --git a/arch/arm64/include/asm/daifflags.h
> b/arch/arm64/include/asm/daifflags.h
> new file mode 100644
> index ..fb40da8e1457
> --- /dev/null
> +++ b/arch/arm64/include/asm/daifflags.h
> @@ -0,0 +1,59 @@
> +/*
> + *
On Wed, Oct 18, 2017 at 3:55 PM, Andrew Jones wrote:
> On Wed, Oct 18, 2017 at 03:18:43PM +0200, Christoffer Dall wrote:
>> On Wed, Oct 18, 2017 at 02:13:05PM +0200, Andrew Jones wrote:
>> > On Sat, Oct 14, 2017 at 09:13:35PM +0200, Christoffer Dall wrote:
>> > > On Fri, Sep 29, 2017 at 01:30:41PM
On Wed, Oct 18, 2017 at 03:18:43PM +0200, Christoffer Dall wrote:
> On Wed, Oct 18, 2017 at 02:13:05PM +0200, Andrew Jones wrote:
> > On Sat, Oct 14, 2017 at 09:13:35PM +0200, Christoffer Dall wrote:
> > > On Fri, Sep 29, 2017 at 01:30:41PM +0200, Andrew Jones wrote:
> > > > When the vPMU is in use
On Mon, Oct 09, 2017 at 05:47:18PM +0100, Marc Zyngier wrote:
> On 23/09/17 01:41, Christoffer Dall wrote:
> > Some systems without proper firmware and/or hardware description data
> > don't support the split EOI and deactivate operation.
> >
> > On such systems, we cannot leave the physical inter
On Tue, Oct 17, 2017 at 03:31:42PM +0100, Dave Martin wrote:
> On Tue, Oct 17, 2017 at 01:50:24PM +0200, Christoffer Dall wrote:
> > On Tue, Oct 10, 2017 at 07:38:39PM +0100, Dave Martin wrote:
> > > Until KVM has full SVE support, guests must not be allowed to
> > > execute SVE instructions.
> > >
On Tue, Oct 17, 2017 at 04:47:08PM +0100, Dave Martin wrote:
> On Tue, Oct 17, 2017 at 03:29:36PM +0100, Marc Zyngier wrote:
> > On 17/10/17 15:07, Dave Martin wrote:
> > > On Tue, Oct 17, 2017 at 06:58:16AM -0700, Christoffer Dall wrote:
> > >> On Tue, Oct 10, 2017 at 07:38:41PM +0100, Dave Martin
On Tue, Oct 17, 2017 at 03:08:40PM +0100, Marc Zyngier wrote:
> On 17/10/17 14:51, Christoffer Dall wrote:
> > On Tue, Oct 10, 2017 at 07:38:19PM +0100, Dave Martin wrote:
> >> Currently, a guest kernel sees the true CPU feature registers
> >> (ID_*_EL1) when it reads them using MRS instructions.
On Wed, Oct 18, 2017 at 02:13:05PM +0200, Andrew Jones wrote:
> On Sat, Oct 14, 2017 at 09:13:35PM +0200, Christoffer Dall wrote:
> > On Fri, Sep 29, 2017 at 01:30:41PM +0200, Andrew Jones wrote:
> > > When the vPMU is in use if a VCPU's perf event overflow handler
> > > were to fire after the VCPU
On Sat, Oct 14, 2017 at 09:13:35PM +0200, Christoffer Dall wrote:
> On Fri, Sep 29, 2017 at 01:30:41PM +0200, Andrew Jones wrote:
> > When the vPMU is in use if a VCPU's perf event overflow handler
> > were to fire after the VCPU started waiting, then the wake up
> > done by the kvm_vcpu_kick() cal
On Sat, Oct 14, 2017 at 09:13:25PM +0200, Christoffer Dall wrote:
> On Fri, Sep 29, 2017 at 01:30:40PM +0200, Andrew Jones wrote:
> > Conceptually, kvm_arch_vcpu_runnable() should be "not waiting,
> > or waiting for interrupts and interrupts are pending",
> >
> > !waiting-uninterruptable &&
> >
On Sat, Oct 14, 2017 at 09:13:08PM +0200, Christoffer Dall wrote:
> On Fri, Sep 29, 2017 at 01:30:39PM +0200, Andrew Jones wrote:
> > Before we add more common code to the wfi emulation, let's first
> > factor out everything common.
> >
> > Signed-off-by: Andrew Jones
> > ---
> > arch/arm/includ
On Sat, Oct 14, 2017 at 09:12:54PM +0200, Christoffer Dall wrote:
> On Fri, Sep 29, 2017 at 01:30:38PM +0200, Andrew Jones wrote:
> > This prepares for more MP states to be used.
> >
> > Signed-off-by: Andrew Jones
> > ---
> > arch/arm/include/asm/kvm_host.h | 6 --
> > arch/arm64/include
On Mon, Oct 09, 2017 at 05:37:43PM +0100, Marc Zyngier wrote:
> On 23/09/17 01:41, Christoffer Dall wrote:
> > We are about to optimize our timer handling logic which involves
> > injecting irqs to the vgic directly from the irq handler.
> >
> > Unfortunately, the injection path can take any AP li
On Wed, Oct 18, 2017 at 11:19:30AM +0100, Marc Zyngier wrote:
> On 17/10/17 15:23, Dongjiu Geng wrote:
> > When a exception is trapped to EL2, hardware uses ELR_ELx to hold
> > the current fault instruction address. If KVM wants to inject a
> > abort to 32 bit guest, it needs to set the LR registe
On Mon, Oct 09, 2017 at 05:21:24PM +0100, Marc Zyngier wrote:
> On 23/09/17 01:41, Christoffer Dall wrote:
> > Currently get_cycles() is hardwired to arch_counter_get_cntvct() on
> > arm64, but as we move to using the physical timer for the in-kernel
> > time-keeping, we need to make that more flex
On Tue, Oct 17, 2017 at 06:44:28PM +0100, James Morse wrote:
> The Software Delegated Exception Interface (SDEI) is an ARM standard
> for registering callbacks from the platform firmware into the OS.
> This is typically used to implement RAS notifications.
>
> Such notifications enter the kernel a
On Tue, Oct 17, 2017 at 06:44:32PM +0100, James Morse wrote:
> SDEI defines a new ACPI table to indicate the presence of the interface.
> The conduit is discovered in the same way as PSCI.
>
> For ACPI we need to create the platform device ourselves as SDEI doesn't
> have an entry in the DSDT.
>
On Tue, Oct 17, 2017 at 06:44:31PM +0100, James Morse wrote:
> SDEI inherits the 'use hvc' bit that is also used by PSCI. PSCI does all
> its initialisation early, SDEI does its late.
>
> Remove the __init annotation from acpi_psci_use_hvc().
>
> Signed-off-by: James Morse
Acked-by: Catalin Mar
On Tue, Oct 17, 2017 at 06:44:30PM +0100, James Morse wrote:
> Private SDE events are per-cpu, and need to be registered and enabled
> on each CPU.
>
> Hide this detail from the caller by adapting our {,un}register and
> {en,dis}able calls to send an IPI to each CPU if the event is private.
>
> C
On Tue, Oct 17, 2017 at 06:44:29PM +0100, James Morse wrote:
> When a CPU enters an idle lower-power state or is powering off, we
> need to mask SDE events so that no events can be delivered while we
> are messing with the MMU as the registered entry points won't be valid.
>
> If the system reboot
On Tue, Oct 17, 2017 at 06:44:27PM +0100, James Morse wrote:
> Today the arm64 arch code allocates an extra IRQ stack per-cpu. If we
> also have SDEI and VMAP stacks we need two extra per-cpu VMAP stacks.
>
> Move the VMAP stack allocation out to a helper in a new header file.
> This avoids missin
On Tue, Oct 17, 2017 at 06:44:26PM +0100, James Morse wrote:
> The Software Delegated Exception Interface (SDEI) is an ARM standard
> for registering callbacks from the platform firmware into the OS.
> This is typically used to implement firmware notifications (such as
> firmware-first RAS) or prom
On Tue, Oct 17, 2017 at 06:44:23PM +0100, James Morse wrote:
> Now that KVM uses tpidr_el2 in the same way as Linux's cpu_offset in
> tpidr_el1, merge the two. This saves KVM from save/restoring tpidr_el1
> on VHE hosts, and allows future code to blindly access per-cpu variables
> without triggerin
On Tue, Oct 17, 2017 at 05:34:13PM +0100, James Morse wrote:
> On 16/10/17 14:41, Catalin Marinas wrote:
> > On Fri, Sep 22, 2017 at 07:26:10PM +0100, James Morse wrote:
> >> + u64 elr = read_sysreg(elr_el1);
> >> + u32 kernel_mode = read_sysreg(CurrentEL) | 1; /* +SPSel */
> >> + unsigned lon
On Fri, Oct 13, 2017 at 05:16:39PM +0100, Dave P Martin wrote:
> On Thu, Oct 12, 2017 at 06:06:32PM +0100, Catalin Marinas wrote:
> > On Tue, Oct 10, 2017 at 07:38:36PM +0100, Dave P Martin wrote:
> > > @@ -702,6 +737,211 @@ static int system_call_set(struct task_struct
> > > *target,
> > > retu
On 17/10/17 15:23, Dongjiu Geng wrote:
> When a exception is trapped to EL2, hardware uses ELR_ELx to hold
> the current fault instruction address. If KVM wants to inject a
> abort to 32 bit guest, it needs to set the LR register for the
> guest to emulate this abort happened in the guest. Because
On Tue, Oct 17, 2017 at 10:23:49PM +0800, Dongjiu Geng wrote:
> When a exception is trapped to EL2, hardware uses ELR_ELx to hold
> the current fault instruction address. If KVM wants to inject a
> abort to 32 bit guest, it needs to set the LR register for the
> guest to emulate this abort happene
On Tue, Oct 17, 2017 at 04:33:05PM +0100, Will Deacon wrote:
> Hi Christoffer,
>
> On Sat, Sep 23, 2017 at 02:41:49AM +0200, Christoffer Dall wrote:
> > Using the physical counter allows KVM to retain the offset between the
> > virtual and physical counter as long as it is actively running a VCPU.
On Fri, Oct 13, 2017 at 06:17:59PM +0100, Dave P Martin wrote:
> On Fri, Oct 13, 2017 at 03:24:21PM +0100, Catalin Marinas wrote:
> > On Tue, Oct 10, 2017 at 07:38:43PM +0100, Dave P Martin wrote:
> > > +* If the SVE context is too big to fit in sigcontext.__reserved[], then
> > > extra
> > > + s
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