Hi Marc,
Thank you for keeping me in the loop, just minor comments below.
On 2018/2/1 19:46, Marc Zyngier wrote:
> Now that we've standardised on SMCCC v1.1 to perform the branch
> prediction invalidation, let's drop the previous band-aid.
> If vendors haven't updated their firmware to do SMCCC
On 2018/2/1 16:53, Marc Zyngier wrote:
[...]
... and actually, perhaps it makes sense for the
SMCCC_ARCH_WORKAROUND_1 check to be completely independent of MIDR
based errata matching?
I.e., if SMCCC v1.1 and SMCCC_ARCH_WORKAROUND_1 are both implemented,
we should
On 2018/2/1 10:40, Hanjun Guo wrote:
> On 2018/1/31 23:05, Marc Zyngier wrote:
>> On 31/01/18 14:38, Ard Biesheuvel wrote:
>>> On 31 January 2018 at 14:35, Ard Biesheuvel <ard.biesheu...@linaro.org>
>>> wrote:
>>>> On 31 January 2018 at 14:
On 2018/1/31 23:05, Marc Zyngier wrote:
> On 31/01/18 14:38, Ard Biesheuvel wrote:
>> On 31 January 2018 at 14:35, Ard Biesheuvel <ard.biesheu...@linaro.org>
>> wrote:
>>> On 31 January 2018 at 14:11, Marc Zyngier <marc.zyng...@arm.com> wrote:
>>>&g
Hi Marc,
On 2018/1/30 1:45, Marc Zyngier wrote:
> static int enable_psci_bp_hardening(void *data)
> {
> const struct arm64_cpu_capabilities *entry = data;
>
> - if (psci_ops.get_version)
> + if (psci_ops.get_version) {
> + if (check_smccc_arch_workaround_1(entry))
>
On 2017/3/2 21:45, Shiju Jose wrote:
Hi James,
Hi Hanjun,
On 01/03/17 08:27, Hanjun Guo wrote:
On 2017/2/28 21:22, James Morse wrote:
On 27/02/17 18:19, Shiju Jose wrote:
Add a new GHES error source handling function for GSIV(Global
System
Interrupt Vector).
If an error source's
Hi James,
On 2017/2/28 21:22, James Morse wrote:
Hi Shiju,
On 27/02/17 18:19, Shiju Jose wrote:
Add a new GHES error source handling function for
GSIV(Global System Interrupt Vector).
If an error source's notification type is GSIV,
then this handling function can be registered
into the GSIV
Hi Harb,
On 2016/10/20 0:59, Abdulhamid, Harb wrote:
> On 10/18/2016 8:44 AM, Hanjun Guo wrote:
>> Hi Tyler,
>>
>> On 2016/10/8 5:31, Tyler Baicar wrote:
>>> ARM APEI extension proposal added SEA (Synchrounous External
>>> Abort) notification type for
On 2016/10/8 5:31, Tyler Baicar wrote:
ARM APEI extension proposal added SEA (Synchrounous External
Abort) notification type for ARMv8.
Add a new GHES error source handling function for SEA. If an error
source's notification type is SEA, then this function can be registered
into the SEA
Hi Tyler,
On 2016/10/8 5:31, Tyler Baicar wrote:
ARM APEI extension proposal added SEA (Synchrounous External
Abort) notification type for ARMv8.
Add a new GHES error source handling function for SEA. If an error
source's notification type is SEA, then this function can be registered
into the
Hi Shanker, Julien,
On 2016/4/11 23:25, Shanker Donthineni wrote:
Hi Julien,
On 04/11/2016 09:27 AM, Julien Grall wrote:
Hello Hanjun,
On 11/04/16 06:27, Hanjun Guo wrote:
On 2016/4/4 19:37, Julien Grall wrote:
+static void __init gic_acpi_setup_kvm_info(void)
+{
+int irq
On 2016/4/11 23:32, Julien Grall wrote:
Currently, most of the pr_* messages in the GICv3 driver don't have a
prefix. Add one to make clear where the messages come from.
Signed-off-by: Julien Grall
---
Changes in v6:
- Patch added
---
and set of helpers to get/set the virtual GIC
information. Also fill up the structure for GICv2.
Signed-off-by: Julien Grall <julien.gr...@arm.com>
For ACPI code,
Acked-by: Hanjun Guo <hanjun@linaro.org>
Thanks
Hanjun
___
kvmarm mailing
On 2016/4/4 19:37, Julien Grall wrote:
Fill up the recently introduced gic_kvm_info with the hardware
information used for virtualization.
Signed-off-by: Julien Grall
Cc: Thomas Gleixner
Cc: Jason Cooper
Cc: Marc Zyngier
acpi_data.redist_regs[i].redist_base);
+ kfree(acpi_data.redist_regs);
out_dist_unmap:
- iounmap(dist_base);
+ iounmap(acpi_data.dist_base);
return err;
}
IRQCHIP_ACPI_DECLARE(gic_v3, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
I'm fine with it,
Reviewed-by: Hanju
the
information in a single structure.
Signed-off-by: Julien Grall <julien.gr...@arm.com>
Acked-by: Christofer Dall <christoffer.d...@linaro.org>
Acked-by: Hanjun Guo <hanjun@linaro.org>
Please cc me if you have further versions, I would
like to review the ARM64 ACPI related co
on top of recent GIC/IRQCHIP patches by
Hanjun Guo, who added support for gic_version in ACPI struct of GIC
distributor (search ACPICA: Introduce GIC version for arm based system).
This patchset can be applied cleanly on top of kvmarm.git queue branch.
-Wei
V1-V2:
* Initialize vgic-max_gic_vcpus
On 06/10/2015 12:16 PM, Wei Huang wrote:
This patch creates a dispatch function to support virt GIC probing
in both device tree (DT) and ACPI environment. kvm_vgic_hyp_init()
will probe DT first. If failed, it will try ACPI.
Signed-off-by: Wei Huang w...@redhat.com
---
include/kvm/arm_vgic.h
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