On 01/24/2017 12:36 PM, Pengfei Qu wrote:
MFX pipeline:
add MFX command for AVC encoder
add MFX Picture slice level command init for AVC
add MFX pipeline init prepare run for AVC encode
add VME/MFX context init for AVC encoder
Reviewed-by: Sean V Kelley
Signed-off-by: Pengfei Qu
---
src/gen9_a
On 01/24/2017 12:36 PM, Pengfei Qu wrote:
VME pipeline:
add resource and surface allocation and free function
add init table for frame mbbrc update
add scaling kernel for AVC encoder
add BRC init reset kernel for AVC RC logic
add BRC frame update-kernel for AVC RC logic
add BRC MB level update ke
On 01/24/2017 12:36 PM, Pengfei Qu wrote:
v1:move kernal array into the header file
v2:add file into Makefile.am
Reviewed-by: Sean V Kelley
Signed-off-by: Pengfei Qu
It seems that it fails to apply this patch and the following error is
complained.
>error: patch failed: src/Makefile.am:16
On 01/24/2017 12:36 PM, Pengfei Qu wrote:
Signed-off-by: Pengfei Qu
Reviewed-by: Sean V Kelley
---
;
+
+struct mbenc_param{
+uint32_t frame_width_in_mb;
+uint32_t frame_height_in_mb;
+uint32_t mbenc_i_frame_dist_in_use;
+uint32_t mad_enable;
+uint32_t roi_enabled;
+uint3
On 01/24/2017 12:36 PM, Pengfei Qu wrote:
v1:add kernel pointer for different platform
+
+#ifndef _I965_AVC_ENCODER_COMMON_H
+#define _I965_AVC_ENCODER_COMMON_H
+
+#include
+#include
+#include
+#include
+#include
+#include "intel_driver.h"
+
+// SubMbPartMask defined in CURBE for AVC ENC
+#defi
On 01/24/2017 12:36 PM, Pengfei Qu wrote:
v1:
add context init function for AVC encoder
v2:
add file in the Makefile.am
Signed-off-by: Pengfei Qu
Reviewed-by: Sean V Kelley
---
src/Makefile.am | 3 +
src/i965_encoder_api.h| 47 +
src/i965_encoder_common.c | 124
On 01/22/2017 03:36 PM, Pengfei Qu wrote:
v1:
add context init function for AVC encoder
v2:
add file in the Makefile.am
Signed-off-by: Pengfei Qu
Reviewed-by: Sean V Kelley
---
src/Makefile.am | 3 +
src/i965_encoder_api.h| 47
src/i965_encoder_common.c | 124 +
On 01/22/2017 03:36 PM, Pengfei Qu wrote:
Encoder architecture restructuring for H.264 (with some impact to HEVC now) on
HSW+
Sorry that patch 04 is missing.
* Improvements to the shaders
* Improvements to the B frame efficiency
* Improvements to the low bit rate mode
* Improved features in
On 01/22/2017 03:36 PM, Pengfei Qu wrote:
v1:
add align version for obj surface conversion to gpe surface
remove comments and enum value
Signed-off-by: Pengfei Qu
Reviewed-by: Sean V Kelley
---
src/gen9_vp9_encoder.c | 154 ++---
src/gen9_vp9_encoder.h | 10 --
src/i
On 01/13/2017 05:24 PM, Pengfei Qu wrote:
MFX pipeline:
add MFX command for AVC encoder
add MFX Picture slice level command init for AVC
add MFX pipeline init prepare run for AVC encode
add VME/MFX context init for AVC encoder
Please see the inline comment.
Reviewed-by: Sean V Kelley
Signed-
On 01/13/2017 05:24 PM, Pengfei Qu wrote:
Encoder architecture restructuring for H.264 (with some impact to HEVC now) on
HSW+
* Improvements to the shaders
* Improvements to the B frame efficiency
* Improvements to the low bit rate mode
* Improved features in two stage VME/PAK pipeline
v1:
Redu
On 01/13/2017 05:24 PM, Pengfei Qu wrote:
add context init function for AVC encoder
More comments are added.
Signed-off-by: Pengfei Qu
Reviewed-by: Sean V Kelley
---
src/i965_encoder_api.h| 47
src/i965_encoder_common.c | 124 +++
src/i965_encoder_common.h | 533 +++
On 01/13/2017 05:24 PM, Pengfei Qu wrote:
add context init function for AVC encoder
Signed-off-by: Pengfei Qu
Reviewed-by: Sean V Kelley
---
src/i965_encoder_api.h| 47
src/i965_encoder_common.c | 124 +++
src/i965_encoder_common.h | 533
On 01/13/2017 05:24 PM, Pengfei Qu wrote:
v1:
add align version for obj surface conversion to gpe surface
remove comments and enum value
This version patch looks much clearer.
But it seems that the this patch still adds more defintions besides
moving the GPE functions for generic usage.
S
Signed-off-by: Zhao Yakui
---
src/gen8_mfc.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/gen8_mfc.c b/src/gen8_mfc.c
index 7efe66e..9ea7423 100644
--- a/src/gen8_mfc.c
+++ b/src/gen8_mfc.c
@@ -1642,11 +1642,12 @@ gen8_mfc_avc_batchbuffer_pipeline(VADriverContextP
Signed-off-by: Zhao Yakui
---
src/gen9_vp9_encoder.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/gen9_vp9_encoder.c b/src/gen9_vp9_encoder.c
index 0de2cd7..f5c250b 100644
--- a/src/gen9_vp9_encoder.c
+++ b/src/gen9_vp9_encoder.c
@@ -5613,6 +5613,8 @@ gen9_vp9_pak_pipeline_prepare
The access domain is not configured correctly for PAK_OBJ command buffer.
And it causes that the buffer content is not synchronized correctly.
At the same time the 64-byte is aligned for the boundary between
CPU and GPU access instead of 16-byte.
Signed-off-by: Zhao Yakui
---
src/gen8_mfc.c
The MOCS field is used to define the cache type for the given buffer. From the
SKL+, the MOCS field is interpreted as the index that is used to find the
corresponding
cache type in kernel driver. The current MOCS setting causes that buffer uses
the wrong cache type.
Signed-off-by: Zhao Yakui
Currently it works well for 32-bit address. But it will cause that the
upper 32-bit address is incorrect if the 48-bit address buffer is allocated.
Signed-off-by: Zhao Yakui
---
src/gen75_vpp_vebox.c | 39 +++-
src/gen8_mfc.c | 73
On 01/11/2017 07:37 AM, Sean V Kelley wrote:
Encoder architecture restructuring for H.264 (with some impact to HEVC now) on
HSW+
* Improvements to the shaders
* Improvements to the B frame efficiency
* Improvements to the low bit rate mode
* Improved features in two stage VME/PAK pipeline
Aft
On 01/11/2017 07:38 AM, Sean V Kelley wrote:
From: Pengfei Qu
The OUT_BCS_RELOC issue still exits.
Please use the OUT_BCS_RELOC64 instead.
Signed-off-by: Pengfei Qu
Reviewed-by: Sean V Kelley
---
src/gen9_avc_encoder.c | 399 +
1 file chang
On 01/11/2017 07:37 AM, Sean V Kelley wrote:
From: Pengfei Qu
It seems that the patch 09/10/11 are trying to add the function of
buffer allocation/free back and forth.
Can these be merged together?
Thanks
Signed-off-by: Pengfei Qu
Reviewed-by: Sean V Kelley
---
src/gen9_avc_encoder.c |
On 01/11/2017 07:37 AM, Sean V Kelley wrote:
From: Pengfei Qu
Signed-off-by: Pengfei Qu
Reviewed-by: Sean V Kelley
---
src/gen9_avc_encoder.c | 548 +
1 file changed, 548 insertions(+)
create mode 100755 src/gen9_avc_encoder.c
diff --git a/sr
On 01/11/2017 07:37 AM, Sean V Kelley wrote:
From: Pengfei Qu
Signed-off-by: Pengfei Qu
Reviewed-by: Sean V Kelley
---
src/i965_avc_encoder_common.c | 319 ++
src/i965_avc_encoder_common.h | 305
2 files changed
On 01/11/2017 07:37 AM, Sean V Kelley wrote:
From: Pengfei Qu
Signed-off-by: Pengfei Qu
Reviewed-by: Sean V Kelley
---
src/i965_encoder_api.h | 59 ++
1 file changed, 59 insertions(+)
create mode 100755 src/i965_encoder_api.h
diff --git a/src
On 01/11/2017 07:37 AM, Sean V Kelley wrote:
From: Pengfei Qu
Signed-off-by: Pengfei Qu
Reviewed-by: Sean V Kelley
---
src/i965_encoder_common.c | 124 +++
src/i965_encoder_common.h | 533 ++
2 files changed, 657 insertions(+)
create mode
On 01/11/2017 07:37 AM, Sean V Kelley wrote:
From: Pengfei Qu
Signed-off-by: Pengfei Qu
Reviewed-by: Sean V Kelley
---
src/gen9_vp9_encoder.c | 154 ++--
src/gen9_vp9_encoder.h | 10 --
src/i965_gpe_utils.c | 265 -
On 12/31/2016 01:54 AM, Mark Thompson wrote:
On 30/12/16 00:14, Zhao Yakui wrote:
On 12/30/2016 02:52 AM, Mark Thompson wrote:
On 29/12/16 07:09, Zhao Yakui wrote:
On 12/29/2016 03:08 PM, Xiang, Haihao wrote:
On 12/29/2016 01:22 PM, Xiang, Haihao wrote:
User can use
On 12/30/2016 04:08 PM, peng.chen wrote:
Signed-off-by: peng.chen
In fact the dri_bo_unreference function can handle the scenario that bo
is NULL.
Of course it also looks good to me that the explicit check is added in
the i965_destroy_surface_storage.
Add: Reviewed-by: Zhao Yakui
ntrol for bitrate control.
This looks good to me.
Add: Reviewed-by: Zhao Yakui
Signed-off-by: Xiang, Haihao
---
src/i965_drv_video.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/src/i965_drv_video.c b/src/i965_drv_video.c
index 15920f5..51a708c 100644
---
On 12/30/2016 02:52 AM, Mark Thompson wrote:
On 29/12/16 07:09, Zhao Yakui wrote:
On 12/29/2016 03:08 PM, Xiang, Haihao wrote:
On 12/29/2016 01:22 PM, Xiang, Haihao wrote:
User can use VAEncMiscParameterRateControl to update bitrate, so we
should ignore
the bitrate in the sequence parameter
uence?
Yes if bits_per_second in the sequence parameter is not equal to the
value for the previous Begin/Render/End sequence except bits_per_second
in the sequence parameter is 0.
OK.
It makes sense.
This looks good to me.
Add: Reviewed-by: Zhao Yakui
Thanks
Yakui
Thanks
Yakui
Signe
On 12/29/2016 01:22 PM, Xiang, Haihao wrote:
User can use VAEncMiscParameterRateControl to update bitrate, so we should
ignore
the bitrate in the sequence parameter if VAEncMiscParameterRateControl is
present.
This makes sense. The MiscRateControl mentions that it can override the
bps settin
Signed-off-by: Zhao Yakui
---
src/i965_encoder.c | 16
1 file changed, 16 insertions(+)
diff --git a/src/i965_encoder.c b/src/i965_encoder.c
index be37b84..3099175 100644
--- a/src/i965_encoder.c
+++ b/src/i965_encoder.c
@@ -1047,8 +1047,15 @@ intel_encoder_check_hevc_parameter
On 12/07/2016 01:48 PM, Xiang, Haihao wrote:
Now we have the same way for frame rate for each codec in i965_encoder.c, it
would be better to use the result directly
Hi, Mark
Can you refresh your patch based on Haihao's suggestion?
Now the frame rate is parsed in the function of
intel
On 12/06/2016 02:02 AM, Mark Thompson wrote:
Signed-off-by: Mark Thompson
Good work.
This patch looks good to me.
Add: Reviewed-by: Zhao Yakui
Thanks
---
Tested on Kaby Lake. Someone who has access to the manuals should make sure
that the framerate numerator/denominator actually works
On 12/06/2016 01:49 AM, Mark Thompson wrote:
Signed-off-by: Mark Thompson
---
It's already returned as a usable surface format for the video processor, but
is missing from the list returned by vaQueryImageFormats().
src/i965_drv_video.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/s
gpe->reset_bindind_table()
and so on.
This patch looks fine to me.
Add: Reviewed-by: Zhao Yakui
Signed-off-by: Xiang, Haihao
---
src/gen6_mfc.h | 2 +-
src/i965_drv_video.c | 6
src/i965_drv_video.h | 3 ++
src/i965_gpe_utils.c | 72
On 11/29/2016 12:33 PM, Xiang, Haihao wrote:
Instead we can use the parameters saved in the common encoder context.
It also corrects frame rate used in VDEnc
v2: Align the ROI region and fix compile error after rebase
This looks fine to me.
Thanks
Signed-off-by: Xiang, Haihao
---
src/gen
On 11/29/2016 12:33 PM, Xiang, Haihao wrote:
From: "peng.chen"
These parameters can be used for all codecs
This looks fine to me.
Thanks
v2: Save mb_rate_control/target_percentage per layer too
Signed-off-by: peng.chen
Signed-off-by: Xiang, Haihao
---
src/i965_encoder.c | 14 +++
On 11/29/2016 12:33 PM, Xiang, Haihao wrote:
From: "peng.chen"
These parameters can be used for all codecs
v2: Don't align ROI region, each codec might have
special requirement
This looks fine to me.
Thanks
Signed-off-by: peng.chen
Signed-off-by: Xiang, Haihao
---
src/i965_encoder.c | 3
On 11/28/2016 03:22 PM, Xiang, Haihao wrote:
On 11/25/2016 04:22 PM, Xiang, Haihao wrote:
From: "peng.chen"
These parameters can be used for all codecs
Signed-off-by: peng.chen
Signed-off-by: Xiang, Haihao
---
src/i965_encoder.c | 14 +-
src/i965_encoder.h | 2 ++
2 files
On 11/25/2016 04:22 PM, Xiang, Haihao wrote:
From: "peng.chen"
These parameters can be used for all codecs
Signed-off-by: peng.chen
Signed-off-by: Xiang, Haihao
---
src/i965_encoder.c | 14 +-
src/i965_encoder.h | 2 ++
2 files changed, 15 insertions(+), 1 deletion(-)
diff --g
On 11/25/2016 04:22 PM, Xiang, Haihao wrote:
From: "peng.chen"
These parameters can be used for all codecs
Signed-off-by: peng.chen
Signed-off-by: Xiang, Haihao
---
src/i965_encoder.c | 40
src/i965_encoder.h | 6 ++
2 files changed, 46 insertio
On 11/25/2016 04:36 PM, Xiang, Haihao wrote:
This is to define some common structures/functions so that they can
be used on more platforms when adding new VPP functions.
Here new VPP functions just means CSC and scaling, right?
Yes.
Thanks
Yakui
Signed-off-by: Zhao Yakui
---
src
is executed on part region of one surface.
They are for the different purpose. So it is not appropriate that the
CSC and clearing backgroud color are combined together.
Thanks
Yakui
The following conversion is supported:
NV12->NV12
NV12->I420
I420->NV12
I420->I420
Signed-off
V1->V2: Add the support of clearing background color for NV12
The following conversion is supported:
NV12->NV12
NV12->I420
I420->NV12
I420->I420
Signed-off-by: Zhao Yakui
---
src/Makefile.am| 1 +
src/gen75_picture_process.c
The following conversion is supported:
NV12->NV12
NV12->I420
I420->NV12
I420->I420
Signed-off-by: Zhao Yakui
---
src/gen8_post_processing.c | 450 +
src/intel_common_vpp_internal.c| 10 +-
src/intel_common_vp
This is to define some common structures/functions so that they can
be used on more platforms when adding new VPP functions.
Signed-off-by: Zhao Yakui
---
src/Makefile.am | 2 ++
src/gen75_picture_process.c | 1 +
src/gen8_post_processing.h | 8 -
src
This is to define some common structures/functions so that they can
be used on more platforms when adding new VPP functions.
Signed-off-by: Zhao Yakui
---
src/Makefile.am | 2 ++
src/gen75_picture_process.c | 1 +
src/gen8_post_processing.h | 8 -
src
The following conversion is supported:
NV12->NV12
NV12->I420
I420->NV12
I420->I420
Signed-off-by: Zhao Yakui
---
src/Makefile.am| 1 +
src/gen75_picture_process.c| 34 +++
src/gen8_post_processing.c
The following conversion is supported:
NV12->NV12
NV12->I420
I420->NV12
I420->I420
Signed-off-by: Zhao Yakui
---
src/gen8_post_processing.c | 450 +
src/intel_common_vpp_internal.c| 10 +-
src/intel_common_vp
On 11/22/2016 08:51 AM, Li, ZhijianX wrote:
-Original Message-
From: Xiang, Haihao
Sent: Monday, November 21, 2016 11:25 PM
To: Li, ZhijianX; libva@lists.freedesktop.org
Subject: RE: [Libva] [PATCH] va.h: fix compile warning
Although taking unspecified arguments is obsolete, I don't s
I010 format is another kind of 10-bit surface. And its layout is similar to
I420.
Signed-off-by: Zhao Yakui
---
src/gen75_picture_process.c | 45 ++---
1 file changed, 42 insertions(+), 3 deletions(-)
diff --git a/src/gen75_picture_process.c b/src
If it is not supported, it will fall back to the original config.
Signed-off-by: Zhao Yakui
Reviewed-by: Charles Daniel
---
src/gen8_mfc.c | 6 +-
src/gen8_post_processing.c | 5 -
src/gen8_vme.c | 8 +++-
src/gen9_post_processing.c | 12
src
And it is treated as non-tiling for I010 surfaces, which is like I420.
Every pixel also uses two bytes like P010 but it occupies the lower 10-bit.
Signed-off-by: Zhao Yakui
---
src/i965_drv_video.c | 23 +++
src/i965_fourcc.h| 4
2 files changed, 27 insertions
This info can be used to configure the max EU threads of GPU device.
>eu_total * 6
V2->V3: Refresh the patches again.
V1->V2: Remove the extra bit_field of has_eu_flag. Instead the eu_total > 0
can be used.
Signed-off-by: Zhao Yakui
Reviewed-by: Charles Daniel
---
src/intel_d
;V2: Remove the extra bit_field of has_eu_flag. Instead the
eu_total> 0
can be used.
Signed-off-by: Zhao Yakui
Reviewed-by: Charles Daniel
---
src/intel_driver.c | 11 +++
src/intel_driver.h | 2 ++
2 files changed, 13 insertions(+)
diff --git a/src/intel_driver.c b/src/intel_dr
On 11/18/2016 01:43 PM, Xiang, Haihao wrote:
Signed-off-by: Xiang, Haihao
This looks good to me.
Thanks
---
src/i965_gpe_utils.c | 16
src/i965_gpe_utils.h | 19 +++
src/intel_driver.h | 6 ++
3 files changed, 41 insertions(+)
diff --git a/src/i96
On 11/18/2016 01:43 PM, Xiang, Haihao wrote:
Signed-off-by: Xiang, Haihao
This looks good to me.
Thanks
---
src/i965_gpe_utils.c | 73
src/i965_gpe_utils.h | 5
2 files changed, 78 insertions(+)
diff --git a/src/i965_gpe_utils.c
On 11/18/2016 01:43 PM, Xiang, Haihao wrote:
v2: Add support for override_offset, clean up the code for 2D surface.
This looks good to me.
Thanks
Signed-off-by: Xiang, Haihao
---
src/i965_gpe_utils.c | 217 +++
src/i965_gpe_utils.h | 5 ++
On 11/18/2016 01:43 PM, Xiang, Haihao wrote:
This looks good to me.
Thanks
Signed-off-by: Xiang, Haihao
---
src/i965_gpe_utils.c | 18 +-
src/i965_gpe_utils.h | 3 ++-
2 files changed, 19 insertions(+), 2 deletions(-)
diff --git a/src/i965_gpe_utils.c b/src/i965_gpe_utils.
On 11/18/2016 01:43 PM, Xiang, Haihao wrote:
This function can be used on GEN8 too
The patch looks good to me.
But please change the title to "gen8_gpe_mi_store_register_mem" instead
of gen8_gpe_mi_load_register_mem
Thanks.
Signed-off-by: Xiang, Haihao
---
src/gen9_vdenc.c | 10 ++
On 11/18/2016 01:43 PM, Xiang, Haihao wrote:
This function can be used on GEN8 too
This looks good to me.
Thanks
Signed-off-by: Xiang, Haihao
---
src/gen9_vdenc.c | 4 ++--
src/gen9_vp9_encoder.c | 4 ++--
src/i965_gpe_utils.c | 2 +-
src/i965_gpe_utils.h | 2 +-
4 files cha
On 11/18/2016 01:43 PM, Xiang, Haihao wrote:
This function can be used on GEN8 too
This looks good to me.
Signed-off-by: Xiang, Haihao
---
src/gen9_vdenc.c | 2 +-
src/gen9_vp9_encoder.c | 6 +++---
src/i965_gpe_utils.c | 2 +-
src/i965_gpe_utils.h | 2 +-
4 files changed, 6 i
On 11/18/2016 01:43 PM, Xiang, Haihao wrote:
This function can be used on GEN8 too
This looks good to me.
Thanks
Signed-off-by: Xiang, Haihao
---
src/gen9_post_processing.c | 2 +-
src/gen9_vp9_encoder.c | 2 +-
src/i965_gpe_utils.c | 2 +-
src/i965_gpe_utils.h | 2 +-
On 11/18/2016 01:43 PM, Xiang, Haihao wrote:
Like as i965_dri_object_to_buffer_gpe_resource(), use i965_ instead of
i965_gpe_ as prefix
This looks good to me.
Thanks
Signed-off-by: Xiang, Haihao
---
src/gen9_post_processing.c | 2 +-
src/gen9_vp9_encoder.c | 2 +-
src/i965_gpe_ut
On 11/18/2016 01:43 PM, Xiang, Haihao wrote:
gpe_context->curbe.bo always points to the curbe buffer now, and the two
functions
can be used on all platforms
This looks good to me.
Thanks
Yakui
Signed-off-by: Xiang, Haihao
---
src/gen9_post_processing.c | 4 ++--
src/gen9_vp9_encoder.
On 11/18/2016 01:43 PM, Xiang, Haihao wrote:
It is multiple of 64 bytes
This looks good to me.
Add: Reviewed-by: Zhao Yakui
Signed-off-by: Xiang, Haihao
---
src/i965_gpe_utils.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/i965_gpe_utils.c b/src
On 11/18/2016 01:43 PM, Xiang, Haihao wrote:
Make sure the size for each part in dynamic state buffer is multiple of 64
bytes.
This looks good to me.
Add: Reviewed-by: Zhao Yakui
Signed-off-by: Xiang, Haihao
---
src/i965_gpe_utils.c | 9 +
1 file changed, 5 insertions(+), 4
dynamic
state buffer or not.
This looks good to me.
Add: Reviewed-by: Zhao Yakui
Signed-off-by: Xiang, Haihao
---
src/gen8_mfc.c | 3 ++-
src/gen8_vme.c | 4 ++--
src/gen9_post_processing.c | 13 +++--
src/gen9_vme.c | 4 ++--
src
this
table is a part of the dynamic state buffer or not.
This looks good to me.
Add: Reviewed-by: Zhao Yakui
Thanks
Signed-off-by: Xiang, Haihao
---
src/gen75_vpp_gpe.c| 10 +-
src/gen8_mfc.c | 7 ---
src/gen8_vme.c | 8 +---
src
buffer or not.
This looks good to me.
Add: Reviewed-by: Zhao Yakui
Signed-off-by: Xiang, Haihao
---
src/gen75_vpp_gpe.c| 2 +-
src/gen8_mfc.c | 2 +-
src/gen8_vme.c | 12 ++--
src/gen9_post_processing.c | 3 +--
src/gen9_vme.c | 12
On 11/18/2016 01:43 PM, Xiang, Haihao wrote:
Make sure the size is multiple of 64 bytes
This looks good to me.
Add: Reviewed-by: Zhao Yakui
Signed-off-by: Xiang, Haihao
---
src/i965_gpe_utils.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/src
And it is treated as non-tiling for I010 surfaces, which is like I420.
Signed-off-by: Zhao Yakui
---
src/i965_drv_video.c | 23 +++
src/i965_fourcc.h| 4
2 files changed, 27 insertions(+)
diff --git a/src/i965_drv_video.c b/src/i965_drv_video.c
index 04670f4
I010 format is another kind of 10-bit surface. And its layout is similar to
I420.
Signed-off-by: Zhao Yakui
---
src/gen75_picture_process.c | 45 ++---
1 file changed, 42 insertions(+), 3 deletions(-)
diff --git a/src/gen75_picture_process.c b/src
If it is not supported, it will fall back to the original config.
Signed-off-by: Zhao Yakui
Reviewed-by: Charles Daniel
---
src/gen8_mfc.c | 6 +-
src/gen8_post_processing.c | 5 -
src/gen8_vme.c | 7 ++-
src/gen9_post_processing.c | 12
src
This info can be used to configure the max EU threads of GPU device.
>eu_total * 6
V1->V2: Remove the extra bit_field of has_eu_flag. Instead the eu_total > 0
can be used.
Signed-off-by: Zhao Yakui
Reviewed-by: Charles Daniel
---
src/intel_driver.c | 11 +++
src/intel_driv
On 11/18/2016 09:42 AM, Xiang, Haihao wrote:
On 11/18/2016 12:58 AM, Xiang, Haihao wrote:
-Original Message-
From: Zhao, Yakui
Sent: Thursday, November 17, 2016 8:42 PM
To: Xiang, Haihao
Cc: libva@lists.freedesktop.org
Subject: Re: [Libva] [Libva-intel-driver][PATCH 02/17] Move all
I010 is another kind of 10-bit format. Its layout is similar to IYUV(I420).
And the lower 10-bit is used.
Signed-off-by: Zhao Yakui
---
va/va.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/va/va.h b/va/va.h
index 88628a8..153a89b 100644
--- a/va/va.h
+++ b/va/va.h
@@ -2545,6
On 11/18/2016 08:47 AM, Xiang, Haihao wrote:
On Wed, 2016-11-16 at 21:06 -0500, Zhao Yakui wrote:
This info can be used to configure the max EU threads of GPU device.
eu_total * 6
Signed-off-by: Zhao Yakui
---
src/intel_driver.c | 13 +
src/intel_driver.h | 3 +++
2 files
On 11/18/2016 09:00 AM, Xiang, Haihao wrote:
Could you add the new FOURCC in libva as well ?
Sure.
Thanks
Haihao
And it is treated as non-tiling for I010 surfaces, which is like
I420.
Signed-off-by: Zhao Yakui
---
src/i965_drv_video.c | 23 +++
src/i965_fourcc.h
On 11/18/2016 12:22 AM, Xiang, Haihao wrote:
-Original Message-
From: Zhao, Yakui
Sent: Thursday, November 17, 2016 8:47 PM
To: Xiang, Haihao
Cc: libva@lists.freedesktop.org
Subject: Re: [Libva] [Libva-intel-driver][PATCH 06/17] Fix curbe length in
CMD_MEDIA_CURBE_LOAD on GEN8+
On 11
On 11/17/2016 11:48 PM, Xiang, Haihao wrote:
-Original Message-
From: Zhao, Yakui
Sent: Thursday, November 17, 2016 9:14 PM
To: Xiang, Haihao
Cc: libva@lists.freedesktop.org
Subject: Re: [Libva] [Libva-intel-driver][PATCH 15/17] Add a new gpe function
gen8_gpe_context_add_surface() to
On 11/18/2016 12:12 AM, Xiang, Haihao wrote:
-Original Message-
From: Libva [mailto:libva-boun...@lists.freedesktop.org] On Behalf Of Zhao
Yakui
Sent: Thursday, November 17, 2016 8:59 PM
To: libva@lists.freedesktop.org
Subject: Re: [Libva] [Libva-intel-driver][PATCH 09/17] Rename
On 11/18/2016 12:58 AM, Xiang, Haihao wrote:
-Original Message-
From: Zhao, Yakui
Sent: Thursday, November 17, 2016 8:42 PM
To: Xiang, Haihao
Cc: libva@lists.freedesktop.org
Subject: Re: [Libva] [Libva-intel-driver][PATCH 02/17] Move all curbe related
settings to the inner structure
On 11/17/2016 04:35 PM, Xiang, Haihao wrote:
Signed-off-by: Xiang, Haihao
Can the gen8_gpe_context_add_surface follow the similar logic in
gen9_gpe_context_add_surface?
>2d_surface && override_offset
>2d && is_uv
>2d
>adv
>buffer
The 2d_surface && override_offset is especia
On 11/17/2016 04:35 PM, Xiang, Haihao wrote:
This function can be used on GEN8 too
Based on HW spec, Broadwell and Gen9 have some difference about the
MEDIA_OBJECT_WALKER commands.
So it will be better to add a new wrapper of media_object_walker for gen8.
Thanks
Signed-off-by: Xiang, Haih
On 11/17/2016 04:35 PM, Xiang, Haihao wrote:
It is multiple of 64 bytes
Can we align the size of curbe_buffer when calling the
gen8_gpe_context_init?
Signed-off-by: Xiang, Haihao
---
src/i965_gpe_utils.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/i965_gpe_ut
On 11/17/2016 04:35 PM, Xiang, Haihao wrote:
To avoid confusion between curbe.length and curbe_size, this patch uses
curbe.length only. curbe.bo is always set even if curbe is a part of the
dynamic state buffer, hence we can use curbe related settings no matter
it is a part of the dynamic state b
I010 format is another kind of 10-bit surface. And its layout is similar to
I420.
Signed-off-by: Zhao Yakui
---
src/gen75_picture_process.c | 45 ++---
1 file changed, 42 insertions(+), 3 deletions(-)
diff --git a/src/gen75_picture_process.c b/src
This will help to make good use of HW EU resources.
If it is not supported, it will fall back to the original config.
Signed-off-by: Zhao Yakui
---
src/gen8_mfc.c | 6 +-
src/gen8_post_processing.c | 5 -
src/gen8_vme.c | 7 ++-
src/gen9_post_processing.c
This info can be used to configure the max EU threads of GPU device.
>eu_total * 6
Signed-off-by: Zhao Yakui
---
src/intel_driver.c | 13 +
src/intel_driver.h | 3 +++
2 files changed, 16 insertions(+)
diff --git a/src/intel_driver.c b/src/intel_driver.c
index bb19401..a2c8
And it is treated as non-tiling for I010 surfaces, which is like I420.
Signed-off-by: Zhao Yakui
---
src/i965_drv_video.c | 23 +++
src/i965_fourcc.h| 4
2 files changed, 27 insertions(+)
diff --git a/src/i965_drv_video.c b/src/i965_drv_video.c
index 04670f4
good to me as it adds more restrict check for
VP9 encoding. This will help to check the wrong parameter passed by the
user.
Add: Reviewed-by: Zhao Yakui
Thanks
Signed-off-by: Daniel Charles
---
src/i965_device_info.c | 1 +
src/i965_drv_video.c | 2 +-
src/i965_drv_video.h | 5
On 11/16/2016 09:01 AM, Zhao Yakui wrote:
On 11/15/2016 06:43 AM, Sean V Kelley wrote:
On Thu, Nov 10, 2016 at 5:56 PM, Zhao Yakui wrote:
V1->V2: Add the conv_p010.g9b shader into the dist list
+ width, height, pitch,
+ gpe_resource->bo->offset64 + gpe_surface->
On 11/15/2016 06:43 AM, Sean V Kelley wrote:
On Thu, Nov 10, 2016 at 5:56 PM, Zhao Yakui wrote:
V1->V2: Add the conv_p010.g9b shader into the dist list
Signed-off-by: Zhao Yakui
---
src/gen75_vpp_vebox.c | 2 +
src/gen75_vpp_vebox.h |
to VEBOX.
Signed-off-by: Zhao Yakui
Reviewed-by: Xiang, Haihao
---
src/gen75_picture_process.c | 50 +++--
1 file changed, 44 insertions(+), 6 deletions(-)
diff --git a/src/gen75_picture_process.c b/src/gen75_picture_process.c
index ee99c88..d012ba4 100644
This is the HW requirement and it is handled internally.
Signed-off-by: Zhao Yakui
Reviewed-by: Xiang, Haihao
---
src/gen75_picture_process.c | 8
1 file changed, 8 insertions(+)
diff --git a/src/gen75_picture_process.c b/src/gen75_picture_process.c
index d012ba4..40b4ffc 100644
--- a
Signed-off-by: Zhao Yakui
Reviewed-by: Xiang, Haihao
---
src/i965_gpe_utils.c | 48
src/i965_gpe_utils.h | 14 ++
2 files changed, 62 insertions(+)
diff --git a/src/i965_gpe_utils.c b/src/i965_gpe_utils.c
index d824c18..f394c07 100644
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