This adds the required device tree nodes to bring up the
secondary cores on the ipq4019 SoC.
Signed-off-by: Matthew McClintock
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 60 +
1 file changed, 60 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi
b
This adds the required device tree nodes to bring up the
secondary cores on the ipq4019 SoC.
Signed-off-by: Matthew McClintock
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 60 +
1 file changed, 60 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi
b
Lina Iyer writes:
> A PM domain comprising of CPUs may be powered off when all the CPUs in
> the domain are powered down. Powering down a CPU domain is generally a
> expensive operation and therefore the power performance trade offs
> should be considered. The time between the last CPU powering d
Lorenzo Pieralisi writes:
> On Tue, Nov 17, 2015 at 03:37:42PM -0700, Lina Iyer wrote:
>> A PM domain comprising of CPUs may be powered off when all the CPUs in
>> the domain are powered down. Powering down a CPU domain is generally a
>> expensive operation and therefore the power performance tra
Lina Iyer writes:
> Reading the next wakeup of the CPU can only be realiably done only from
> that CPU. In the idle enter path record the next wake up of the CPU. The
> information is useful to determine the sleep time left for the CPU.
>
> Signed-off-by: Lina Iyer
> ---
> drivers/cpuidle/cpuid
From: Varadarajan Narayanan
This patch adds support for the global clock controller found on
the IPQ4019 based devices. This includes UART, I2C, SPI etc.
Signed-off-by: Pradeep Banavathi
Signed-off-by: Senthilkumar N L
Signed-off-by: Varadarajan Narayanan
Signed-off-by: Matthew McClintock
--
From: Matthew McClintock
Add initial dts files and SoC support for IPQ4019
Signed-off-by: Varadarajan Narayanan
---
v2
- add sleep_clk
arch/arm/boot/dts/qcom-ipq4019.dtsi | 115
1 file changed, 115 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-
From: Matthew McClintock
This will select qcom board type when the machine compatible is
qcom,ipq4019.
Signed-off-by: Matthew McClintock
---
arch/arm/mach-qcom/board.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-qcom/board.c b/arch/arm/mach-qcom/board.c
index 6d8bbf7..b52
From: Matthew McClintock
Initial board support dts files for DK01 board.
Signed-off-by: Senthilkumar N L
Signed-off-by: Varadarajan Narayanan
---
v2
- add xo clock
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts | 22 +
arch/ar
From: Varadarajan Narayanan
Add pinctrl driver support for IPQ4019 platform
Signed-off-by: Sricharan R
Signed-off-by: Mathieu Olivari
Signed-off-by: Varadarajan Narayanan
Signed-off-by: Matthew McClintock
---
v3
- update example with actual values from dts
- add missing pins 71-99
- drop ma
This patch series adds basic support for IPQ8019 series of SoCs,
presently it just boots to prompt via serial but more functionality
will follow.
This is partially based off a previously submitted patch series from
Varada which can be found here:
https://patchwork.ozlabs.org/patch/509954/
The IP
Lina Iyer writes:
> Allow devices that know when their next wakeup event is, to record save
> it as part of timing data. A genpd governor may use this data to
> determine if suspending the domain is going to affect the QoS of its
> devices.
>
> Signed-off-by: Lina Iyer
> ---
> include/linux/pm_
Lina Iyer writes:
> Notify runtime PM when the CPU is going to be powered off in the idle
> state. This allows for runtime PM suspend/resume of the CPU as well as
> its PM domain.
>
> Cc: Daniel Lezcano
> Cc: Lorenzo Pieralisi
> Signed-off-by: Lina Iyer
> ---
> drivers/cpuidle/cpuidle-arm.c |
Lina Iyer writes:
> Allow domain states to hold additional state related data in a u32
> value. This may be used by the platform driver.
Should probably expand the changelog here to give some examples how how
this might be used by the platform driver.
Kevin
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On Thu, Nov 19 2015 at 07:37 -0700, Rob Herring wrote:
On Tue, Nov 17, 2015 at 4:37 PM, Lina Iyer wrote:
From: Kumar Gala
The top level qcom,msm-id and qcom,board-id are utilized by bootloaders
on Qualcomm MSM platforms to determine which device tree should be
utilized and passed to the kerne
On Tue, Nov 17, 2015 at 05:00:26PM -0800, Stephen Boyd wrote:
> The drivers don't really need to know which PMIC they're for, so
> make a generic binding for them. This alleviates us from updating
> the drivers every time a new PMIC comes out. It's still
> recommended that we update the binding wit
On Tue, Nov 17, 2015 at 04:52:33PM -0800, Stephen Boyd wrote:
> Update the driver and binding for pm8994-mpp devices.
>
> Cc:
> Cc: "Ivan T. Ivanov"
> Cc: Bjorn Andersson
> Signed-off-by: Stephen Boyd
Acked-by: Rob Herring
> ---
> Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt
On Tue, Nov 17, 2015 at 04:52:32PM -0800, Stephen Boyd wrote:
> Update the binding and driver for pm8994-gpio devices.
>
> Cc:
> Cc: "Ivan T. Ivanov"
> Cc: Bjorn Andersson
> Signed-off-by: Stephen Boyd
Acked-by: Rob Herring
> ---
> Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.t
On Tue, Nov 17, 2015 at 04:35:46PM -0800, Stephen Boyd wrote:
> From: Joonwoo Park
>
> Add initial pinctrl driver to support pin configuration with
> pinctrl framework for msm8996.
>
> Cc:
> Cc: Bjorn Andersson
> Signed-off-by: Joonwoo Park
> [sb...@codeaurora.org: Remove duplicate entries an
On Tue, Nov 17, 2015 at 4:37 PM, Lina Iyer wrote:
> From: Kumar Gala
>
> The top level qcom,msm-id and qcom,board-id are utilized by bootloaders
> on Qualcomm MSM platforms to determine which device tree should be
> utilized and passed to the kernel.
See [1] and the link there to the prior versi
Move the xo and sleep clocks to device-tree, instead of hard-coding
them in the driver. This allows us to insert the RPM clocks (if they
are enabled) in between the on-board oscillators and the actual clock.
Signed-off-by: Georgi Djakov
---
drivers/clk/qcom/gcc-msm8916.c | 16 +++-
Currently the rates of the xo and sleep clocks are hard-coded in the
GCC driver, but this is a board layout description that actually should
be in the DT. Moving them into DT also allows us to insert the RPM
controlled clocks between the DT and GCC clocks.
Signed-off-by: Georgi Djakov
---
arch/a
Add support for clocks that are controlled by the RPM processor
on Qualcomm msm8916 based platforms.
Signed-off-by: Georgi Djakov
---
.../devicetree/bindings/clock/qcom,rpmcc.txt | 35
drivers/clk/qcom/Kconfig |8 +
drivers/clk/qcom/Makefile
Add the RPM Clock Controller DT node and include the necessary header
file for clocks.
Signed-off-by: Georgi Djakov
---
arch/arm64/boot/dts/qcom/msm8916.dtsi |6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi
b/arch/arm64/boot/dts/qcom/msm8916.dts
This adds initial support for clocks controlled by the Resource
Power Manager (RPM) processor found on some Qualcomm SoCs.
The RPM is a dedicated hardware engine for managing the shared
SoC resources in order to keep the lowest power profile. It
communicates with other hardware subsystems via shar
This patchset adds initial support for the clocks controlled by
the RPM (Resource Power Manager) processor on Qualcomm platforms.
The RPM is a dedicated hardware engine for managing the shared
SoC resources in order to keep the lowest power profile. It
communicates with other hardware subsystems v
On 18/11/2015 19:42, Lorenzo Pieralisi wrote:
On Tue, Nov 17, 2015 at 03:37:42PM -0700, Lina Iyer wrote:
A PM domain comprising of CPUs may be powered off when all the CPUs in
the domain are powered down. Powering down a CPU domain is generally a
expensive operation and therefore the power perfo
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