We want to make sure we control all the information being passed
down to SMP block. Having access to the cfg pointer here may create
bad things in the future.
Signed-off-by: Stephane Viau
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h | 2 +-
drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c | 8
2
This series of patches adds support for MSM8996, including MDP5 v1.7.
Note that only the HDMI interface is supported for now.
Stephane Viau (10):
drm/msm/mdp5: remove the cfg pointer from SMP struct
drm/msm/mdp5: Disable hardware translation table walks (MSM8996)
drm/msm: Fix IOMMU clean
hardware table walks in
the future
Signed-off-by: Stephane Viau
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
index bbab6e6..14ac20a 100644
--- a
could also overwrite those values for
optimization.
In some hardware (eg: MDP5 v1.7), software *must* program those
values since they are not handled in hardware.
Change-Id: I4900165e770f8da702a4f938044616daf5aa81af
Signed-off-by: Stephane Viau
---
rnndb/mdp/mdp5.xml | 24
v_err messages during the
probe.
Signed-off-by: Stephane Viau
---
Documentation/devicetree/bindings/drm/msm/mdp.txt | 3 ++-
drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c | 27 ++-
2 files changed, 18 insertions(+), 12 deletions(-)
diff --git a/Documentation/devicetree/bin
msm_iommu_new() can fail and this change makes sure that we
detect the failure and free the allocated domain before going
any further.
Signed-off-by: Stephane Viau
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c | 1 +
drivers/gpu/drm/msm/msm_gpu.c | 8
2 files changed, 9
: Stephane Viau
---
Documentation/devicetree/bindings/drm/msm/mdp.txt | 3 ++
drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c | 65 +++
drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h | 3 ++
3 files changed, 71 insertions(+)
diff --git a/Documentation/devicetree/bindings/drm/msm
The HDMI controller is new in MDP5 v1.7. As of now, this change
doesn't reflect the novelty and only adds the basics so the probe
gets triggered.
Signed-off-by: Stephane Viau
---
Documentation/devicetree/bindings/drm/msm/hdmi.txt | 3 +++
drivers/gpu/drm/msm/hdmi/hdmi.c
software. For some targets (e.g.: msm8996),
software *must* program those registers.
In order to ease this computation, let's always use bilinear
filters, which are easier to program from kernel. Eventually,
all of these values will come down from user space for better
quality.
Signed-off-by: Ste
This change is the output of Envytools change:
"rnndb: Add Pixel Extension registers"
Signed-off-by: Stephane Viau
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h | 82 +++-
drivers/gpu/drm/msm/mdp/mdp_common.xml.h | 11 -
2 files changed, 90
This change adds the basic MDP5 support for MSM8996.
Signed-off-by: Stephane Viau
---
Documentation/devicetree/bindings/drm/msm/mdp.txt | 2 +
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c | 95 ++-
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h | 9 ++-
drivers/gpu
When calculating phase steps, let's use the same enum
mdp_component_type in order to ease the readability; 0/1 indexes
are a bit confusing and we now have explicit values to index
this type of arrays.
Signed-off-by: Stephane Viau
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c
The current names were guessed based on downstream driver.
This change replaces the filter fields' names to avoid any
confusion.
Signed-off-by: Stephane Viau
---
rnndb/mdp/mdp5.xml | 15 +++
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/rnndb/mdp/mdp5.xml b/rnnd
enum mdp_chroma_samp_type's first value (0) is actually shared by
all non-subsampled formats; that is RGB but also some YUV formats
(eg: YUV444). This change makes the name a little less confusing.
Signed-off-by: Stephane Viau
Signed-off-by: Wentao Xu
---
rnndb/mdp/mdp_common.xml | 2
The current names were guessed based on downstream driver.
This change replaces the filter fields' names to avoid any
confusion.
Signed-off-by: Stephane Viau
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/dr
See envytools commit: "rnndb: Rename scalers' filter fields"
Signed-off-by: Stephane Viau
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h | 58 -
1 file changed, 29 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
From: Wentao Xu
This makes it easy to determine if a format is YUV. The old
method of using chroma sample type incorrectly marks YUV444 as
RGB format.
Signed-off-by: Wentao Xu
[rebase]
Signed-off-by: Stephane Viau
Change-Id: I3e1fa4473be8421fac8d79100f30bff5823be5f4
---
drivers/gpu/drm/msm
Add packed YUV422 and planar YUV420 formats to MDP supported
formats.
Signed-off-by: Stephane Viau
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c | 105 +-
drivers/gpu/drm/msm/mdp/mdp_format.c | 19 ++
2 files changed, 77 insertions(+), 47 deletions(-)
diff
From: Wentao Xu
Newer MDP5 uses 2 shared memory pool clients for certain YUV formats.
For example, if VIG0 is used to fetch data in YUYV format, it will use
VIG0_Y for Y component, and VIG0_Cr for UV packed.
Signed-off-by: Wentao Xu
[rebase]
Signed-off-by: Stephane Viau
Change-Id
See Envytools patch:
rnndb: Rename 1st Source Chroma Sampling option
Signed-off-by: Wentao Xu
Signed-off-by: Stephane Viau
---
drivers/gpu/drm/msm/mdp/mdp_common.xml.h | 37 +++-
1 file changed, 3 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm
,
Stephane.
Stephane Viau (4):
drm/msm/mdp5: Update generated headers (filter fieds)
drm/msm/mdp5: Rename scalers' filter fields
drm/msm/mdp: Update generated headers (chroma_samp)
drm/msm/mdp5: add more YUV formats for MDP5
Wentao Xu (2):
drm/msm/mdp: mark if a MDP format is Y
This change adds the MDP and HDMI support for msm8x94.
Note that HDMI PHY registers are not being accessed anymore from
the driver.
Signed-off-by: Stephane Viau
---
drivers/gpu/drm/msm/hdmi/hdmi.c | 30 -
drivers/gpu/drm/msm/hdmi/hdmi_bridge.c| 8 +++-
drivers/gpu/drm
ed-off-by: Stephane Viau
---
drivers/gpu/drm/msm/hdmi/hdmi.h | 1 -
drivers/gpu/drm/msm/hdmi/hdmi_connector.c | 51 ++-
drivers/gpu/drm/msm/hdmi/hdmi_phy_8960.c | 52
drivers/gpu/drm/msm/hdmi/hdmi_phy_8x60.c | 32 -
driver
This it to follow up with my RFC sent a few days ago[1].
Since the RFC got discussed and approved through IRC, here are the actual
patches.
Rgds,
Stephane.
[1] http://lists.freedesktop.org/archives/dri-devel/2015-June/084788.html
Stephane Viau (2):
drm/msm/hdmi: remove ->reset() from H
ed-off-by: Stephane Viau
---
drivers/gpu/drm/msm/hdmi/hdmi.h | 1 -
drivers/gpu/drm/msm/hdmi/hdmi_connector.c | 51 ++-
drivers/gpu/drm/msm/hdmi/hdmi_phy_8960.c | 52
drivers/gpu/drm/msm/hdmi/hdmi_phy_8x60.c | 32 -
driver
This change adds the MDP and HDMI support for msm8x94.
Note that HDMI PHY registers are not being accessed anymore from
the driver.
Signed-off-by: Stephane Viau
---
drivers/gpu/drm/msm/hdmi/hdmi.c | 30 -
drivers/gpu/drm/msm/hdmi/hdmi_bridge.c| 8 +++-
drivers/gpu/drm
ort and won't change the current
functionality.
Stephane Viau (2):
[RFC] drm/msm/hdmi: remove ->reset() from HDMI PHY
drm/msm: Add support for msm8x94
drivers/gpu/drm/msm/hdmi/hdmi.c | 30 ++
drivers/gpu/drm/msm/hdmi/hdmi.h | 1 -
drivers/gpu/drm/msm/hdmi/
Pinctrl support for HDMI needs a small fix before the actual implementation...
Stephane Viau (2):
drm/msm/hdmi: Point to the right struct device
drm/msm/hdmi: Use pinctrl in HDMI driver
Documentation/devicetree/bindings/drm/msm/hdmi.txt | 6 +++
drivers/gpu/drm/msm/hdmi/hdmi_connector.c
Some targets (eg: msm8994) use the pinctrl framework to configure
interface pins. This change adds support for initialization and
pinctrl active/sleep state control for the HDMI driver.
Signed-off-by: Stephane Viau
---
v3:
- Use pins binding handled in driver really_probe() [Ivan]
v2
DRM device's dev (hdmi->dev->dev) points to the mdss_mdp device
handle. Instead, we should get a reference to the mdss_hdmi
handle.
Signed-off-by: Stephane Viau
---
drivers/gpu/drm/msm/hdmi/hdmi_connector.c | 32 +++
1 file changed, 16 insertions(+), 1
That will complete the lists of Alpha + RGB formats.
Signed-off-by: Stephane Viau
---
drivers/gpu/drm/msm/mdp/mdp_format.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/msm/mdp/mdp_format.c
b/drivers/gpu/drm/msm/mdp/mdp_format.c
index f683433..7b0524d 100644
--- a
Some targets (eg: msm8994) use the pinctrl framework to configure
interface pins. This change adds support for initialization and
pinctrl active/sleep state control for the HDMI driver.
Signed-off-by: Stephane Viau
---
v2:
- Add devicetree binding documentation for pinctrl property [Ivan]
- Use
Some targets (eg: msm8994) use the pinctrl framework to configure
interface pins. This change adds support for initialization and
pinctrl active/sleep state control for the HDMI driver.
Signed-off-by: Stephane Viau
---
drivers/gpu/drm/msm/hdmi/hdmi.c | 25
Add the GDSC instances that exist as part of apq8084 MMCC block.
Signed-off-by: Stephane Viau
---
drivers/clk/qcom/Kconfig | 1 +
drivers/clk/qcom/mmcc-apq8084.c | 56 ++-
include/dt-bindings/clock/qcom,mmcc-apq8084.h | 8
3
MDSS HW version is read.
Signed-off-by: Stephane Viau
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c | 8
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h | 1 +
drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c | 20 ++--
drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c | 26
, the
client ID list is passed through the MDP5 config module rather
than using a list of hard-coded enum values.
Signed-off-by: Stephane Viau
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c | 20 ---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h | 1 +
drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c
This change contains the generated header file for the following
change "drm/msm/mdp5: Separate MDP5 domain from MDSS domain".
Signed-off-by: Stephane Viau
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h | 203 +++-
1 file changed, 118 insertions(+), 85
This patch contains the generated header file of the following
change "drm/msm/mdp5: Get SMP client list from mdp5_cfg".
Signed-off-by: Stephane Viau
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h | 41 ++---
1 file changed, 7 insertions(+), 34 deletions(-)
dware mask [pointed by Archit]
Signed-off-by: Stephane Viau
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c | 52 -
1 file changed, 51 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
index 96
This patch set contains a couple modifications of the MDP5 register
description, followed by the MDP hw configuration of the msm8016 and
msm8916 chipsets.
v2: add CTL flush register's hardware mask [pointed by Archit]
Stephane Viau (5):
drm/msm/mdp5: Update headers (introduce MDP5 d
This TODO can now be removed and replaced by the previous patch
"drm/msm/mdp5: Update headers (add CTL flush bits)"
Signed-off-by: Stephane Viau
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c | 11 ---
1 file changed, 11 deletions(-)
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp
Some upcoming targets have more bits to set in CTL_FLUSH registers.
Example: msm8x16 needs to set TIMING1 bit so that some of the
INTF1's interface registers get flushed.
Signed-off-by: Stephane Viau
---
rnndb/mdp/mdp5.xml | 8
1 file changed, 8 insertions(+)
diff --git a/rnnd
Some upcoming targets have more bits to set in CTL_FLUSH
registers.
Example: msm8x16 needs to set TIMING1 bit so that some of the
INTF1's interface registers get flushed.
Signed-off-by: Stephane Viau
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h | 12 ++--
1 file changed, 10 inser
This patchset proposes in a couple of changes (separate generated header)
to remove the temporary defined symbols in the code and place them into
the generated header file.
Stephane Viau (2):
drm/msm/mdp5: Update headers (add CTL flush bits)
drm/msm/mdp5: Remove CTL flush dummy bits
drivers
Prepare for pipeline operation mode configuration, in particular
for DSI and WB modes.
Signed-off-by: Stephane Viau
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h | 68 -
1 file changed, 33 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/msm/mdp/mdp5
INTF_TIMING_ENGINE_EN registers
Signed-off-by: Stephane Viau
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c | 8 +++
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h | 4 ++
drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c | 112 ++--
3 files changed, 75 insertions(+), 49 deletions(-)
diff --git
pipeline as far
as operation mode goes. DSI and WB interfaces will be added
later.
v2: rename macro to mdp5_cfg_intf_is_virtual() [pointed by Archit]
Signed-off-by: Stephane Viau
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h | 4 ++
drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c| 39
).
Signed-off-by: Stephane Viau
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c | 2 +
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h | 7 +-
drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c| 31 ++--
drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c | 247
drivers/gpu/drm/msm
m/msm: Add display configuration for msm8x16" patch set depends on
"drm/msm: preparation for WB/DSI connectors" patch set.
Stephane Viau (4):
drm/msm/mdp5: Update generated header files
drm/msm/mdp5: Enhance operation mode for pipeline configuration
drm/msm/mdp5: Add STAR
From: Beeresh Gopal
To avoid ambiguity rename register
FRAME_SIZE to SSTILE_FRAME_SIZE.
Signed-off-by: Beeresh Gopal
---
rnndb/mdp/mdp4.xml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/rnndb/mdp/mdp4.xml b/rnndb/mdp/mdp4.xml
index 26d1deb..a84f530 100644
--- a/rnndb/mdp/
From: Beeresh Gopal
To avoid ambiguity rename FRAME_SIZE to
SSTILE_FRAME_SIZE
Signed-off-by: Beeresh Gopal
---
drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h | 36 +
1 file changed, 14 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h
Resending a v2 on behalf of Beeresh with comments from Daniel and Rob
addressed.
Beeresh Gopal (2):
drm/msm: update generated headers
drm/msm/mdp4: Support NV12MT format in mdp4
drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h | 36 ---
drivers/gpu/drm/msm/mdp/mdp4/mdp4_
From: Beeresh Gopal
Using fb modifier flag, support NV12MT format in MDP4.
v2:
- rework the modifier's description [Daniel Vetter's comment]
- drop .set_mode_config() callback [Rob Clark's comment]
Signed-off-by: Beeresh Gopal
Signed-off-by: Stephane Viau
---
drivers/gpu/d
, the
client ID list is passed through the MDP5 config module rather
than using a list of hard-coded enum values.
Signed-off-by: Stephane Viau
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c | 20 ---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h | 1 +
drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c
This patch contains the generated header file of the following
change "drm/msm/mdp5: Get SMP client list from mdp5_cfg".
Signed-off-by: Stephane Viau
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h | 41 ++---
1 file changed, 7 insertions(+), 34 deletions(-)
This change contains the generated header file for the following
change "drm/msm/mdp5: Separate MDP5 domain from MDSS domain".
Signed-off-by: Stephane Viau
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h | 203 +++-
1 file changed, 118 insertions(+), 85
This change adds the hw configuration for msm8x16 chipsets in
mdp5_cfg module.
Note that only one external display interface is present in this
configuration (DSI) but has not been enabled yet. It will be enabled
once drm/msm driver supports DSI connectors.
Signed-off-by: Stephane Viau
MDSS HW version is read.
Signed-off-by: Stephane Viau
---
rnndb/mdp/mdp5.xml | 123 +
1 file changed, 67 insertions(+), 56 deletions(-)
diff --git a/rnndb/mdp/mdp5.xml b/rnndb/mdp/mdp5.xml
index db2e15c..aedaa7c 100644
--- a/rnndb/mdp/mdp5.xml
, the
client ID list is passed through the MDP5 config module rather
than using a list of hard-coded enum values.
Signed-off-by: Stephane Viau
---
rnndb/mdp/mdp5.xml | 34 --
1 file changed, 4 insertions(+), 30 deletions(-)
diff --git a/rnndb/mdp/mdp5.xml b/rnndb/mdp
MDSS HW version is read.
Signed-off-by: Stephane Viau
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c | 8
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h | 1 +
drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c | 20 ++--
drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c | 26
This patch set contains a couple modifications of the MDP5 register
description, followed by the MDP hw configuration of the msm8016 and
msm8916 chipsets.
Stephane Viau (5):
drm/msm/mdp5: Update headers (introduce MDP5 domain)
drm/msm/mdp5: Separate MDP5 domain from MDSS domain
drm/msm/mdp5
Up until now, we assume that eDP is tight to intf_0 and HDMI to
intf_3. This information shall actually come from the mdp5_cfg
module since it can change from one chip to another.
v2: rename macro to mdp5_cfg_intf_is_virtual() [pointed by Archit]
Signed-off-by: Stephane Viau
---
drivers/gpu
).
Signed-off-by: Stephane Viau
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c | 2 +
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h | 7 +-
drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c| 31 ++--
drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c | 247
drivers/gpu/drm/msm
pipeline as far
as operation mode goes. DSI and WB interfaces will be added
later.
v2: rename macro to mdp5_cfg_intf_is_virtual() [pointed by Archit]
Signed-off-by: Stephane Viau
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h | 4 ++
drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c| 39
Prepare for pipeline operation mode configuration, in particular
for DSI and WB modes.
Signed-off-by: Stephane Viau
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h | 68 -
1 file changed, 33 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/msm/mdp/mdp5
WB and DSI support are in the pipe and will come out soon. Before that,
we need to prepare the MDP5 driver so we can support these connectors.
v2: rename macro to mdp5_cfg_intf_is_virtual() [pointed by Archit]
Stephane Viau (4):
drm/msm/mdp5: Update generated header files
drm/msm/mdp5
WB and DSI support are in the pipe and will come out soon. Before that, we
need to prepare the MDP5 driver so we can support these connectors.
Stephane Viau (4):
drm/msm/mdp5: Update generated header files
drm/msm/mdp5: Enhance operation mode for pipeline configuration
drm/msm/mdp5: Add
pipeline as far
as operation mode goes. DSI and WB interfaces will be added
later.
Signed-off-by: Stephane Viau
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h | 2 +
drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c| 39 ++---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c | 91
.
Signed-off-by: Stephane Viau
---
rnndb/mdp/mdp5.xml | 67 +++---
1 file changed, 33 insertions(+), 34 deletions(-)
diff --git a/rnndb/mdp/mdp5.xml b/rnndb/mdp/mdp5.xml
index 3c199a1..4d9781c 100644
--- a/rnndb/mdp/mdp5.xml
+++ b/rnndb/mdp/mdp5.xml
Prepare for pipeline operation mode configuration, in particular
for DSI and WB modes.
Signed-off-by: Stephane Viau
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h | 68 -
1 file changed, 33 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/msm/mdp/mdp5
).
Signed-off-by: Stephane Viau
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c | 2 +
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h | 7 +-
drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c| 31 ++--
drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c | 247
drivers/gpu/drm/msm
Up until now, we assume that eDP is tight to intf_0 and HDMI to
intf_3. This information shall actually come from the mdp5_cfg
module since it can change from one chip to another.
Signed-off-by: Stephane Viau
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c | 8 +++
drivers/gpu/drm/msm/mdp/mdp5
Some target have up to 6 layer mixers (LM). Let the xml file
access the last LM's base address.
Signed-off-by: Stephane Viau
---
rnndb/mdp/mdp5.xml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/rnndb/mdp/mdp5.xml b/rnndb/mdp/mdp5.xml
index cd3bf37..eaaec47 100644
when we .atomic_check()/.atomic_flush() on a
disabled CRTC.
A CTL needs to be kept as long as the CRTC is alive. Releasing it
after the last VBlank is safer than in .atomic_flush().
Signed-off-by: Stephane Viau
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c | 26 +++---
1 file cha
The 4th CRTC could not be accessed because of a missing case entry.
Also, only flush registers when a CRTC is enabled (and thus a CTL is allocated).
This shall fix the cursor move issue that Rob mentioned.
Stephane Viau (2):
drm/msm: update generated headers (add 6th lm.base entry)
drm/msm
Some target have up to 6 layer mixers (LM).
Let the header file access the last LM's base address.
Signed-off-by: Stephane Viau
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h | 15 ---
1 file changed, 4 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/msm/mdp/mdp5
s are only present for MDP5. MDP4 is fine.
Signed-off-by: Stephane Viau
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c| 4 ++--
drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c | 6 +++---
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
b/drivers/g
nly *one* FLUSH is called between Vblanks interrupts.
Signed-off-by: Stephane Viau
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
index
In case we request a number of SMP blocks which is lower than
the already reserved blocks, we should not try to allocate a
negative number, but 0 blocks instead.
Signed-off-by: Stephane Viau
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions
Update generated headers, in particular pick up the definitions
for Hardware Cursor support (MDP5).
Signed-off-by: Stephane Viau
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h | 79 +
1 file changed, 79 insertions(+)
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5
From: Beeresh Gopal
This patch implements the hardware accelarated cursor
support for MDP5 platforms.
Signed-off-by: Beeresh Gopal
Signed-off-by: Wentao Xu
Signed-off-by: Stephane Viau
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c | 164 +++
1 file changed, 164
This patch set contains the hardware cursor changes. Split into two, as usual,
in order to separate header file generation from the rest of the code.
Beeresh Gopal (1):
drm/msm/mdp5: Add hardware cursor support
Stephane Viau (1):
drm/msm/mdp5: add register description for HW Cursor support
This patch adds the field description for HW Cursor registers.
Signed-off-by: Stephane Viau
---
rnndb/mdp/mdp5.xml | 45 ++---
1 file changed, 38 insertions(+), 7 deletions(-)
diff --git a/rnndb/mdp/mdp5.xml b/rnndb/mdp/mdp5.xml
index 2e61e05..486e942
Instead of reporting BUG_ON when resources arrays are not
dimensioned correctly, this patch does a dynamic allocation of
these arrays. This is needed for the following patches that add a
regulator for a new target.
Signed-off-by: Stephane Viau
---
drivers/gpu/drm/msm/hdmi/hdmi.c | 28
mdp5_ctl_set_intf()'s second argument should be "int", not "enum mdp5_intf".
The passed in value is "intf", not "intf_id".
Signed-off-by: Stephane Viau
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c | 2 +-
drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.
This change add the regulator/clock configuration for MDP5 v1.3.
This config is close to the one already existing for 8x74, except
that one more regulator is needed (hpd-5v-en).
Signed-off-by: Stephane Viau
---
Documentation/devicetree/bindings/drm/msm/hdmi.txt | 1 +
drivers/gpu/drm/msm/hdmi
In the same idea mdp5_cfg was added, this change allows us to quickly
add new instances, such as apq8084's HDMI in this case.
Signed-off-by: Stephane Viau
---
Documentation/devicetree/bindings/drm/msm/hdmi.txt | 1 +
drivers/gpu/drm/msm/hdmi/hdmi.c
Instead of reporting BUG_ON when resources arrays are not
dimensioned correctly, this patch does a dynamic allocation of
these arrays. This is needed for the following patches that add a
regulator for a new target.
Signed-off-by: Stephane Viau
---
drivers/gpu/drm/msm/hdmi/hdmi.c | 33
ation.
Stephane Viau (3):
drm/msm/hdmi: use dynamic allocation for hdmi resources
drm/msm/hdmi: Add HDMI platform config for apq8084
drm/msm/hdmi: rework hdmi configurations, using dt_match[]
Documentation/devicetree/bindings/drm/msm/hdmi.txt | 2 +
drivers/gpu/drm/msm/hdmi/h
Both MDP4 and MDP5 share some code as far as YUV support is
concerned. This change adds this information and will be followed
by the actual MDP4 and MDP5 YUV support patches.
Signed-off-by: Stephane Viau
---
drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h | 19 --
drivers/gpu/drm/msm/mdp/mdp5
This change adds the NV12 format support for public planes.
Signed-off-by: Stephane Viau
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c | 213 +++---
drivers/gpu/drm/msm/msm_fb.c | 2 +-
2 files changed, 194 insertions(+), 21 deletions(-)
diff --git a
From: Beeresh Gopal
The patch add support for YUV frame format
for MDP4 platform.
Signed-off-by: Beeresh Gopal
Signed-off-by: Stephane Viau
---
drivers/gpu/drm/msm/mdp/mdp4/mdp4_plane.c | 104 +++---
1 file changed, 95 insertions(+), 9 deletions(-)
diff --git a
.
Generated headers are kept in a separate change to ease the
actual driver's code review.
Signed-off-by: Stephane Viau
---
drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h | 44 +
drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h | 153 +--
drivers/gpu/drm/ms
don't have a build based on atomic yet. The change is pretty
similar to MDP5 though.
Rgds,
Stephane.
Beeresh Gopal (1):
drm/msm/mdp4: add YUV format support
Stephane Viau (3):
drm/msm/mdp: add register description for YUV support
drm/msm/mdp: add common YUV information for MDP4/MDP5
dr
Note:
chroma_samp_type can be used by both MDP4 and MDP5, thus
moved to mdp_common.
Signed-off-by: Stephane Viau
---
rnndb/mdp/mdp4.xml | 16
rnndb/mdp/mdp5.xml | 64 +---
rnndb/mdp/mdp_common.xml | 13 ++
3 files
ior of the SMP block. These registers access is now
restricted to the SMP module.
Signed-off-by: Stephane Viau
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c | 28 +++-
drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h | 34 ++---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c | 92 ++--
drivers/g
This patch set updates the SMP config for MDP5, introduces a Config module for
easier platform config update and allows MDP5 driver to use multiple CRTCs as
well as multiple planes (overlay).
Stephane Viau (3):
drm/msm/mdp5: make SMP module dynamically configurable
drm/msm/mdp5: introduce
The hardware configuration modification from a version to another
is quite consequent. Introducing a configuration module
(mdp5_cfg) may make things more clear and easier to access when a
new hardware version comes up.
Signed-off-by: Stephane Viau
---
drivers/gpu/drm/msm/Makefile
MDP5 currently support one single CRTC with its private pipe.
This change allows the configuration of multiple CRTCs with
the possibility to attach several public planes to these CRTCs.
Signed-off-by: Stephane Viau
---
drivers/gpu/drm/msm/Makefile| 1 +
drivers/gpu/drm/msm/mdp
The core clock rate depends on the hw configuration. Once we have
read the hardware revision, we can set the core clock to its
maximum value.
Before then, the clock is set at a rate supported by all MDP5
revisions.
Signed-off-by: Stephane Viau
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c | 9
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