[PATCH v6 1/2] crypto: skcipher AF_ALG - overhaul memory management

The updated memory management is described in the top part of the code. As one benefit of the changed memory management, the AIO and synchronous operation is now implemented in one common function. The AF_ALG operation uses the async kernel crypto API interface for each cipher operation. Thus, the

[PATCH v6 0/2] crypto: AF_ALG memory management fix

Hi Herbert, Changes v6: * port to 4.11-rc1 (a header file was included from upstream) * Limit the RX SGL in an identical fashion as the TX SGL size is limited by adding [skcipher|aead]_readable which is an equivalent to the existing [skcipher|aead]_writable. To ensure that the limit is

[PATCH v6 2/2] crypto: aead AF_ALG - overhaul memory management

The updated memory management is described in the top part of the code. As one benefit of the changed memory management, the AIO and synchronous operation is now implemented in one common function. The AF_ALG operation uses the async kernel crypto API interface for each cipher operation. Thus, the

Re: [PATCH] crypto/nx: Update MAINTAINERS entry for 842 compression

On Sat, Apr 1, 2017 at 1:25 PM, Haren Myneni wrote: > [PATCH] crypto/nx: Update MAINTAINERS entry for 842 compression > > Signed-off-by: Haren Myneni Acked-by: Dan Streetman > > --- > MAINTAINERS | 2 +- > 1 file changed, 1

[PATCH] crypto/nx: Update MAINTAINERS entry for 842 compression

[PATCH] crypto/nx: Update MAINTAINERS entry for 842 compression Signed-off-by: Haren Myneni --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index c265a5f..4cfd225 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@

[RESEND PATCH 0/5] Enable NX 842 compression engine on Power9

Sorry for reposting. Missed to specify dependency - VAS kernel changes. [PATCH 0/5] Enable NX 842 compression engine on Power9 P9 introduces Virtual Accelerator Switchboard (VAS) to communicate with NX 842 engine. icswx function is used to access NX before. On powerNV systems, NX-842 driver

[PATCH 5/5] crypto/nx: Add P9 NX specific error codes for 842 engine

[PATCH 5/5] crypto/nx: Add P9 NX specific error codes for 842 engine This patch adds changes for checking P9 specific 842 engine error codes. These errros are reported in co-processor status block (CSB) for failures. Signed-off-by: Haren Myneni ---

[PATCH 4/5] crypto/nx: Add P9 NX support for 842 compression engine.

[PATCH 4/5] crypto/nx: Add P9 NX support for 842 compression engine. This patch adds P9 NX support for 842 compression engine. Virtual Accelerator Switchboard (VAS) is used to access 842 engine on P9. For each NX engine per chip, setup receive window using vas_rx_win_open() which configures

[PATCH 3/5] crypto/nx: Create nx842_delete_coproc function

[PATCH 3/5] crypto/nx: Create nx842_delete_coproc function Move deleting coprocessor info upon exit or failure to nx842_delete_coproc(). Signed-off-by: Haren Myneni --- drivers/crypto/nx/nx-842-powernv.c | 25 - 1 file changed, 12 insertions(+), 13

[PATCH 2/5] crypto/nx: Create nx842_cfg_crb function

[PATCH 2/5] crypto/nx: Create nx842_cfg_crb function Configure CRB is moved to nx842_cfg_crb() so that it can be used for icswx function and VAS function which will be added later. Signed-off-by: Haren Myneni --- drivers/crypto/nx/nx-842-powernv.c | 57

[PATCH 1/5] crypto/nx: Rename nx842_powernv_function as icswx function

[PATCH 1/5] crypto/nx: Rename nx842_powernv_function as icswx function nx842_powernv_function is points to nx842_icswx_function and will be point to VAS function which will be added later for P9 NX support. Signed-off-by: Haren Myneni --- drivers/crypto/nx/nx-842-powernv.c |

[PATCH 0/5] crypto/nx: Enable NX 842 compression engine on Power9

[PATCH 0/5] crypto/nx: Enable NX 842 compression engine on Power9 P9 introduces Virtual Accelerator Switchboard (VAS) to communicate with NX 842 engine. icswx function is used to access NX before. On powerNV systems, NX-842 driver invokes VAS functions for configuring RxFIFO (receive window) per

Re: [PATCH 1/6] virtio: wrap find_vqs

On Wed 29 Mar 13:48 PDT 2017, Michael S. Tsirkin wrote: > We are going to add more parameters to find_vqs, let's wrap the call so > we don't need to tweak all drivers every time. > > Signed-off-by: Michael S. Tsirkin Acked-by: Bjorn Andersson

Re: [PATCH v4] crypto: gf128mul - define gf128mul_x_* in gf128mul.h

Never mind, Gmail is confusing me... there is indeed "v4" in the subject :) O.M. 2017-04-01 17:19 GMT+02:00 Ondrej Mosnáček : > Oops, sorry, wrong prefix... > > 2017-04-01 17:17 GMT+02:00 Ondrej Mosnacek : >> The gf128mul_x_ble function is currently

Re: [PATCH v4] crypto: gf128mul - define gf128mul_x_* in gf128mul.h

Oops, sorry, wrong prefix... 2017-04-01 17:17 GMT+02:00 Ondrej Mosnacek : > The gf128mul_x_ble function is currently defined in gf128mul.c, because > it depends on the gf128mul_table_be multiplication table. > > However, since the function is very small and only uses two

[PATCH v4] crypto: gf128mul - define gf128mul_x_* in gf128mul.h

The gf128mul_x_ble function is currently defined in gf128mul.c, because it depends on the gf128mul_table_be multiplication table. However, since the function is very small and only uses two values from the table, it is better for it to be defined as inline function in gf128mul.h. That way, the

Re: [PATCH v3] crypto: gf128mul - define gf128mul_x_* in gf128mul.h

2017-04-01 5:44 GMT+02:00 Eric Biggers : > Also, I realized that for gf128mul_x_lle() now that we aren't using the table > we > don't need to shift '_tt' but rather can use the constant 0xe100: > > /* equivalent to (u64)gf128mul_table_le[(b << 7) & 0xff]

[PATCH] crypto: AF_ALG: handle 0 lengths in af_alg_make_sg

Hi Herbert, If you concur with the patch, I think it should go to 4.11 as well as to stable. Ciao Stephan ---8<--- The function af_alg_make_sg converts user-provided IOVECs into an SGL. Thus it operates directly on the user-space provided number of IOVECs. When user space provides 0 for the