t; some cases as it applies to all entries. 'contains' is the correct schema
> to use in the case of multiple entries.
>
> Cc: Herbert Xu
> Cc: "David S. Miller"
> Cc: Maxime Ripard
> Cc: Chen-Yu Tsai
> Cc: Eric Anholt
> Cc: Nicolas Saenz Julienne
>
-18,7 +18,7 @@ properties:
> > const: 1
> >
> >compatible:
> > -const: allwinner,sun9i-a80-usb-clocks
> > +const: allwinner,sun9i-a80-usb-clks
>
> Should the file name change too?
Ideally yes, and with that change
Acked-by: Maxime Ripard
Maxime
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On Tue, Sep 08, 2020 at 08:15:56AM +0200, Maxime Ripard wrote:
> On Mon, Sep 07, 2020 at 07:54:37PM +0200, Corentin Labbe wrote:
> > When adding allwinner,sun8i-a33-crypto, I forgot to add that it needs reset.
> > Furthermore, there are no need to use items to list only one co
On Mon, Sep 07, 2020 at 06:24:56PM +0200, Martin Cerveny wrote:
> Add support for crypto engine (sun4i-ss) for Allwinner V3s.
> Functionality like A33 so add only compatible and enable
> in device tree.
>
> Regards.
Applied, thanks
Maxime
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ngs: crypto: add new compatible for A33 SS")
> Signed-off-by: Corentin Labbe
Acked-by: Maxime Ripard
Thanks!
Maxime
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On Thu, Sep 03, 2020 at 04:54:45PM +0200, Corentin Labbe wrote:
> When adding allwinner,sun8i-a33-crypto, I forgot to add that it needs reset.
> Furthermore, there are no need to use items to list only one compatible
> in compatible list.
>
> Fixes: f81547ba7a98 ("dt-bindings: crypto: add new comp
On Wed, Sep 02, 2020 at 11:17:16AM +0200, Corentin Labbe wrote:
> When adding allwinner,sun8i-a33-crypto, I forgot to add that it needs reset.
> Furthermore, there are no need to use items to list only one compatible
> in compatible list.
>
> Fixes: f81547ba7a98 ("dt-bindings: crypto: add new comp
On Tue, Sep 01, 2020 at 12:57:19PM +0200, Corentin Labbe wrote:
> On Tue, Sep 01, 2020 at 11:32:49AM +0200, Maxime Ripard wrote:
> > On Mon, Aug 31, 2020 at 09:30:59AM +0200, Martin Cerveny wrote:
> > > Like A33 "sun4i-ss" has a difference, it give SHA1 digest
>
On Mon, Aug 31, 2020 at 09:31:00AM +0200, Martin Cerveny wrote:
> V3s contains crypto engine that is compatible with "sun4i-ss".
>
> Tested-by: Martin Cerveny
> Signed-off-by: Martin Cerveny
> ---
> arch/arm/boot/dts/sun8i-v3s.dtsi | 10 ++
> 1 file changed, 10 insertions(+)
>
> diff -
On Mon, Aug 31, 2020 at 09:30:59AM +0200, Martin Cerveny wrote:
> Like A33 "sun4i-ss" has a difference, it give SHA1 digest
> directly in BE. So add new compatible.
>
> Tested-by: Martin Cerveny
The Tested-by tag is for the other developpers. You're very much
expected to have tested your patch b
On Tue, Jun 23, 2020 at 05:00:32PM +0200, Markus Elfring wrote:
> >>> Fix this by …
> >>
> >> Please replace the beginning of this sentence with the tag “Fixes”.
> >> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/process/submitting-patches.rst?id=625d3449788f
On Mon, Jun 22, 2020 at 07:50:08PM +0200, Markus Elfring wrote:
> > Fix this by …
>
> Please replace the beginning of this sentence with the tag “Fixes”.
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/process/submitting-patches.rst?id=625d3449788f8556909678
TRA_TESTS
> and tested on:
> sun8i-a83t-bananapi-m3
> sun9i-a80-cubieboard4
>
> This serie is based on top of the "crypto: add sun8i-ce driver for
> Allwinner crypto engine" serie.
For the crypto part,
Acked-by: Maxime Ripard
I'll apply patches 3 and 4 once Herbert will have merged the patches 1 and 2
Thanks!
Maxime
e-h64
> sun8i-h2-plus-libretech-all-h3-cc
> sun8i-h2-plus-orangepi-r1
> sun8i-h2-plus-orangepi-zero
> sun8i-h3-libretech-all-h3-cc
> sun8i-h3-orangepi-pc
> sun8i-r40-bananapi-m2-ultra
for the drivers/crypto part
Acked-by: Maxime Ripard
I'll merge the dt and defconfig bits wh
On Thu, Oct 10, 2019 at 08:23:19PM +0200, Corentin Labbe wrote:
> + ce->reset = devm_reset_control_get_optional(&pdev->dev, "bus");
> + if (IS_ERR(ce->reset)) {
> + if (PTR_ERR(ce->reset) == -EPROBE_DEFER)
> + return PTR_ERR(ce->reset);
> + dev_er
Hi,
On Tue, Oct 01, 2019 at 08:41:32PM +0200, Corentin Labbe wrote:
> + /* CTS and recent CE (H6) need length in bytes, in word otherwise */
> + if (ce->variant->model == CE_v2)
> + cet->t_dlen = areq->cryptlen;
It's entirely redundant withe the compatible.
How about using so
On Tue, Oct 01, 2019 at 08:41:35PM +0200, Corentin Labbe wrote:
> The Crypto Engine is a hardware cryptographic accelerator that supports
> many algorithms.
> It could be found on most Allwinner SoCs.
>
> This patch enables the Crypto Engine on the Allwinner H3 SoC Device-tree.
>
> Signed-off-by: C
On Tue, Oct 01, 2019 at 08:41:33PM +0200, Corentin Labbe wrote:
> This patch adds documentation for Device-Tree bindings for the
> Crypto Engine cryptographic accelerator driver.
>
> Signed-off-by: Corentin Labbe
> ---
> .../bindings/crypto/allwinner,sun8i-ce.yaml | 92 +++
> 1
on PM in the future.
>
> Signed-off-by: Corentin Labbe
Acked-by: Maxime Ripard
Thanks!
Maxime
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Hi,
On Thu, Sep 19, 2019 at 07:10:35AM +0200, Corentin Labbe wrote:
> This patch enables power management on the Security System.
>
> Signed-off-by: Corentin Labbe
> ---
> drivers/crypto/sunxi-ss/sun4i-ss-cipher.c | 9 +++
> drivers/crypto/sunxi-ss/sun4i-ss-core.c | 94 +++
On Thu, Sep 12, 2019 at 09:37:17PM +0100, Chen-Yu Tsai wrote:
> On Thu, Sep 12, 2019 at 9:33 PM Maxime Ripard wrote:
> > On Thu, Sep 12, 2019 at 09:26:27PM +0100, Chen-Yu Tsai wrote:
> > > > >
> > > > > clock-names:
> > > > > items:
>
On Fri, Sep 13, 2019 at 10:15:55AM +0200, Corentin Labbe wrote:
> On Sat, Sep 07, 2019 at 07:03:53AM +0300, Maxime Ripard wrote:
> > On Fri, Sep 06, 2019 at 08:45:51PM +0200, Corentin Labbe wrote:
> > > This patch adds the new allwinner crypto configs to sunxi_defconfig
> &g
On Thu, Sep 12, 2019 at 09:26:27PM +0100, Chen-Yu Tsai wrote:
> > >
> > > clock-names:
> > > items:
> > > - const: ahb
> > > - const: mod
> > > - const: mbus
> >
> > And here as well
> >
> > Something I missed earlier though was that we've tried to unify as
> > much as possi
Hi Corentin,
On Wed, Sep 11, 2019 at 08:31:58PM +0200, Corentin Labbe wrote:
> On Sat, Sep 07, 2019 at 07:01:16AM +0300, Maxime Ripard wrote:
> > On Fri, Sep 06, 2019 at 08:45:45PM +0200, Corentin Labbe wrote:
> > > This patch adds documentation for Device-Tree bindings fo
Hi,
Le mer. 11 sept. 2019 à 13:46, Corentin Labbe
a écrit :
>
> This patch enables power management on the Security System.
>
> Signed-off-by: Corentin Labbe
> ---
> drivers/crypto/sunxi-ss/sun4i-ss-cipher.c | 5 +++
> drivers/crypto/sunxi-ss/sun4i-ss-core.c | 42 ++-
> 2
dev_err(ss->dev, "Cannot deassert reset control\n");
> + goto err_enable;
> + }
> + }
> + return err;
And after each block here?
With that fixed:
Acked-by: Maxime Ripard
Thanks!
Maxime
On Mon, Sep 09, 2019 at 03:19:06PM +0200, Corentin Labbe wrote:
> On Mon, Sep 09, 2019 at 01:38:37PM +0200, Maxime Ripard wrote:
> > On Sat, Sep 07, 2019 at 09:04:08PM +0200, Corentin Labbe wrote:
> > > > Also, I'm not sure what is the point of having the clocks names b
ion(&ce->chanlist[i].complete);
> > > + mutex_init(&ce->chanlist[i].lock);
> > > +
> > > + ce->chanlist[i].engine = crypto_engine_alloc_init(ce->dev,
> > > true);
> > > + if (!ce->chanlist[i].engine) {
> > > + dev_err(ce->dev, "Cannot allocate engine\n");
> > > + i--;
> > > + goto error_engine;
> > > + }
> > > + err = crypto_engine_start(ce->chanlist[i].engine);
> > > + if (err) {
> > > + dev_err(ce->dev, "Cannot start engine\n");
> > > + goto error_engine;
> > > + }
> > > + ce->chanlist[i].tl = dma_alloc_coherent(ce->dev,
> > > + sizeof(struct ce_task),
> > > + &ce->chanlist[i].t_phy,
> > > + GFP_KERNEL);
> > > + if (!ce->chanlist[i].tl) {
> > > + dev_err(ce->dev, "Cannot get DMA memory for task %d\n",
> > > + i);
> > > + err = -ENOMEM;
> > > + goto error_engine;
> > > + }
> > > + }
> >
> > All this initialization should be done before calling
> > request_irq. You're using some of those fields in your handler.
>
> No interrupt could fire, since algorithms are still not registred.
That's not true. Spurious interrupts are a thing, the engine could
have been left in a weird state by the bootloader / kexec / reboot
with some pending interrupts, etc.
You have registered that handler already, you should expect it to be
called at any point in time.
Maxime
--
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Embedded Linux and Kernel engineering
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her.base.cra_name);
> + err =
> crypto_register_skcipher(&ce_algs[i].alg.skcipher);
> + if (err) {
> + dev_err(ce->dev, "Fail to register %s\n",
> + ce_algs[i].alg.skcipher.base.cra_name);
> + ce_algs[i].ce = NULL;
> + goto error_alg;
> + }
> + break;
> + default:
> + dev_err(ce->dev, "ERROR: tryed to register an unknown
> algo\n");
> + }
> + }
> +
> + return 0;
> +error_alg:
> + i--;
> + for (; i >= 0; i--) {
> + switch (ce_algs[i].type) {
> + case CRYPTO_ALG_TYPE_SKCIPHER:
> + if (ce_algs[i].ce)
> +
> crypto_unregister_skcipher(&ce_algs[i].alg.skcipher);
> + break;
> + }
> + }
> +#ifdef CONFIG_CRYPTO_DEV_SUN8I_CE_DEBUG
> +error_debugfs:
> + debugfs_remove_recursive(ce->dbgfs_dir);
> +#endif
> + i = ce->variant->maxflow;
> +error_engine:
> + while (i >= 0) {
> + crypto_engine_exit(ce->chanlist[i].engine);
> + if (ce->chanlist[i].tl)
> + dma_free_coherent(ce->dev, sizeof(struct ce_task),
> + ce->chanlist[i].tl,
> + ce->chanlist[i].t_phy);
> + i--;
> + }
> +error_flow:
> + reset_control_assert(ce->reset);
> +error_clk:
> + for (i = 0; i < CE_MAX_CLOCKS; i++)
> + clk_disable_unprepare(ce->ceclks[i]);
> + return err;
> +}
So that function takes around 200-250 LoC, this is definitely too
much and should be split into multiple functions.
Maxime
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NLS_CODEPAGE_437=y
> CONFIG_NLS_ISO8859_1=y
> CONFIG_PRINTK_TIME=y
> CONFIG_DEBUG_FS=y
> +CONFIG_CRYPTO_DEV_ALLWINNER=y
> +CONFIG_CRYPTO_DEV_SUN8I_CE=y
> CONFIG_CRYPTO_DEV_SUN4I_SS=y
> --
> 2.21.0
>
--
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Embedded Linux and Kernel engineering
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0 {
> + compatible = "allwinner,sun50i-a64-crypto";
> + reg = <0x01c15000 0x1000>;
> + interrupts = ;
> + interrupt-names = "ce_ns";
You didn't document that property
Maxime
--
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resets = <&ccu RST_BUS_CE>;
> + reset-names = "ahb";
> + status = "okay";
The driver will probe if status is not declared, so if you want it
always enabled you should simply remove status
Maxime
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Kconfig | 2 ++
> drivers/crypto/Makefile | 1 +
> drivers/crypto/allwinner/Kconfig | 6 ++
I guess it would make sense to move the sun4i driver there too?
Maxime
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t: mod
> +
> + resets:
> +maxItems: 1
> +
> + reset-names:
> +const: ahb
This prevents the usage of the additionalProperties property, which
you should really use.
What you can do instead is moving the clocks and clock-names
description under properties, with a minItems of 2 and a maxItems of
3. Then you can restrict the length of that property to either 2 or 3
depending on the case here.
Maxime
--
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The older Allwinner SoCs have a crypto engine that is supported in Linux,
with a matching Device Tree binding.
Now that we have the DT validation in place, let's convert the device tree
bindings for that controller over to a YAML schemas.
Signed-off-by: Maxime Ripard
---
.../crypto/allw
On Tue, Jun 20, 2017 at 01:45:36PM +0200, Corentin Labbe wrote:
> On Tue, Jun 20, 2017 at 11:59:47AM +0200, Maxime Ripard wrote:
> > Hi,
> >
> > On Tue, Jun 20, 2017 at 10:58:19AM +0200, Corentin Labbe wrote:
> > > The Security System have a PRNG, thi
t; #define SS_RXFIFO_EMP_INT_ENABLE (1 << 2)
> #define SS_TXFIFO_AVA_INT_ENABLE (1 << 0)
>
> +#define SS_SEED_LEN (192 / 8)
> +#define SS_DATA_LEN (160 / 8)
> +
> struct sun4i_ss_ctx {
> void __iomem *base;
> int irq;
> @@ -136,6 +140,7 @@ struct sun4i_ss_ctx {
> struct device *dev;
> struct resource *res;
> spinlock_t slock; /* control the use of the device */
> + u32 seed[SS_SEED_LEN / 4];
Shouldn't you define SS_SEED_LEN in bits, and then use either
BITS_PER_BYTE and BITS_PER_LONG so that it's obvious what you're doing
?
And you could also make that variable defined based on the option,
otherwise you'll always allocate that array, even if you're not using
it.
Maxime
--
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On Thu, Jun 01, 2017 at 09:39:05PM +0200, Antoine Tenart wrote:
> Add SoC specific compatibles for all sunXi crypto nodes, in addition to
> the one already used (allwinner,sun4i-a10-crypto).
>
> Signed-off-by: Antoine Tenart
Applied, thanks!
Maxime
--
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thanks!
Maxime
--
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that if we ever
need to fix something in there we don't have to update our DT.
Thanks!
Maxime
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d it?)
It probably shouldn't.
The AHB clock is shared by most of the drivers, some of them actually
using that clock to generate their signals.
You would have to unbreak all those drivers first, which is probably
not needed at all. I haven't seen a case where a block had a module
cloc
On Tue, Oct 25, 2016 at 07:38:55AM +0200, LABBE Corentin wrote:
> On Mon, Oct 24, 2016 at 10:10:20PM +0200, Maxime Ripard wrote:
> > On Sat, Oct 22, 2016 at 03:53:28PM +0200, Corentin Labbe wrote:
> > > Since SID's content is constant over reboot,
> >
> > That&
ss.
And I don't think that's true either. A constant entropy provider will
not add any entropy, but will not remove any, would it?
Maxime
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On Tue, Dec 22, 2015 at 12:27:45PM +, Andre Przywara wrote:
> The length parameter in this dev_dbg() call is actually a size_t,
> so use the proper type to avoid warnings when compiling for 64-bit
> architectures.
>
> Signed-off-by: Andre Przywara
Acked-by: Maxime Ripard
s.
Commit 8996eafdcbad ('crypto: ahash - ensure statesize is non-zero')
made impossible to load them without giving statesize. This patch
specifiy statesize for sha1 and md5.
Fixes: 6298e948215f ("crypto: sunxi-ss - Add Allwinner Security System crypto
accelerator")
""&
On Fri, Nov 06, 2015 at 12:56:39PM +0800, Herbert Xu wrote:
> On Thu, Nov 05, 2015 at 08:07:19AM -0800, Maxime Ripard wrote:
> >
> > On Thu, Nov 05, 2015 at 08:48:57AM +0100, LABBE Corentin wrote:
> > > sun4i-ss implementaton of md5/sha1 is via ahash algorithms.
&g
d-off-by: LABBE Corentin
> Cc: sta...@vger.kernel.org
Please also add a Fixes tag (and the stable version it applies to).
Thanks!
Maxime
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todo
isn't assigned to anything.
I'm not sure whether initializing todo to 0 is the right thing to do
though. Corentin?
Maxime
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On Tue, Jul 21, 2015 at 08:50:14PM +0800, Herbert Xu wrote:
> On Tue, Jul 21, 2015 at 02:38:47PM +0200, Maxime Ripard wrote:
> > I thought you needed at least my Acked-by for that, but
> > whatever... How are we supposed to handle subsequent DT patches that
> > should be m
On Mon, Jul 20, 2015 at 04:20:57PM +0800, Herbert Xu wrote:
> On Mon, Jul 20, 2015 at 10:18:36AM +0200, Maxime Ripard wrote:
> > On Mon, Jul 20, 2015 at 04:10:50PM +0800, Herbert Xu wrote:
> > > On Fri, Jul 17, 2015 at 04:39:37PM +0200, LABBE Corentin wrote:
> > > >
out precisions
> > - A80 and A83T datasheet speak about a security system with more functions
> > (SHA224/SHA256/RSA/CRC), they will be supported in a separate driver.
>
> All applied. Thanks a lot!
All applied, DT bits included?
Maxime
--
Maxime Ripard, Free Electro
CB mode with 128/196/256bits keys.
> - DES and 3DES block cipher in CBC/ECB mode
>
> Signed-off-by: LABBE Corentin
There's still a number of style issues.
Make sure to run checkpatch with the --strict option, and fix
everything that's reported.
Maxime
--
Maxime Ripard
eave the other scenarios for other dmaengine
> maintainers to jump in an implement?
From my limited understanding of RAID and PQ computations, it would be
3 with a twist.
Our hardware controller supports xor and PQ, but the checks and
recovering data is not supported (we're not able to offload async_mult
and async_sum_product).
Maxime
--
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Embedded Linux, Kernel and Android engineering
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On Mon, May 18, 2015 at 10:06:55AM -0700, Dan Williams wrote:
> On Mon, May 18, 2015 at 2:14 AM, Maxime Ripard
> wrote:
> > Hi Dan,
> >
> > On Wed, May 13, 2015 at 09:00:46AM -0700, Dan Williams wrote:
> >> On Wed, May 13, 2015 at 2:17 AM, Maxime
Hi Dan,
On Wed, May 13, 2015 at 09:00:46AM -0700, Dan Williams wrote:
> On Wed, May 13, 2015 at 2:17 AM, Maxime Ripard
> wrote:
> > Hi Dan,
> >
> > On Tue, May 12, 2015 at 09:05:41AM -0700, Dan Williams wrote:
> >> On Tue, May 12, 2015 at 8:37 AM, Max
gt; +- clock-names : Name of the functional clock, should be "ahb" and "mod".
And we usually have an example after too.
Thanks!
Maxime
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On Fri, Apr 17, 2015 at 05:01:55PM +0200, Gregory CLEMENT wrote:
> On 17/04/2015 16:50, Maxime Ripard wrote:
> > On Fri, Apr 17, 2015 at 04:40:43PM +0200, Gregory CLEMENT wrote:
> >> Hi Maxime,
> >>
> >> On 17/04/2015 16:32, Maxime Ripard wrote:
> >&
On Fri, Apr 17, 2015 at 04:40:43PM +0200, Gregory CLEMENT wrote:
> Hi Maxime,
>
> On 17/04/2015 16:32, Maxime Ripard wrote:
> > On Fri, Apr 17, 2015 at 04:19:22PM +0200, Boris Brezillon wrote:
> >> Hi Gregory,
> >>
> >> On Fri, 17 Apr 2015 15:01:01 +0200
g new
> > >> compatible strings for the kirkwood, dove and orion platforms, and I'm
> > >> sure sure this is a good idea.
> > > ^ not
> > >
> > >> Do you have any ideas ?
> >
> > You use devm_ioremap_resource() in th
uot;allwinner,sun7i-a20-crypto";
> + reg = <0x01c15000 0x1000>;
> + interrupts = <0 86 4>;
Please use the GIC's define here.
Thanks,
Maxime
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On Thu, Nov 06, 2014 at 10:32:18PM +0800, Herbert Xu wrote:
> On Thu, Nov 06, 2014 at 03:26:33PM +0100, Maxime Ripard wrote:
> >
> > But you still haven't explain why the driver, while it doesn't handle
> > the user space buffer at any time, should be worried that
On Mon, Nov 03, 2014 at 06:35:28PM +0800, Herbert Xu wrote:
> On Mon, Nov 03, 2014 at 10:34:46AM +0100, Maxime Ripard wrote:
> > What I mean is that since you are saying that drivers should do the
> > kmap themselves, then *all* of the drivers are broken if they are not
> >
On Fri, Oct 31, 2014 at 06:05:22PM +0800, Herbert Xu wrote:
> On Fri, Oct 31, 2014 at 10:57:06AM +0100, Maxime Ripard wrote:
> >
> > On a 3.18-rc2 kernel:
> >
> > $ git grep kmap -- crypto/
> > crypto/ahash.c: walk->data
On Fri, Oct 31, 2014 at 04:18:03PM +0800, Herbert Xu wrote:
> On Fri, Oct 31, 2014 at 09:13:23AM +0100, Maxime Ripard wrote:
> >
> > I don't understand here. Why would other drivers *not* being affected?
> >
> > If the scatter list passed by AF_ALG can be in highme
On Fri, Oct 31, 2014 at 03:20:30PM +0800, Herbert Xu wrote:
> On Thu, Oct 30, 2014 at 06:19:33PM +0100, Maxime Ripard wrote:
> >
> > > With AF_ALG and cryptodev, the SG is in highmem. Verified with some
> > > PageHighMem().
> >
> > Then fix AF_ALG and cryp
On Fri, Oct 24, 2014 at 08:52:26PM +0200, Corentin LABBE wrote:
> On 10/21/14 21:11, Maxime Ripard wrote:
> > Hi Corentin,
> >
> > Thanks for resending it.
> >
> > On Sun, Oct 19, 2014 at 04:16:22PM +0200, LABBE Corentin wrote:
> >> Add support for the
We are removing the dmaengine_device_control API, that shouldn't even have been
exposed in the first place. Change the callers to use the proper API.
Signed-off-by: Maxime Ripard
---
drivers/crypto/ux500/cryp/cryp_core.c | 4 ++--
drivers/crypto/ux500/hash/hash_core.c | 2 +-
2 files chang
Hi Corentin,
Thanks for resending it.
On Sun, Oct 19, 2014 at 04:16:22PM +0200, LABBE Corentin wrote:
> Add support for the Security System included in Allwinner SoC A20.
> The Security System is a hardware cryptographic accelerator that support
> AES/MD5/SHA1/DES/3DES/PRNG algorithms.
>
> Sign
clude
> +#include
> +
> +#define SS_CTL0x00
> +#define SS_KEY0 0x04
> +#define SS_KEY1 0x08
> +#define SS_KEY2 0x0C
> +#define SS_KEY3 0x10
> +#define SS_KEY4 0x14
> +#define SS_KEY5 0x18
> +#defin
On Sat, Jul 12, 2014 at 02:59:12PM +0200, LABBE Corentin wrote:
> This patch adds documentation for Device-Tree bindings for the Security
> System cryptographic accelerator driver.
>
> Signed-off-by: LABBE Corentin
Acked-by: Maxime Ripard
Thanks!
Maxime
--
Maxime Ripard, Fr
gt; > AES/MD5/SHA1/DES/3DES/PRNG algorithms.
> >
> > Signed-off-by: LABBE Corentin
>
> This is essentially a synchronous driver, no? If so please
> switch to the blkcipher/shash interface.
The exact opposite has been asked for during v1's review...
Maxime
--
Maxim
ecify all the SoCs for which
> > given compatible string can be used for this IP anyway, because there is
> > usually no other source of information about this available (except
> > directly comparing two datasheets...).
>
> Better get the DT stuff correctly right from the start.
uot;allwinner,sun7i-crypto"
> would
> be a better string ?
No. sun7i-a20-crypto is perfectly fine, and the pattern is used for
all the IPs. sun7i is the SoC family, A20 the actual SoC. In the A20
case, they're equivalent, it's not the case for other Allwinner
SoCs. And I definitely prefer consistency over plain mess. You might
see it differently, but that's not going to change.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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