From: Thor Thayer
Add the device tree entries needed to support the Altera SD/MMC
FIFO buffer EDAC on the Arria10 chip.
Signed-off-by: Thor Thayer
Acked-by: Dinh Nguyen
---
v2 No change
---
arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts | 12
1 file changed, 12 insertions(+
From: Thor Thayer
Add the SD/MMC FIFO EDAC module which is a dual-port RAM as
opposed to the other Arria10 peripheral's single port RAM FIFOs.
Thor Thayer (3):
Documentation: dt: socfpga: Add Arria10 SD-MMC EDAC binding
EDAC, altera: Add Arria10 SD-MMC EDAC support
ARM: dts: Add Arria10 SD
From: Thor Thayer
Add Altera Arria10 SD-MMC FIFO memory EDAC support. The SD-MMC
is a dual port RAM implementation which is different than any
of the other peripherals and therefore requires additional code.
Signed-off-by: Thor Thayer
---
v2 Cleanup PortB initialization by moving device tree s
From: Thor Thayer
Add the device tree bindings needed to support the Altera SD-MMC
FIFO buffers EDAC on the Arria10 chip.
Signed-off-by: Thor Thayer
Acked-by: Rob Herring
---
v2 No change
---
.../bindings/arm/altera/socfpga-eccmgr.txt | 19 +++
1 file changed, 19 in
From: Thor Thayer
Add the device tree entries needed to support the Altera SD/MMC
FIFO buffer EDAC on the Arria10 chip.
Signed-off-by: Thor Thayer
---
arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/socfpga
From: Thor Thayer
This patch series adds the SD/MMC FIFO EDAC module which is a dual-port
RAM as opposed to the other Arria10 peripheral's single port RAM FIFOs.
Thor Thayer (3):
Documentation: dt: socfpga: Add Arria10 SD-MMC EDAC binding
EDAC, altera: Add Arria10 SD-MMC EDAC support
ARM:
From: Thor Thayer
Add the device tree bindings needed to support the Altera SD-MMC
FIFO buffers EDAC on the Arria10 chip.
Signed-off-by: Thor Thayer
---
.../bindings/arm/altera/socfpga-eccmgr.txt | 19 +++
1 file changed, 19 insertions(+)
diff --git a/Documentation/d
From: Thor Thayer
Add Altera Arria10 SD-MMC FIFO memory EDAC support. The SD-MMC
is a dual port RAM implementation which is different than any
of the other peripherals and therefore requires additional code.
Signed-off-by: Thor Thayer
---
drivers/edac/Kconfig |7 ++
drivers/edac/alte
From: Thor Thayer
Add the device tree bindings needed to support the Altera NAND
FIFO buffers EDAC on the Arria10 chip.
Signed-off-by: Thor Thayer
---
.../bindings/arm/altera/socfpga-eccmgr.txt | 32
1 file changed, 32 insertions(+)
diff --git a/Documentation/de
From: Thor Thayer
Add Altera Arria10 QSPI FIFO memory EDAC support.
Signed-off-by: Thor Thayer
---
drivers/edac/Kconfig |7 +++
drivers/edac/altera_edac.c | 34 +-
2 files changed, 40 insertions(+), 1 deletion(-)
diff --git a/drivers/edac/Kconfi
From: Thor Thayer
Add the device tree bindings needed to support the Altera QSPI
FIFO buffer EDAC on the Arria10 chip.
Signed-off-by: Thor Thayer
---
.../bindings/arm/altera/socfpga-eccmgr.txt | 16
1 file changed, 16 insertions(+)
diff --git a/Documentation/devicet
From: Thor Thayer
Add Altera Arria10 USB FIFO memory EDAC support.
Signed-off-by: Thor Thayer
---
drivers/edac/Kconfig |7 +++
drivers/edac/altera_edac.c | 34 +-
2 files changed, 40 insertions(+), 1 deletion(-)
diff --git a/drivers/edac/Kconfig
From: Thor Thayer
This patch series adds the NAND, DMA, USB and QSPI FIFO EDAC modules.
Thor Thayer (10):
Documentation: dt: socfpga: Add Arria10 NAND EDAC binding
Documentation: dt: socfpga: Add Arria10 DMA EDAC binding
Documentation: dt: socfpga: Add Arria10 USB EDAC binding
Documentat
From: Thor Thayer
Add the device tree bindings needed to support the Altera USB
FIFO buffer EDAC on the Arria10 chip.
Signed-off-by: Thor Thayer
---
.../bindings/arm/altera/socfpga-eccmgr.txt | 15 +++
1 file changed, 15 insertions(+)
diff --git a/Documentation/devicetre
From: Thor Thayer
Add the device tree entries needed to support the Altera USB
FIFO buffer EDAC on the Arria10 chip.
Signed-off-by: Thor Thayer
---
arch/arm/boot/dts/socfpga_arria10.dtsi |8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi
b/ar
From: Thor Thayer
Add Altera Arria10 NAND FIFO memory EDAC support.
Signed-off-by: Thor Thayer
---
drivers/edac/Kconfig |7 +++
drivers/edac/altera_edac.c | 34 +-
2 files changed, 40 insertions(+), 1 deletion(-)
diff --git a/drivers/edac/Kconfi
From: Thor Thayer
Add the device tree entries needed to support the Altera DMA
FIFO buffer EDAC on the Arria10 chip.
Signed-off-by: Thor Thayer
---
arch/arm/boot/dts/socfpga_arria10.dtsi |8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi
b/ar
From: Thor Thayer
Add Altera Arria10 DMA FIFO memory EDAC support.
Signed-off-by: Thor Thayer
---
drivers/edac/Kconfig |7 +++
drivers/edac/altera_edac.c | 34 +-
2 files changed, 40 insertions(+), 1 deletion(-)
diff --git a/drivers/edac/Kconfig
From: Thor Thayer
Add the device tree bindings needed to support the Altera DMA
FIFO buffer EDAC on the Arria10 chip.
Signed-off-by: Thor Thayer
---
.../bindings/arm/altera/socfpga-eccmgr.txt | 16
1 file changed, 16 insertions(+)
diff --git a/Documentation/devicetr
From: Thor Thayer
In preparation for additional memory module ECCs, the IRQ and
check_deps() functions are being made available to all the memory
buffers. Move them outside of the OCRAM only area.
Signed-off-by: Thor Thayer
---
v2 New patch. Move shared functions outside OCRAM only area.
v3 C
From: Thor Thayer
The device private data structures should be converted from const
struct edac_device_prv_data to static const struct edac_device_prv_data.
Signed-off-by: Thor Thayer
---
v4 New patch added for conversion.
v5 No change
---
drivers/edac/altera_edac.c | 16
From: Thor Thayer
In preparation for additional memory module ECCs, add the
memory initialization functions and helper functions used
for memory initialization.
Signed-off-by: Thor Thayer
---
v2: Specify INTMODE selection -> IRQ on each ECC error.
Insert functions above memory-specific func
From: Thor Thayer
Add the device tree entries needed to support the Altera Ethernet
FIFO buffer EDAC on the Arria10 chip.
Signed-off-by: Thor Thayer
---
v2 No change
v3 Add interrupts for SBERR and DBERR.
v4 No change
v5 Change "parent" phandle to "altr,ecc-parent"
---
arch/arm/boot/dts/so
From: Thor Thayer
This patch set adds the Ethernet EDAC and memory initialization functions
for Altera's Arria10 peripherals. The ECC memory init functions are common
to all the peripheral memory buffers (to follow in later patches).
Version 5 corrects a misunderstanding of the phandle name for
From: Thor Thayer
In preparation for the Arria10 ECC modules, check the status
of the parent in the device tree to ensure the block is enabled.
Skip if no parent phandle is set in the device tree.
Signed-off-by: Thor Thayer
---
v2 No change
v3 Move check into validate_parent_available().
v4
From: Thor Thayer
Add Altera Arria10 Ethernet FIFO memory EDAC support. Update
to support a common compatibility string for all Ethernet
FIFOs in the DT.
Signed-off-by: Thor Thayer
---
v2 Remove (void *) cast from altr_edac_device_of_match[]
Addition of panic flag to ethernet private data.
From: Thor Thayer
Add the device tree bindings needed to support the Altera Ethernet
FIFO buffers on the Arria10 chip.
Signed-off-by: Thor Thayer
---
v2 No Change
v3 Change to common compatible string based on maintainer comments
Add local IRQ values.
v4 Add compatible string for parent
From: Thor Thayer
In preparation for additional memory module ECCs, the
IRQ function will check a panic flag before doing a
kernel panic on double bit errors.
OCRAM uncorrectable errors cause a panic because sleep/resume
functions and FPGA contents during sleep are stored in OCRAM.
ECCs on peri
From: Thor Thayer
Add the device tree bindings needed to support the Altera Ethernet
FIFO buffers on the Arria10 chip.
Signed-off-by: Thor Thayer
---
v2 No Change
v3 Change to common compatible string based on maintainer comments
Add local IRQ values.
v4 Add compatible string for parent
From: Thor Thayer
The device private data structures should be converted from const
struct edac_device_prv_data to static const struct edac_device_prv_data.
Signed-off-by: Thor Thayer
---
v4 New patch added for conversion.
---
drivers/edac/altera_edac.c | 16
1 file changed
From: Thor Thayer
In preparation for additional memory module ECCs, the IRQ and
check_deps() functions are being made available to all the memory
buffers. Move them outside of the OCRAM only area.
Signed-off-by: Thor Thayer
---
v2 New patch. Move shared functions outside OCRAM only area.
v3 C
From: Thor Thayer
This patch set adds the Ethernet EDAC and memory initialization functions
for Altera's Arria10 peripherals. The ECC memory init functions are common
to all the peripheral memory buffers (to follow in later patches).
Thor Thayer (7):
EDAC, altera: Add panic flag check to A10 I
From: Thor Thayer
In preparation for additional memory module ECCs, the
IRQ function will check a panic flag before doing a
kernel panic on double bit errors.
OCRAM uncorrectable errors cause a panic because sleep/resume
functions and FPGA contents during sleep are stored in OCRAM.
ECCs on peri
From: Thor Thayer
In preparation for additional memory module ECCs, add the
memory initialization functions and helper functions used
for memory initialization.
Signed-off-by: Thor Thayer
---
v2: Specify INTMODE selection -> IRQ on each ECC error.
Insert functions above memory-specific func
From: Thor Thayer
Add Altera Arria10 Ethernet FIFO memory EDAC support. Update
to support a common compatibility string for all ethernet
FIFOs in the DT.
Signed-off-by: Thor Thayer
---
v2 Remove (void *) cast from altr_edac_device_of_match[]
Addition of panic flag to ethernet private data.
From: Thor Thayer
Add the device tree entries needed to support the Altera Ethernet
FIFO buffer EDAC on the Arria10 chip.
Signed-off-by: Thor Thayer
---
v2 No change
v3 Add interrupts for SBERR and DBERR.
v4 No change
---
arch/arm/boot/dts/socfpga_arria10.dtsi | 16
1 fil
From: Thor Thayer
In preparation for the Arria10 ECC modules, check the status
of the parent in the device tree to ensure the block is enabled.
Skip if no parent phandle is set in the device tree.
Signed-off-by: Thor Thayer
---
v2 No change
v3 Move check into validate_parent_available().
---
From: Thor Thayer
In preparation for additional memory module ECCs, the
IRQ function will check a panic flag before doing a
kernel panic on double bit errors. ECCs on buffers
will not cause a kernel panic on DBERRs.
Signed-off-by: Thor Thayer
---
v2 New patch. Add panic flag to IRQ function.
v
From: Thor Thayer
Add the device tree bindings needed to support the Altera Ethernet
FIFO buffers on the Arria10 chip.
Signed-off-by: Thor Thayer
---
v2 No Change
v3 Change to common compatible string based on maintainer comments
Add local IRQ values.
---
.../bindings/arm/altera/socfpga-
From: Thor Thayer
In preparation for additional memory module ECCs, add the
memory initialization functions and helper functions used
for memory initialization.
Signed-off-by: Thor Thayer
---
v2: Specify INTMODE selection -> IRQ on each ECC error.
Insert functions above memory-specific func
From: Thor Thayer
Add Altera Arria10 Ethernet FIFO memory EDAC support. Update
to support a common compatibility string for all ethernet
FIFOs in the DT.
Signed-off-by: Thor Thayer
---
v2 Remove (void *) cast from altr_edac_device_of_match[]
Addition of panic flag to ethernet private data.
From: Thor Thayer
Add the device tree entries needed to support the Altera Ethernet
FIFO buffer EDAC on the Arria10 chip.
Signed-off-by: Thor Thayer
---
v2 No change
v3 Add interrupts for SBERR and DBERR.
---
arch/arm/boot/dts/socfpga_arria10.dtsi | 16
1 file changed, 16
From: Thor Thayer
In preparation for additional memory module ECCs, the IRQ and
check_deps() functions are being made available to all the memory
buffers. Move them outside of the OCRAM only area.
Signed-off-by: Thor Thayer
---
v2 New patch. Move shared functions outside OCRAM only area.
v3 C
From: Thor Thayer
This patch set adds the Ethernet EDAC and memory initialization functions
for Altera's Arria10 peripherals. The ECC memory init functions are common
to all the peripheral memory buffers.
Thor Thayer (7):
EDAC, altera: Check parent status for Arria10 EDAC block
EDAC, altera:
From: Thor Thayer
To better support child devices, the ECC manager needs to be
implemented as an IRQ controller.
Signed-off-by: Thor Thayer
---
v2 Update with cleanup/improvements from maintainer.
---
drivers/edac/altera_edac.c | 161 +---
drivers/edac
From: Thor Thayer
Separate the device match arrays for each platform to prevent
CycloneV matches when calling of_platform_populate() on the
Arria10 ECC manager node.
If the SDRAM is a child node of ECC manager, call probe function
via of_platform_populate().
Signed-off-by: Thor Thayer
---
driv
From: Thor Thayer
Designate the ECC Manager as an interrupt controller and add child
interrupts.
Signed-off-by: Thor Thayer
---
.../bindings/arm/altera/socfpga-eccmgr.txt | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindi
From: Thor Thayer
Changes to support ECC Manager as SDRAM IRQ parent by
1) updating IRQ property values to correct child IRQs
2) moving node under ECC Manager.
Signed-off-by: Thor Thayer
---
arch/arm/boot/dts/socfpga_arria10.dtsi | 13 +++--
1 file changed, 7 insertions(+), 6 deletio
From: Thor Thayer
The Arria10 IRQs for each peripheral ECC block funnel into 2 IRQs
[1 for single bit errors (SBERR) and 1 for double bit errors (DBERR)]
which are better handled by the IRQ controller and IRQ domain
framework than the IRQ handler in the current implementation.
The IRQ numbers (h
From: Thor Thayer
To better support child devices, the ECC manager needs to be
implemented as an IRQ controller.
Signed-off-by: Thor Thayer
---
drivers/edac/altera_edac.c | 162 +---
drivers/edac/altera_edac.h |5 +-
2 files changed, 125 insertions(
From: Thor Thayer
Changes to support IRQ controller implementation including adding
new property irq-controller to eccmgr and adding IRQ property
to children.
Signed-off-by: Thor Thayer
---
arch/arm/boot/dts/socfpga_arria10.dtsi |6 ++
1 file changed, 6 insertions(+)
diff --git a/arch
From: Thor Thayer
In preparation for the Arria10 ECC modules, check the status
of the parent in the device tree to ensure the block is enabled.
Skip if no parent phandle is set in the device tree.
Signed-off-by: Thor Thayer
---
v2 No change
---
drivers/edac/altera_edac.c |9 +
1 f
From: Thor Thayer
In preparation for additional memory module ECCs, the
IRQ function will check a panic flag before doing a
kernel panic on double bit errors. ECCs on buffers
will not cause a kernel panic on DBERRs.
Signed-off-by: Thor Thayer
---
v2 New patch. Add panic flag to IRQ function.
-
From: Thor Thayer
This patch set adds the memory initialization functions for Altera's
Arria10 peripherals, the first of which is the Ethernet EDAC. The
ECC memory init functions are common to all the peripheral memory
buffers.
Thor Thayer (7):
EDAC, altera: Check parent status for Arria10 EDA
From: Thor Thayer
In preparation for additional memory module ECCs, the IRQ and
check_deps() functions are being made available to all the
memory buffers. Move it outside of the OCRAM only area.
Signed-off-by: Thor Thayer
---
v2 New patch. Move shared functions outside OCRAM only area.
---
dr
From: Thor Thayer
In preparation for additional memory module ECCs, add the
memory initialization functions.
Signed-off-by: Thor Thayer
---
v2: Specify INTMODE selection -> IRQ on each ECC error.
Insert functions above memory-specific functions so that function
declarations are not requ
From: Thor Thayer
Add the device tree entries needed to support the Altera Ethernet
FIFO buffer EDAC on the Arria10 chip.
Signed-off-by: Thor Thayer
---
v2 No change
---
arch/arm/boot/dts/socfpga_arria10.dtsi | 36
1 file changed, 36 insertions(+)
diff --gi
From: Thor Thayer
Add the device tree bindings needed to support the Altera Ethernet
FIFO buffers on the Arria10 chip.
Signed-off-by: Thor Thayer
---
v2 No Change
---
.../bindings/arm/altera/socfpga-eccmgr.txt | 24
1 file changed, 24 insertions(+)
diff --git a
From: Thor Thayer
Add Altera Arria10 Ethernet FIFO memory EDAC support.
Signed-off-by: Thor Thayer
---
v2 Remove (void *) cast from altr_edac_device_of_match[]
Addition of panic flag to private data.
---
drivers/edac/Kconfig |7 ++
drivers/edac/altera_edac.c | 159 +
From: Thor Thayer
In preparation for additional memory module ECCs, the
IRQ declaration is being made available to everyone.
Move it outside of the OCRAM only area.
Signed-off-by: Thor Thayer
---
drivers/edac/altera_edac.c |7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff -
From: Thor Thayer
In preparation for additional memory module ECCs, add the
memory initialization functions.
Signed-off-by: Thor Thayer
---
drivers/edac/altera_edac.c | 152
drivers/edac/altera_edac.h |3 +
2 files changed, 155 insertions(+)
d
From: Thor Thayer
Add the device tree entries needed to support the Altera Ethernet
FIFO buffer EDAC on the Arria10 chip.
Signed-off-by: Thor Thayer
---
arch/arm/boot/dts/socfpga_arria10.dtsi | 36
1 file changed, 36 insertions(+)
diff --git a/arch/arm/boot/
From: Thor Thayer
Add the device tree bindings needed to support the Altera Ethernet
FIFO buffers on the Arria10 chip.
Signed-off-by: Thor Thayer
---
.../bindings/arm/altera/socfpga-eccmgr.txt | 24
1 file changed, 24 insertions(+)
diff --git a/Documentation/dev
From: Thor Thayer
In preparation for the Arria10 ECC modules, check the status
of the parent in the device tree to ensure the block is enabled.
Skip if no parent phandle is set in the device tree.
Signed-off-by: Thor Thayer
---
drivers/edac/altera_edac.c |9 +
1 file changed, 9 ins
From: Thor Thayer
Add Altera Arria10 Ethernet FIFO memory EDAC support.
Signed-off-by: Thor Thayer
---
drivers/edac/Kconfig |7 ++
drivers/edac/altera_edac.c | 153
drivers/edac/altera_edac.h | 14
3 files changed, 174 insertions(+
This patch set adds the memory initialization functions for Altera's
Arria10 peripherals, the first of which is the Ethernet EDAC. The
first 3 patches add the memory initialization functionality. The
last 3 patches add Ethernet EDAC support.
[PATCH 1/6] EDAC, altera: Check parent status for Arria1
From: Thor Thayer
In preparation for the Arria10 peripheral ECCs, a register
offset from the ECC base was added to the private data
structure to index to the ECC enable register.
Signed-off-by: Thor Thayer
---
v2: No change
---
drivers/edac/altera_edac.c |3 ++-
drivers/edac/altera_edac.h
From: Thor Thayer
Add the device tree bindings needed to support the Altera On-Chip
RAM ECC on the Arria10 chip.
Signed-off-by: Thor Thayer
---
v2: Align Required Properties descriptions
---
.../bindings/arm/altera/socfpga-eccmgr.txt | 10 ++
1 file changed, 10 insertions(+)
From: Thor Thayer
Enable ECC for Arria10 On-Chip RAM on machine startup. The ECC has to
be enabled and memory initialized before data is stored in memory
otherwise the ECC will fail on reads.
Signed-off-by: Thor Thayer
---
v2: Add Arria10 ECC block initialization locally.
---
arch/arm/mach-soc
From: Thor Thayer
Add the device tree entries needed to support the Altera On-Chip
RAM EDAC on the Arria10 chip.
Signed-off-by: Thor Thayer
---
v2: No change
---
arch/arm/boot/dts/socfpga_arria10.dtsi |5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/socfpga_arria10
From: Thor Thayer
Addition of the Arria10 On-Chip RAM ECC handling. Addition
of private data structure for Arria10 OCRAM ECC.
Addition of a new file operations function and trigger
function for Arria10 OCRAM and other peripheral memories.
Signed-off-by: Thor Thayer
---
v2: Remove the Arria10 EC
From: Thor Thayer
In preparation for the Arria10 peripheral ECCs, new file
operations are used because the Arria10 IRQ trigger mechanism
is different than Cyclone5/Arria5 and Arria10 L2 cache.
Add new pointer for file operations function to ecc data
structure and point to current file operations
From: Thor Thayer
In preparation for the Arria10 peripheral ECCs, the OCRAM
ECC dependency check was moved into the general ECC area
since this same function can be used by other memories.
Signed-off-by: Thor Thayer
---
v2: No change
---
drivers/edac/altera_edac.c | 43 +-
From: Thor Thayer
This series of patches adds the Arria10 OCRAM EDAC support
Thor Thayer (7):
EDAC, altera: New file operations for Arria10 ECC modules
EDAC, altera: Add register offset for ECC Enable
EDAC, altera: Make OCRAM ECC dependency check generic
Documentation: dt: socfpga: Add A
From: Thor Thayer
Enable ECC for Arria10 On-Chip RAM on machine startup. The ECC has to be
enabled before data is stored in memory otherwise the ECC will fail
on reads.
Signed-off-by: Thor Thayer
---
arch/arm/mach-socfpga/core.h|1 +
arch/arm/mach-socfpga/ocram.c | 22 +
From: Thor Thayer
In preparation for the Arria10 peripheral ECCs, a register
offset from the ECC base was added to the private data
structure to index to the ECC enable register.
Signed-off-by: Thor Thayer
---
drivers/edac/altera_edac.c |3 ++-
drivers/edac/altera_edac.h |1 +
2 files
From: Thor Thayer
In preparation for the Arria10 peripheral ECCs, new file
operations are used because the Arria10 IRQ trigger mechanism
is different than Cyclone5/Arria5 and Arria10 L2 cache.
Add new pointer for file operations function to ecc data
structure and point to current file operations
From: Thor Thayer
In preparation for the Arria10 peripheral ECCs, the OCRAM
ECC dependency check was moved into the general ECC area
since this same function can be used by other memories.
Signed-off-by: Thor Thayer
---
drivers/edac/altera_edac.c | 43 +---
From: Thor Thayer
Addition of the Arria10 On-Chip RAM ECC handling. Addition
of private data structure for Arria10 OCRAM ECC and the
ECC module and memory initialization functions which are
shared between memory modules such as NAND, Ethernet, etc.
Addition of a new file operations function and t
From: Thor Thayer
Add the device tree entries needed to support the Altera On-Chip
RAM EDAC on the Arria10 chip.
Signed-off-by: Thor Thayer
---
arch/arm/boot/dts/socfpga_arria10.dtsi |5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi
b/arch/arm/
From: Thor Thayer
Add the device tree bindings needed to support the Altera On-Chip
RAM ECC on the Arria10 chip.
Signed-off-by: Thor Thayer
---
.../bindings/arm/altera/socfpga-eccmgr.txt | 10 ++
1 file changed, 10 insertions(+)
diff --git a/Documentation/devicetree/bindings
This series of patches adds the Arria10 OCRAM EDAC support.
[PATCH 1/7] EDAC, altera: New file operations for Arria10 ECC
[PATCH 2/7] EDAC, altera: Add register offset for ECC Enable
[PATCH 3/7] EDAC, altera: Make OCRAM ECC dependency check generic
[PATCH 4/7] Documentation: dt: socfpga: Add Alter
From: Thor Thayer
Add the device tree bindings needed to support the Altera L2
cache on the Arria10 chip. Since all the peripherals share
IRQs, the IRQ fields are now in the ecc_manager.
Signed-off-by: Thor Thayer
---
v2 Correct spelling of Arria10 in patch title.
v3 Major restructuring change
From: Thor Thayer
Enable ECC for Arria10 L2 cache on machine startup. The ECC has to be
enabled before data is stored in memory otherwise the ECC will fail
on reads.
Use DT_MACHINE to select Arria10 L2 cache function.
Signed-off-by: Thor Thayer
Acked-by: Dinh Nguyen
---
v2: Split into 2 separa
From: Thor Thayer
Addition of the Arria10 L2 Cache ECC handling. Addition
of private data structure for Arria10 L2 cache ECC and
the probe function for it.
The Arria10 ECC device IRQs are in a shared register so
the ECC Manager parent/child relationship requires a
different probe function.
Signe
From: Thor Thayer
Force L2 cache dependency instead of forcing selection of
L2 cache.
Signed-off-by: Thor Thayer
---
v2/3 No change
---
drivers/edac/Kconfig |5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 37755e6..6c
This version refactors how the EDAC is configured for Arria10 since
the ECC hardware is significantly different than Cyclone5 and Arria5.
Since all the IRQs are shared, a new probe function based on the
xgene codebase was used.
[PATCHv3 1/9] EDAC: Altera L2 Kconfig change from select to depends
[
From: Thor Thayer
In preparation for the Arria10 peripheral ECCs, the
ECC Enable mask is used in place of hard coded masks
in the check dependency functions.
Signed-off-by: Thor Thayer
---
v3: This change added.
---
drivers/edac/altera_edac.c |9 +++--
1 file changed, 7 insertions(+),
From: Thor Thayer
In preparation for the Arria10 peripheral ECCs, a register
offset from the ECC base was added to the private data
structure to index to the error injection register.
Signed-off-by: Thor Thayer
---
v2: Split large patch into smaller patches. Add an ECC
error inject offset t
From: Thor Thayer
Add the device tree entries needed to support the Altera L2
cache EDAC on the Arria10 chip.
Signed-off-by: Thor Thayer
---
v2 Match register value (l2-ecc@ffd06010)
v3 Set ecc_manager to beginning of system_manager. Add sysman
phandle. Move IRQs into ecc_manager from childr
From: Thor Thayer
In preparation for the Arria10 peripheral ECCs, the
platform device parameter is removed from the check_deps()
functions because it is not needed and makes the Arria10
check_deps() cleaner.
Signed-off-by: Thor Thayer
---
v3: This change added.
---
drivers/edac/altera_edac.c
From: Thor Thayer
Move the device structs and defines to altera_edac.h in preparation
for adding the Arria10 L2 cache ECC.
Signed-off-by: Thor Thayer
---
v2: Split original patch into smaller patches. Move private data
and defines into header file.
v3: Commented description above defines.
-
From: Thor Thayer
Add the device tree entries needed to support the Altera L2
cache EDAC on the Arria10 chip.
Signed-off-by: Thor Thayer
---
v2 Match register value (l2-ecc@ffd06010)
---
arch/arm/boot/dts/socfpga_arria10.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git
From: Thor Thayer
Addition of the Arria10 L2 Cache ECC handling. Addition
of private data structure for Arria10 L2 cache ECC and
the initialization function for it.
Signed-off-by: Thor Thayer
---
v2: Split large patch into smaller patches. Addition of
Arria10 L2 cache dependency check and p
From: Thor Thayer
In preparation for the Arria10 peripheral ECCs, irq_flags
was added to the private data structure because Arria10
uses shared IRQs while Cyclone5/Arria5 have exclusive IRQs.
Signed-off-by: Thor Thayer
---
v2: Split large patch into smaller patches. Add irq_flags
to the pri
From: Thor Thayer
Enable ECC for Arria10 L2 cache on machine startup. The ECC has to be
enabled before data is stored in memory otherwise the ECC will fail
on reads.
Use DT_MACHINE to select Arria10 L2 cache function.
Signed-off-by: Thor Thayer
---
v2: Split into 2 separate functions selected w
From: Thor Thayer
In preparation for the Arria10 peripheral ECCs, a register
offset from the ECC base was added to the private data
structure to index to the error injection register.
Signed-off-by: Thor Thayer
---
v2: Split large patch into smaller patches. Add an ECC
error inject offset t
From: Thor Thayer
In preparation for the Arria10 peripheral ECCs, the IRQ
status needs to be determined because the IRQs are shared.
The IRQ status register is read to determine if the IRQ
was for this ECC peripheral. Cyclone5 and Arria5 have
dedicated IRQs so the confirmation mechanism is not
re
From: Thor Thayer
Move the device structs and defines to altera_edac.h in preparation
for adding the Arria10 L2 cache ECC.
Signed-off-by: Thor Thayer
---
v2: Split original patch into smaller patches. Move private data
and defines into header file.
---
drivers/edac/altera_edac.c | 43 ---
From: Thor Thayer
In preparation for the Arria10 peripheral ECCs, a register
offset from the ECC base was added to the private data
structure to index into the ECC enable register.
Signed-off-by: Thor Thayer
---
v2: Split large patch into smaller patches. Add an ECC
control offset to suppor
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