On Thu, Apr 07, 2016 at 09:54:16AM -0600, Naveen Kaje wrote:
> The ARMv8.0 architecture reserves several system register
> encodings for future use. These encodings should behave
> as read-only and always return zero on a read. The Kryo core
> errantly causes an instruction abort upon an AArch64
>
On Mon, Apr 11, 2016 at 07:49:20AM +0100, James Morse wrote:
> On 08/04/16 11:24, Marc Zyngier wrote:
> > On 08/04/16 10:58, Suzuki K Poulose wrote:
> >> On 07/04/16 18:31, Marc Zyngier wrote:
> >>
> +All system register encodings above use the form
> +
> +Op0, Op1, C
On 08/04/16 11:24, Marc Zyngier wrote:
> On 08/04/16 10:58, Suzuki K Poulose wrote:
>> On 07/04/16 18:31, Marc Zyngier wrote:
>>
+ All system register encodings above use the form
+
+ Op0, Op1, CRn, CRm, Op2.
+
+ Note that some of the encodings listed above include
On 08/04/16 11:31, Suzuki K Poulose wrote:
> On 08/04/16 11:24, Marc Zyngier wrote:
>> On 08/04/16 10:58, Suzuki K Poulose wrote:
>>> On 07/04/16 18:31, Marc Zyngier wrote:
>>>
> + All system register encodings above use the form
> +
> + Op0, Op1, CRn, CRm, Op2.
> +
> + Note tha
On 08/04/16 11:24, Marc Zyngier wrote:
On 08/04/16 10:58, Suzuki K Poulose wrote:
On 07/04/16 18:31, Marc Zyngier wrote:
+ All system register encodings above use the form
+
+ Op0, Op1, CRn, CRm, Op2.
+
+ Note that some of the encodings listed above include
+ the system
On 08/04/16 10:58, Suzuki K Poulose wrote:
> On 07/04/16 18:31, Marc Zyngier wrote:
>
>>> + All system register encodings above use the form
>>> +
>>> + Op0, Op1, CRn, CRm, Op2.
>>> +
>>> + Note that some of the encodings listed above include
>>> + the system register space reserved for th
On 07/04/16 18:31, Marc Zyngier wrote:
+ All system register encodings above use the form
+
+ Op0, Op1, CRn, CRm, Op2.
+
+ Note that some of the encodings listed above include
+ the system register space reserved for the following
+ identification registers which ma
HI Naveen,
On 07/04/16 16:54, Naveen Kaje wrote:
> The ARMv8.0 architecture reserves several system register
> encodings for future use. These encodings should behave
> as read-only and always return zero on a read. The Kryo core
> errantly causes an instruction abort upon an AArch64
> read attem
The ARMv8.0 architecture reserves several system register
encodings for future use. These encodings should behave
as read-only and always return zero on a read. The Kryo core
errantly causes an instruction abort upon an AArch64
read attempt to the following system register encodings using
the MRS i
