Tejun Heo wrote:
ATA_ECAT_DUBIOUS_BASE was too high by one and thus all DUBIOUS error
categorizations were wrong. This passed test because only ATA_BUS and
UNK_DEV were used during testing and the ones after them - ATA_BUS and
an overflowed entry - behaved similarly.
This patch fixes the
Tejun Heo schrieb:
Mark Lord wrote:
Tejun,
This Oops (2.6.23.13) looks very much like the same bug
you fixed recently for me in 2.6.24.
The bug was with sata_qstor and other drivers, in that
devres/libata were freeing the I/O resources before invoking
the LLD's host/port_stop routines ..
Tejun Heo wrote:
Factor out AHCI enabling into ahci_enable_ahci() and enabling AHCI
before reading CAP in ahci_save_initial_config() as the spec requires
enabling AHCI mode before accessing any other registers.
Signed-off-by: Tejun Heo [EMAIL PROTECTED]
Ping. Sorry about the missing
For ICH8, SCRs can be accessed using index and data register pair
located at BAR 5. This patch implements support for it such that PHY
status, errors and hardreset are available for those controllers.
This is the only case where two devices on a PATA channel have access
to SCRs and creates a
ata_piix requires more configuration during initialization than most
other SFF compliant controllers and one-go initialzation with
ata_pci_one() is too rigid.
This patch converts ata_piix to use two step prepare - activate
initialization used by other more advanced controllers. This
conversion
Factor out ata_pci_activate_sff_host() from ata_pci_one(). This does
about the same thing as ata_host_activate() but needs to be separate
because SFF controllers use different and multiple IRQs in legacy
mode.
This will be used to make SFF LLD initialization more flexible.
Signed-off-by: Tejun
This patchset implements SIDPR SCR access which is available for ICH8
and above. With SIDPR SCR access enabled, ata_piix ports can access
PHY events and errors and can also be hardreset which is important as
in rare cases hardreset is necessary to recover from error conditions.
Changes from the
+ /* udmatim Register */
+ palm_bk3710_base-config.udmatim = 0xFFF0;
+ palm_bk3710_base-config.udmatim |= level;
Direct memory access to I/O space - should be using read/write functions
Sigh, I was anticipationg that somebody would say that... :-)
Well
Tomasz Chmielewski wrote:
Tejun Heo schrieb:
Mark Lord wrote:
Tejun,
This Oops (2.6.23.13) looks very much like the same bug
you fixed recently for me in 2.6.24.
The bug was with sata_qstor and other drivers, in that
devres/libata were freeing the I/O resources before invoking
the LLD's
On Thu, 17 Jan 2008 16:50:42 -0600
James Bottomley [EMAIL PROTECTED] wrote:
On Tue, 2008-01-15 at 16:44 -0800, Kristen Carlson Accardi wrote:
Add Enclosure Management support to libata and ahci.
This patch adds support for the LED protocol, as defined in the
AHCI spec. It adds a generic
Alan Cox wrote:
It won't -- we can *not* call ide_setup_dma() which fills them out as this
is not a PCI chip.
Gak.
Or maybe we still can -- with hwif-mmio set?
AFAIR (from the 2006 discussion) Bart said it's *only* for PCI devices...
Alan
MBR, Sergei
-
To unsubscribe from this
On Thu, 2008-01-10 at 02:21 -0500, Jeff Garzik wrote:
Jeff Garzik wrote:
1) To make it easier for people to review and test the driver, I would
suggest posting a diff against 2.6.24-rc7 (or 2.6.23), ignoring my
original code. Thus, it would result in a patch
Er, that sentence was
Hello, Jeff:
I am on an Nforce4-Ultra board with a mix of ATA/SATA
disk drives and a SATA burner(GSA-H30L), while the
writer has been working well under a 2.6.16 kernel
with the old IDE-SATA driver. My recent upgrade to
2.6.23 resulted the drive being identified as a 0xCDROM
drive(I have
On Fri, 2008-01-18 at 09:41 -0800, Kristen Carlson Accardi wrote:
On Fri, 18 Jan 2008 11:11:21 -0600
James Bottomley [EMAIL PROTECTED] wrote:
On Fri, 2008-01-18 at 08:52 -0800, Kristen Carlson Accardi wrote:
On Thu, 17 Jan 2008 16:50:42 -0600
James Bottomley [EMAIL PROTECTED] wrote:
ATA requires that all DMA transfers begin and end on word boundaries.
Because of this, a large amount of machinery grew up in ide to adjust
scatterlists on this basis. However, as of 2.5, the block layer has a
dma_alignment variable which ensures both the beginning and length of a
DMA transfer
Matt Mackall wrote:
On Wed, 2008-01-16 at 10:00 +0900, Tejun Heo wrote:
And mprintk the following.
code:
DEFINE_MPRINTK(mp, 2 * 80);
mprintk_set_header(mp, KERN_INFO ata%u.%2u: , 1, 0);
mprintk_push(mp, ATA %d, 7);
mprintk_push(mp, , %u sectors\n, 1024);
mprintk(mp, everything
On Fri, 18 Jan 2008 18:16:34 -0600
James Bottomley [EMAIL PROTECTED] wrote:
On Fri, 2008-01-18 at 09:41 -0800, Kristen Carlson Accardi wrote:
On Fri, 18 Jan 2008 11:11:21 -0600
James Bottomley [EMAIL PROTECTED] wrote:
On Fri, 2008-01-18 at 08:52 -0800, Kristen Carlson Accardi
On Fri, 18 Jan 2008 18:47:18 -0600
James Bottomley [EMAIL PROTECTED] wrote:
On Fri, 2008-01-18 at 16:35 -0800, Kristen Carlson Accardi wrote:
Unfortunately, all the dual SAS/SATA enclosures seem to be coming
with either SGPIO devices or full fledged SES-2 devices. I've
actually got
On Fri, 18 Jan 2008 18:16:34 -0600
James Bottomley [EMAIL PROTECTED] wrote:
On Fri, 2008-01-18 at 09:41 -0800, Kristen Carlson Accardi wrote:
On Fri, 18 Jan 2008 11:11:21 -0600
James Bottomley [EMAIL PROTECTED] wrote:
On Fri, 2008-01-18 at 08:52 -0800, Kristen Carlson Accardi
On Fri, 2008-01-18 at 16:35 -0800, Kristen Carlson Accardi wrote:
Unfortunately, all the dual SAS/SATA enclosures seem to be coming with
either SGPIO devices or full fledged SES-2 devices. I've actually got
both (a backplane with SGPIO and an internal SAS/SATA enclosure with
SES-2).
Hello.
Alan Cox wrote:
This is Palmchip BK3710 IDE controller support for kernel version 2.6.24-rc8.
The IDE controller logic supports PIO, multiword DMA and ultra-DMA modes.
Supports interface to compact Flash (CF) configured in True-IDE mode.
New drivers should really be going at least
On Fri, 18 Jan 2008 11:11:21 -0600
James Bottomley [EMAIL PROTECTED] wrote:
On Fri, 2008-01-18 at 08:52 -0800, Kristen Carlson Accardi wrote:
On Thu, 17 Jan 2008 16:50:42 -0600
James Bottomley [EMAIL PROTECTED] wrote:
On Tue, 2008-01-15 at 16:44 -0800, Kristen Carlson Accardi wrote:
On Friday 18 January 2008, Sergei Shtylyov wrote:
Alan Cox wrote:
It won't -- we can *not* call ide_setup_dma() which fills them out as
this
is not a PCI chip.
Gak.
Or maybe we still can -- with hwif-mmio set?
AFAIR (from the 2006 discussion) Bart said it's *only* for
Hi,
On Thursday 17 January 2008, Anton Salnikov wrote:
This is Palmchip BK3710 IDE controller support for kernel version 2.6.24-rc8.
The IDE controller logic supports PIO, multiword DMA and ultra-DMA modes.
Supports interface to compact Flash (CF) configured in True-IDE mode.
Thanks, overall
On Fri, 2008-01-18 at 16:55 -0800, Kristen Carlson Accardi wrote:
On Fri, 18 Jan 2008 18:47:18 -0600
James Bottomley [EMAIL PROTECTED] wrote:
On Fri, 2008-01-18 at 16:35 -0800, Kristen Carlson Accardi wrote:
Unfortunately, all the dual SAS/SATA enclosures seem to be coming
with
On Fri, 2008-01-18 at 11:44 -0700, Matthew Wilcox wrote:
On Fri, Jan 18, 2008 at 12:41:08PM -0600, Matt Mackall wrote:
On Wed, 2008-01-16 at 10:00 +0900, Tejun Heo wrote:
And mprintk the following.
code:
DEFINE_MPRINTK(mp, 2 * 80);
mprintk_set_header(mp, KERN_INFO
On Wed, 2008-01-16 at 10:00 +0900, Tejun Heo wrote:
And mprintk the following.
code:
DEFINE_MPRINTK(mp, 2 * 80);
mprintk_set_header(mp, KERN_INFO ata%u.%2u: , 1, 0);
mprintk_push(mp, ATA %d, 7);
mprintk_push(mp, , %u sectors\n, 1024);
mprintk(mp, everything seems dandy\n);
On Fri, Jan 18, 2008 at 12:41:08PM -0600, Matt Mackall wrote:
On Wed, 2008-01-16 at 10:00 +0900, Tejun Heo wrote:
And mprintk the following.
code:
DEFINE_MPRINTK(mp, 2 * 80);
mprintk_set_header(mp, KERN_INFO ata%u.%2u: , 1, 0);
mprintk_push(mp, ATA %d, 7);
On Fri, 2008-01-18 at 08:52 -0800, Kristen Carlson Accardi wrote:
On Thu, 17 Jan 2008 16:50:42 -0600
James Bottomley [EMAIL PROTECTED] wrote:
On Tue, 2008-01-15 at 16:44 -0800, Kristen Carlson Accardi wrote:
Add Enclosure Management support to libata and ahci.
This patch adds
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