On Fri, Jul 22, 2016 at 09:42:30AM +0800, Yakir Yang wrote:
> According to page 16 of Sharp LQ123P1JX31 datasheet, we need to add the
> missing delay timing. Panel prepare time should be t1 (0.5ms~10ms) plus
> t3 (0ms~100ms), and panel enable time should equal to t7 (0ms~50ms), and
> panel
On Fri, Jul 22, 2016 at 09:42:30AM +0800, Yakir Yang wrote:
> According to page 16 of Sharp LQ123P1JX31 datasheet, we need to add the
> missing delay timing. Panel prepare time should be t1 (0.5ms~10ms) plus
> t3 (0ms~100ms), and panel enable time should equal to t7 (0ms~50ms), and
> panel
Hi Alan,
>> So you mean if I do "hciconfig hci0 down", then the uart-bus should
>> "down" the tty and only on "hciconfig hci0 up" it should "up" the
>> tty? I would expect a uart-bus slave-device takes control of the
>> device ("up" it) on probe. It's hardwired anyway.
>
> Today you can switch
Hello,
I hit the following BUG:
[1851513.239831] [ cut here ]
[1851513.240079] kernel BUG at net/unix/garbage.c:149!
[1851513.240313] invalid opcode: [#1] SMP
[1851513.248320] CPU: 37 PID: 11683 Comm: nginx Tainted: G O
4.4.14-clouder3 #26
Hi Alan,
>> So you mean if I do "hciconfig hci0 down", then the uart-bus should
>> "down" the tty and only on "hciconfig hci0 up" it should "up" the
>> tty? I would expect a uart-bus slave-device takes control of the
>> device ("up" it) on probe. It's hardwired anyway.
>
> Today you can switch
Hello,
I hit the following BUG:
[1851513.239831] [ cut here ]
[1851513.240079] kernel BUG at net/unix/garbage.c:149!
[1851513.240313] invalid opcode: [#1] SMP
[1851513.248320] CPU: 37 PID: 11683 Comm: nginx Tainted: G O
4.4.14-clouder3 #26
On 08/24/2016 04:10 PM, Arvind Yadav wrote:
> iounmap frees the mapping when timer id is not matching.
>
> Signed-off-by: Arvind Yadav
What is the difference with the V2 ?
> ---
> drivers/clocksource/clps711x-timer.c | 41
> +++-
> 1
Hi,
Given a SoC and its SDK, 3rd party users of said SoC (customers of the SoC's
manufacturer) may need/want to write kernel modules.
Since the DT describes the HW, it would make sense to expose some HW properties
through the DT, and have 3rd party users rely on them to write their drivers in
a
On 08/24/2016 04:10 PM, Arvind Yadav wrote:
> iounmap frees the mapping when timer id is not matching.
>
> Signed-off-by: Arvind Yadav
What is the difference with the V2 ?
> ---
> drivers/clocksource/clps711x-timer.c | 41
> +++-
> 1 file changed, 22
Hi,
Given a SoC and its SDK, 3rd party users of said SoC (customers of the SoC's
manufacturer) may need/want to write kernel modules.
Since the DT describes the HW, it would make sense to expose some HW properties
through the DT, and have 3rd party users rely on them to write their drivers in
a
On (08/24/16 10:19), Petr Mladek wrote:
> > On (08/23/16 13:47), Petr Mladek wrote:
> > [..]
> > > > if (!(lflags & LOG_NEWLINE)) {
> > > > + if (!this_cpu_read(cont_printing)) {
> > > > + if (system_state == SYSTEM_RUNNING) {
> > > > +
On (08/24/16 10:19), Petr Mladek wrote:
> > On (08/23/16 13:47), Petr Mladek wrote:
> > [..]
> > > > if (!(lflags & LOG_NEWLINE)) {
> > > > + if (!this_cpu_read(cont_printing)) {
> > > > + if (system_state == SYSTEM_RUNNING) {
> > > > +
Em Sun, Aug 21, 2016 at 03:57:33PM +0800, Shawn Lin escreveu:
> lzma_decompress_to_file never actually close the file
> pointer, let's fix it.
>
> Signed-off-by: Shawn Lin
Thanks, I changed the logic a bit to shorten the patch, this is how it
ended up:
commit
Em Sun, Aug 21, 2016 at 03:57:33PM +0800, Shawn Lin escreveu:
> lzma_decompress_to_file never actually close the file
> pointer, let's fix it.
>
> Signed-off-by: Shawn Lin
Thanks, I changed the logic a bit to shorten the patch, this is how it
ended up:
commit
yes, I am referring this code for clock control.
--Arvind
On Tuesday 23 August 2016 09:45 PM, Heiko Stübner wrote:
Hi Arvind,
Am Samstag, 13. August 2016, 20:56:18 schrieb Arvind Yadav:
-check return of 'of_iomap'.if It's falied to remap then abort.
-Unmap a region obtained by remap.
yes, I am referring this code for clock control.
--Arvind
On Tuesday 23 August 2016 09:45 PM, Heiko Stübner wrote:
Hi Arvind,
Am Samstag, 13. August 2016, 20:56:18 schrieb Arvind Yadav:
-check return of 'of_iomap'.if It's falied to remap then abort.
-Unmap a region obtained by remap.
iounmap frees the mapping when timer id is not matching.
Signed-off-by: Arvind Yadav
---
drivers/clocksource/clps711x-timer.c | 41 +++-
1 file changed, 22 insertions(+), 19 deletions(-)
diff --git
iounmap frees the mapping when timer id is not matching.
Signed-off-by: Arvind Yadav
---
drivers/clocksource/clps711x-timer.c | 41 +++-
1 file changed, 22 insertions(+), 19 deletions(-)
diff --git a/drivers/clocksource/clps711x-timer.c
On 08/23/2016 07:49 AM, Ming Lei wrote:
After arbitrary bio size is supported, the incoming bio may
be very big. We have to split the bio into small bios so that
each holds at most BIO_MAX_PAGES bvecs for safety reason, such
as bio_clone().
This patch fixes the following kernel crash:
[
On 08/23/2016 07:49 AM, Ming Lei wrote:
After arbitrary bio size is supported, the incoming bio may
be very big. We have to split the bio into small bios so that
each holds at most BIO_MAX_PAGES bvecs for safety reason, such
as bio_clone().
This patch fixes the following kernel crash:
[
Alexander Shishkin writes:
> Alexander Shishkin writes:
>
>> Signed-off-by: Alexander Shishkin
>
> Ok, this one is broken, please disregard.
Vince, can you try the following (with the
On Sun, Aug 21, 2016 at 11:57:58AM +0300, Dmitry Osipenko wrote:
> Window uses shared stride for UV planes and tegra_dc_window struct
> defines array of 2 strides per window. That's not taken in account
> during setting up of the window addresses and strides, resulting in
> out-of-bounds write of
On Fri, Aug 19, 2016 at 04:30:25PM +0800, Chen Yu wrote:
> People reported that they can not do a poweroff nor a
> suspend to ram on their Mac Pro 11. After some investigations
> it was found that, once the PCI bridge :00:1c.0 reassigns its
> mm windows to ([mem 0x7fa0-0x7fbf] and
>
Alexander Shishkin writes:
> Alexander Shishkin writes:
>
>> Signed-off-by: Alexander Shishkin
>
> Ok, this one is broken, please disregard.
Vince, can you try the following (with the other two in this series)?
---
>From 68713194b3df8e565c4d319a80e9e7338fa1ec13 Mon Sep 17 00:00:00 2001
On Sun, Aug 21, 2016 at 11:57:58AM +0300, Dmitry Osipenko wrote:
> Window uses shared stride for UV planes and tegra_dc_window struct
> defines array of 2 strides per window. That's not taken in account
> during setting up of the window addresses and strides, resulting in
> out-of-bounds write of
On Fri, Aug 19, 2016 at 04:30:25PM +0800, Chen Yu wrote:
> People reported that they can not do a poweroff nor a
> suspend to ram on their Mac Pro 11. After some investigations
> it was found that, once the PCI bridge :00:1c.0 reassigns its
> mm windows to ([mem 0x7fa0-0x7fbf] and
>
Le 23/08/2016 à 21:03, Florian Fainelli a écrit :
+others,
On 08/23/2016 04:13 AM, Christophe Leroy wrote:
In ERRATA DS8700A dated 05 May 2016, Microship recommends to
not use software power down mode on KSZ8041 family.
s/Microship/Microchip/
They say they have no plan to fix this
Le 23/08/2016 à 21:03, Florian Fainelli a écrit :
+others,
On 08/23/2016 04:13 AM, Christophe Leroy wrote:
In ERRATA DS8700A dated 05 May 2016, Microship recommends to
not use software power down mode on KSZ8041 family.
s/Microship/Microchip/
They say they have no plan to fix this
On 08/24/2016 04:52 AM, Andy Lutomirski wrote:
nvme_set_features() callers seem to expect that passing NULL as the
result pointer is acceptable. Teach nvme_set_features() not to try to
write to the NULL address.
For symmetry, make the same change to nvme_get_features(), despite the
fact that
On 08/24/2016 04:52 AM, Andy Lutomirski wrote:
nvme_set_features() callers seem to expect that passing NULL as the
result pointer is acceptable. Teach nvme_set_features() not to try to
write to the NULL address.
For symmetry, make the same change to nvme_get_features(), despite the
fact that
Sorry if I'm making redundant comments with previous discussions, I
might have missed a few threads.
On Mon, Aug 22, 2016 at 2:05 PM, Heikki Krogerus
wrote:
> The purpose of USB Type-C connector class is to provide
> unified interface for the user space to get
Sorry if I'm making redundant comments with previous discussions, I
might have missed a few threads.
On Mon, Aug 22, 2016 at 2:05 PM, Heikki Krogerus
wrote:
> The purpose of USB Type-C connector class is to provide
> unified interface for the user space to get the status and
> basic information
On 24/08/2016 13:59, Hannes Reinecke wrote:
On 08/24/2016 01:05 PM, John Garry wrote:
Add code in slot_complete_v2_hw() to deal with the
slots which have completed due to internal abort.
The status codes have the following meaning:
- STAT_IO_ABORTED: the IO has been aborted due to
internal
On 24/08/2016 13:59, Hannes Reinecke wrote:
On 08/24/2016 01:05 PM, John Garry wrote:
Add code in slot_complete_v2_hw() to deal with the
slots which have completed due to internal abort.
The status codes have the following meaning:
- STAT_IO_ABORTED: the IO has been aborted due to
internal
> > +/* Set Management Data Clock, must be call after device reset */
> > +static void sun8i_emac_set_mdc(struct net_device *ndev)
> > +{
> > + struct sun8i_emac_priv *priv = netdev_priv(ndev);
> > + unsigned long rate;
> > + u32 reg;
> > +
> > + rate = clk_get_rate(priv->ahb_clk);
> > +
> > +/* Set Management Data Clock, must be call after device reset */
> > +static void sun8i_emac_set_mdc(struct net_device *ndev)
> > +{
> > + struct sun8i_emac_priv *priv = netdev_priv(ndev);
> > + unsigned long rate;
> > + u32 reg;
> > +
> > + rate = clk_get_rate(priv->ahb_clk);
> > +
On Tue, Aug 23, 2016 at 10:25:45PM +0100, Al Viro wrote:
> Sadly, sizeof is what we use when copying that sucker to userland. So these
> padding bits in the end would've leaked, true enough, and the case is somewhat
> weaker. And any normal architecture will have those, but then any such
>
On Tue, Aug 23, 2016 at 10:25:45PM +0100, Al Viro wrote:
> Sadly, sizeof is what we use when copying that sucker to userland. So these
> padding bits in the end would've leaked, true enough, and the case is somewhat
> weaker. And any normal architecture will have those, but then any such
>
In v4l2_async_test_notify() if the registered_async callback or the
complete notifier returns an error the subdev is not unregistered.
This leave paths where v4l2_async_register_subdev() can fail but
leave the subdev still registered.
Add the required calls to v4l2_device_unregister_subdev() to
In v4l2_async_test_notify() if the registered_async callback or the
complete notifier returns an error the subdev is not unregistered.
This leave paths where v4l2_async_register_subdev() can fail but
leave the subdev still registered.
Add the required calls to v4l2_device_unregister_subdev() to
On Wed, Aug 24, 2016 at 04:44:50AM +0800, Salil Mehta wrote:
> This patch is meant to add support of ACPI to the Hisilicon RoCE
> driver.
>
> Changes done are primarily meant to detect the type and then either
> use DT specific or ACPI spcific functions. Where ever possible,
> this patch tries to
On Wed, Aug 24, 2016 at 04:44:50AM +0800, Salil Mehta wrote:
> This patch is meant to add support of ACPI to the Hisilicon RoCE
> driver.
>
> Changes done are primarily meant to detect the type and then either
> use DT specific or ACPI spcific functions. Where ever possible,
> this patch tries to
> So you mean if I do "hciconfig hci0 down", then the uart-bus should
> "down" the tty and only on "hciconfig hci0 up" it should "up" the
> tty? I would expect a uart-bus slave-device takes control of the
> device ("up" it) on probe. It's hardwired anyway.
Today you can switch stacks at runtime,
> So you mean if I do "hciconfig hci0 down", then the uart-bus should
> "down" the tty and only on "hciconfig hci0 up" it should "up" the
> tty? I would expect a uart-bus slave-device takes control of the
> device ("up" it) on probe. It's hardwired anyway.
Today you can switch stacks at runtime,
Implement the .set_eeprom callback to allow setting the MAC address
as well as a few other parameters. Note that the EEPROM must have a
correct PID/VID checksum set otherwise the SROM is used and reads
return the SROM content.
Signed-off-by: Alban Bedel
---
Implement the .set_eeprom callback to allow setting the MAC address
as well as a few other parameters. Note that the EEPROM must have a
correct PID/VID checksum set otherwise the SROM is used and reads
return the SROM content.
Signed-off-by: Alban Bedel
---
drivers/net/usb/ax88179_178a.c | 57
This patch supports the multiple IORESOURCE_MEM resources for one pin-bank.
In the pre-existing Exynos series, the registers of the gpio bank are included
in the one memory map. But, some gpio bank need to support the one more memory
map (IORESOURCE_MEM) because the registers of gpio bank are
This patch supports the multiple IORESOURCE_MEM resources for one pin-bank.
In the pre-existing Exynos series, the registers of the gpio bank are included
in the one memory map. But, some gpio bank need to support the one more memory
map (IORESOURCE_MEM) because the registers of gpio bank are
From: Joonyoung Shim
This patch add the support of GPF[1-5] pin of Exynos5433 SoC. The GPFx need
to support the multiple memory map because the registers of GPFx are located
in the different domain.
Cc: Linus Walleij
Cc: Rob Herring
This patch adds the support for ARM 64bit. The delay_timer is only supported
on ARM 32bit.
Cc: Daniel Lezcano
Cc: Thomas Gleixner
Cc: Kukjin Kim
Cc: Krzysztof Kozlowski
Signed-off-by: Chanwoo Choi
From: Joonyoung Shim
This patch add the support of GPF[1-5] pin of Exynos5433 SoC. The GPFx need
to support the multiple memory map because the registers of GPFx are located
in the different domain.
Cc: Linus Walleij
Cc: Rob Herring
Cc: Mark Rutland
Cc: Tomasz Figa
Cc: Krzysztof Kozlowski
This patch adds the support for ARM 64bit. The delay_timer is only supported
on ARM 32bit.
Cc: Daniel Lezcano
Cc: Thomas Gleixner
Cc: Kukjin Kim
Cc: Krzysztof Kozlowski
Signed-off-by: Chanwoo Choi
---
drivers/clocksource/Kconfig | 2 +-
drivers/clocksource/exynos_mct.c | 4
2
This patch adds the exynos5433 PMU compatible to support the access
of PMU (Power Management Unit) block.
Signed-off-by: Chanwoo Choi
Reviewed-by: Krzysztof Kozlowski
Acked-by: Rob Herring
---
This patch adds new Exynos5433 dtsi to support 64-bit Exynos5433 SoC based on
Octa-core CPUs (quad Cortex-A57 and quad Cortex-A53). And Exynos5433 supports
PSCI (Power State Coordination Interface) v0.1.
This patch includes following Device Tree node to support Exynos5433 SoC:
1. Octa cores for
This patchset adds the Device Tree file for Samsung 64-bit Exynos5433 SoC
and TM/TM2E board based on Exynos5433. The Exynos5433 has Octa-core CPUs
(quad Cortex-A57 and quad Cortex-A53). The TM2 and TM2E are the Samsung board
based on Exynos5433 SoC.
I sent the Exynos5433 patches[2]. But it was
This patch adds the exynos5433 PMU compatible to support the access
of PMU (Power Management Unit) block.
Signed-off-by: Chanwoo Choi
Reviewed-by: Krzysztof Kozlowski
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/arm/samsung/pmu.txt | 1 +
1 file changed, 1 insertion(+)
diff
This patch adds new Exynos5433 dtsi to support 64-bit Exynos5433 SoC based on
Octa-core CPUs (quad Cortex-A57 and quad Cortex-A53). And Exynos5433 supports
PSCI (Power State Coordination Interface) v0.1.
This patch includes following Device Tree node to support Exynos5433 SoC:
1. Octa cores for
This patchset adds the Device Tree file for Samsung 64-bit Exynos5433 SoC
and TM/TM2E board based on Exynos5433. The Exynos5433 has Octa-core CPUs
(quad Cortex-A57 and quad Cortex-A53). The TM2 and TM2E are the Samsung board
based on Exynos5433 SoC.
I sent the Exynos5433 patches[2]. But it was
Am Dienstag, den 16.08.2016, 18:41 +0900 schrieb Masahiro Yamada:
> Hi Arnd,
>
> 2016-08-06 0:35 GMT+09:00 Arnd Bergmann :
>
> >
> > config RESET_FOO
> > bool "FOO reset controller" if COMPILE_TEST && !ARCH_FOO
> > default ARCH_FOO
> >
> > then I think we get both:
Am Dienstag, den 16.08.2016, 18:41 +0900 schrieb Masahiro Yamada:
> Hi Arnd,
>
> 2016-08-06 0:35 GMT+09:00 Arnd Bergmann :
>
> >
> > config RESET_FOO
> > bool "FOO reset controller" if COMPILE_TEST && !ARCH_FOO
> > default ARCH_FOO
> >
> > then I think we get both: you won't be
On Wed, Aug 24, 2016 at 06:58:11PM +0800, Herbert Xu wrote:
> On Fri, Aug 19, 2016 at 03:42:55PM +0200, LABBE Corentin wrote:
> > The driver name is displayed each time differently.
> > This patch make use of the same name everywhere.
> >
> > Signed-off-by: LABBE Corentin
On Wed, Aug 24, 2016 at 06:58:11PM +0800, Herbert Xu wrote:
> On Fri, Aug 19, 2016 at 03:42:55PM +0200, LABBE Corentin wrote:
> > The driver name is displayed each time differently.
> > This patch make use of the same name everywhere.
> >
> > Signed-off-by: LABBE Corentin
> > ---
> >
This patch adds the Device Tree source for Exynos5433-based Samsung TM2E
board. TM2E board is the most similar with TM2 board. The exynos5433-tm2e.dts
include the difference between TM2 and TM2E.
Signed-off-by: Chanwoo Choi
Signed-off-by: Jaehoon Chung
On Fri, 1 Jul 2016 13:55:44 +0200
Hans Verkuil wrote:
> On 05/11/2016 06:32 PM, Alban Bedel wrote:
> > On Wed, 11 May 2016 12:22:44 -0400
> > Javier Martinez Canillas wrote:
> >
> >> Hello Alban,
> >>
> >> On 05/11/2016 11:40 AM, Alban Bedel wrote:
This patch adds the Device Tree source for Exynos5433-based Samsung TM2E
board. TM2E board is the most similar with TM2 board. The exynos5433-tm2e.dts
include the difference between TM2 and TM2E.
Signed-off-by: Chanwoo Choi
Signed-off-by: Jaehoon Chung
Signed-off-by: Seung-Woo Kim
On Fri, 1 Jul 2016 13:55:44 +0200
Hans Verkuil wrote:
> On 05/11/2016 06:32 PM, Alban Bedel wrote:
> > On Wed, 11 May 2016 12:22:44 -0400
> > Javier Martinez Canillas wrote:
> >
> >> Hello Alban,
> >>
> >> On 05/11/2016 11:40 AM, Alban Bedel wrote:
> >>> In v4l2_async_test_notify() if the
On Mon, 22 Aug 2016 17:39:09 -0500
Rob Herring wrote:
> tty_port_open handles much of the common parts of tty opening. Convert
> uart_open to use it and move the serial_core specific parts into
> tty_port.activate function. This will be needed to use tty_port functions
>
This patch adds the Device Tree source for Exynos5433-based Samsung TM2 board.
This board fully support the all things for mobile target.
This patch supports the following devices:
1. basic SoC
- Initial booting for Samsung Exynos5433 SoC
- DRAM LPDDR3 (3GB)
- eMMC (32GB)
- ARM architecture timer
On Mon, 22 Aug 2016 17:39:09 -0500
Rob Herring wrote:
> tty_port_open handles much of the common parts of tty opening. Convert
> uart_open to use it and move the serial_core specific parts into
> tty_port.activate function. This will be needed to use tty_port functions
> directly from in kernel
This patch adds the Device Tree source for Exynos5433-based Samsung TM2 board.
This board fully support the all things for mobile target.
This patch supports the following devices:
1. basic SoC
- Initial booting for Samsung Exynos5433 SoC
- DRAM LPDDR3 (3GB)
- eMMC (32GB)
- ARM architecture timer
Commit-ID: 01175255fd8e3e993353a779f819ec8c0c59137e
Gitweb: http://git.kernel.org/tip/01175255fd8e3e993353a779f819ec8c0c59137e
Author: Brian Gerst
AuthorDate: Sat, 13 Aug 2016 12:38:22 -0400
Committer: Ingo Molnar
CommitDate: Wed, 24 Aug 2016
Commit-ID: 01175255fd8e3e993353a779f819ec8c0c59137e
Gitweb: http://git.kernel.org/tip/01175255fd8e3e993353a779f819ec8c0c59137e
Author: Brian Gerst
AuthorDate: Sat, 13 Aug 2016 12:38:22 -0400
Committer: Ingo Molnar
CommitDate: Wed, 24 Aug 2016 12:31:51 +0200
sched: Remove __schedule()
Commit-ID: 4e047aa7f267c3449b6d323510d35864829aca70
Gitweb: http://git.kernel.org/tip/4e047aa7f267c3449b6d323510d35864829aca70
Author: Brian Gerst
AuthorDate: Sat, 13 Aug 2016 12:38:16 -0400
Committer: Ingo Molnar
CommitDate: Wed, 24 Aug 2016
Commit-ID: 4e047aa7f267c3449b6d323510d35864829aca70
Gitweb: http://git.kernel.org/tip/4e047aa7f267c3449b6d323510d35864829aca70
Author: Brian Gerst
AuthorDate: Sat, 13 Aug 2016 12:38:16 -0400
Committer: Ingo Molnar
CommitDate: Wed, 24 Aug 2016 12:27:40 +0200
sched/x86/32, kgdb: Don't
Commit-ID: 13e25bab7e51bdd4ba7df1ef2388961294bb565e
Gitweb: http://git.kernel.org/tip/13e25bab7e51bdd4ba7df1ef2388961294bb565e
Author: Josh Poimboeuf
AuthorDate: Fri, 19 Aug 2016 06:53:02 -0500
Committer: Ingo Molnar
CommitDate: Wed, 24 Aug 2016
Commit-ID: 13e25bab7e51bdd4ba7df1ef2388961294bb565e
Gitweb: http://git.kernel.org/tip/13e25bab7e51bdd4ba7df1ef2388961294bb565e
Author: Josh Poimboeuf
AuthorDate: Fri, 19 Aug 2016 06:53:02 -0500
Committer: Ingo Molnar
CommitDate: Wed, 24 Aug 2016 12:15:15 +0200
x86/dumpstack/ftrace:
Commit-ID: 163630191ecb0dd9e4146d3c910045aba1cfeec1
Gitweb: http://git.kernel.org/tip/163630191ecb0dd9e4146d3c910045aba1cfeec1
Author: Brian Gerst
AuthorDate: Sat, 13 Aug 2016 12:38:17 -0400
Committer: Ingo Molnar
CommitDate: Wed, 24 Aug 2016
Commit-ID: 163630191ecb0dd9e4146d3c910045aba1cfeec1
Gitweb: http://git.kernel.org/tip/163630191ecb0dd9e4146d3c910045aba1cfeec1
Author: Brian Gerst
AuthorDate: Sat, 13 Aug 2016 12:38:17 -0400
Committer: Ingo Molnar
CommitDate: Wed, 24 Aug 2016 12:27:40 +0200
sched/x86/64, kgdb: Clear
Commit-ID: 408fe5de2f2767059a9561e0ae6d4385d1b39dac
Gitweb: http://git.kernel.org/tip/408fe5de2f2767059a9561e0ae6d4385d1b39dac
Author: Josh Poimboeuf
AuthorDate: Fri, 19 Aug 2016 06:52:59 -0500
Committer: Ingo Molnar
CommitDate: Wed, 24 Aug 2016
Commit-ID: 408fe5de2f2767059a9561e0ae6d4385d1b39dac
Gitweb: http://git.kernel.org/tip/408fe5de2f2767059a9561e0ae6d4385d1b39dac
Author: Josh Poimboeuf
AuthorDate: Fri, 19 Aug 2016 06:52:59 -0500
Committer: Ingo Molnar
CommitDate: Wed, 24 Aug 2016 12:15:14 +0200
x86/dumpstack/ftrace:
Commit-ID: b2d4c2edb2e4f89aaf85449dee3b87fbf0f8a4d4
Gitweb: http://git.kernel.org/tip/b2d4c2edb2e4f89aaf85449dee3b87fbf0f8a4d4
Author: Vegard Nossum
AuthorDate: Thu, 18 Aug 2016 18:41:00 +0200
Committer: Ingo Molnar
CommitDate: Wed, 24 Aug
Commit-ID: 6f727b84e23421721025f4eb1b4f6cea1d4d723a
Gitweb: http://git.kernel.org/tip/6f727b84e23421721025f4eb1b4f6cea1d4d723a
Author: Josh Poimboeuf
AuthorDate: Fri, 19 Aug 2016 06:53:01 -0500
Committer: Ingo Molnar
CommitDate: Wed, 24 Aug 2016
Commit-ID: 6f727b84e23421721025f4eb1b4f6cea1d4d723a
Gitweb: http://git.kernel.org/tip/6f727b84e23421721025f4eb1b4f6cea1d4d723a
Author: Josh Poimboeuf
AuthorDate: Fri, 19 Aug 2016 06:53:01 -0500
Committer: Ingo Molnar
CommitDate: Wed, 24 Aug 2016 12:15:15 +0200
x86/dumpstack/ftrace:
Commit-ID: b2d4c2edb2e4f89aaf85449dee3b87fbf0f8a4d4
Gitweb: http://git.kernel.org/tip/b2d4c2edb2e4f89aaf85449dee3b87fbf0f8a4d4
Author: Vegard Nossum
AuthorDate: Thu, 18 Aug 2016 18:41:00 +0200
Committer: Ingo Molnar
CommitDate: Wed, 24 Aug 2016 12:16:13 +0200
locking/hung_task: Show
On Wed, 24 Aug 2016 11:22:09 +0300
"Dan Akunis" wrote:
> When select wakes up on a UDP socket, user is expecting to get data. Getting
> 0 from recvfrom() or whatever read function she uses, is a wrong attitude.
> I agree with David.
>
> The unit test that expects select
On Wed, 24 Aug 2016 11:22:09 +0300
"Dan Akunis" wrote:
> When select wakes up on a UDP socket, user is expecting to get data. Getting
> 0 from recvfrom() or whatever read function she uses, is a wrong attitude.
> I agree with David.
>
> The unit test that expects select to wake up is wrong and
Since commit 183223770ae862 ("drivers/of: Export OF changeset functions"),
the mentioned functions do all necessary locking.
Signed-off-by: Wolfram Sang
Fixes: 183223770ae862 ("drivers/of: Export OF changeset functions")
---
V2: corrected the "Fixes" tag
Since commit 183223770ae862 ("drivers/of: Export OF changeset functions"),
the mentioned functions do all necessary locking.
Signed-off-by: Wolfram Sang
Fixes: 183223770ae862 ("drivers/of: Export OF changeset functions")
---
V2: corrected the "Fixes" tag
From: Mirza Krak
Hi.
This is a follow up to my previous RFC to add support for Tegra GMI bus
controller.
I have tested this series on a Tegra30 using a Colibri T30 SOM on a custom
carrier board which has multiple CAN controllers (SJA1000) connected to the
GMI bus.
I have
From: Mirza Krak
Add a device node for the GMI controller found on Tegra20.
Signed-off-by: Mirza Krak
---
Changes in v2:
- added address-cells, size-cells and ranges properties
arch/arm/boot/dts/tegra20.dtsi | 14 ++
1 file changed, 14
From: Mirza Krak
Add a device node for the GMI controller found on Tegra30.
Signed-off-by: Mirza Krak
---
Changes in v2:
- added address-cells, size-cells and ranges properties
arch/arm/boot/dts/tegra30.dtsi | 13 +
1 file changed, 13
From: Mirza Krak
Add TEGRA30_CLK_NOR to init table and set default rate to 127 MHz which
is max rate.
Signed-off-by: Mirza Krak
---
Changes in v2:
- no changes
drivers/clk/tegra/clk-tegra30.c | 1 +
1 file changed, 1 insertion(+)
diff --git
From: Mirza Krak
Hi.
This is a follow up to my previous RFC to add support for Tegra GMI bus
controller.
I have tested this series on a Tegra30 using a Colibri T30 SOM on a custom
carrier board which has multiple CAN controllers (SJA1000) connected to the
GMI bus.
I have rebased on top of
From: Mirza Krak
Add a device node for the GMI controller found on Tegra20.
Signed-off-by: Mirza Krak
---
Changes in v2:
- added address-cells, size-cells and ranges properties
arch/arm/boot/dts/tegra20.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git
From: Mirza Krak
Add a device node for the GMI controller found on Tegra30.
Signed-off-by: Mirza Krak
---
Changes in v2:
- added address-cells, size-cells and ranges properties
arch/arm/boot/dts/tegra30.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git
From: Mirza Krak
Add TEGRA30_CLK_NOR to init table and set default rate to 127 MHz which
is max rate.
Signed-off-by: Mirza Krak
---
Changes in v2:
- no changes
drivers/clk/tegra/clk-tegra30.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/tegra/clk-tegra30.c
From: Mirza Krak
Document the devicetree bindings for the Generic Memory Interface (GMI)
bus driver found on Tegra SOCs.
Signed-off-by: Mirza Krak
---
Changes in v2:
- Updated examples and some information based on comments from Jon Hunter.
From: Mirza Krak
The Generic Memory Interface bus can be used to connect high-speed
devices such as NOR flash, FPGAs, DSPs...
Signed-off-by: Mirza Krak
---
Changes in v2:
- Fixed some checkpatch errors
- Re-ordered probe to get rid of local variables
From: Mirza Krak
Add TEGRA20_CLK_NOR to init tabel and set default rate to 92 MHz which
is max rate.
Signed-off-by: Mirza Krak
---
Changes in v2:
- no changes
drivers/clk/tegra/clk-tegra20.c | 1 +
1 file changed, 1 insertion(+)
diff --git
From: Mirza Krak
Document the devicetree bindings for the Generic Memory Interface (GMI)
bus driver found on Tegra SOCs.
Signed-off-by: Mirza Krak
---
Changes in v2:
- Updated examples and some information based on comments from Jon Hunter.
.../devicetree/bindings/bus/nvidia,tegra20-gmi.txt
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