[resend RFC 5/6] sysfs: add sysfs_add_group_link()

The current __compat_only_sysfs_link_entry_to_kobj() code allows us to create symbolic links in sysfs to groups or attributes. Something like: /sys/.../entry1/groupA -> /sys/.../entry2/groupA This patch extends this functionality with a new sysfs_add_group_link() call that allows the link to

[resend RFC 5/6] sysfs: add sysfs_add_group_link()

The current __compat_only_sysfs_link_entry_to_kobj() code allows us to create symbolic links in sysfs to groups or attributes. Something like: /sys/.../entry1/groupA -> /sys/.../entry2/groupA This patch extends this functionality with a new sysfs_add_group_link() call that allows the link to

[resend RFC 4/6] hmem: add heterogeneous memory sysfs support

Add a new sysfs subsystem, /sys/devices/system/hmem, which surfaces information about memory initiators and memory targets to the user. These initiators and targets are described by the ACPI SRAT and HMAT tables. A "memory initiator" in this case is any device such as a CPU or a separate memory

[resend RFC 4/6] hmem: add heterogeneous memory sysfs support

Add a new sysfs subsystem, /sys/devices/system/hmem, which surfaces information about memory initiators and memory targets to the user. These initiators and targets are described by the ACPI SRAT and HMAT tables. A "memory initiator" in this case is any device such as a CPU or a separate memory

[resend RFC 6/6] hmem: add performance attributes

Add performance information found in the HMAT to the sysfs representation. This information lives as an attribute group named "via_mem_initX" in the memory target: # tree mem_tgt2 mem_tgt2 ├── firmware_id ├── is_cached ├── is_enabled ├── is_isolated ├── node2 -> ../../node/node2

[resend RFC 6/6] hmem: add performance attributes

Add performance information found in the HMAT to the sysfs representation. This information lives as an attribute group named "via_mem_initX" in the memory target: # tree mem_tgt2 mem_tgt2 ├── firmware_id ├── is_cached ├── is_enabled ├── is_isolated ├── node2 -> ../../node/node2

[resend RFC 2/6] acpi: add missing include in acpi_numa.h

Right now if a file includes acpi_numa.h and they don't happen to include linux/numa.h before it, they get the following warning: ./include/acpi/acpi_numa.h:9:5: warning: "MAX_NUMNODES" is not defined [-Wundef] #if MAX_NUMNODES > 256 ^~~~ Signed-off-by: Ross Zwisler

[resend RFC 3/6] acpi: HMAT support in acpi_parse_entries_array()

The current implementation of acpi_parse_entries_array() assumes that each subtable has a standard ACPI subtable entry of type struct acpi_sutbable_header. This standard subtable header has a one byte length followed by a one byte type. The HMAT subtables have to allow for a longer length so

[resend RFC 2/6] acpi: add missing include in acpi_numa.h

Right now if a file includes acpi_numa.h and they don't happen to include linux/numa.h before it, they get the following warning: ./include/acpi/acpi_numa.h:9:5: warning: "MAX_NUMNODES" is not defined [-Wundef] #if MAX_NUMNODES > 256 ^~~~ Signed-off-by: Ross Zwisler ---

[resend RFC 3/6] acpi: HMAT support in acpi_parse_entries_array()

The current implementation of acpi_parse_entries_array() assumes that each subtable has a standard ACPI subtable entry of type struct acpi_sutbable_header. This standard subtable header has a one byte length followed by a one byte type. The HMAT subtables have to allow for a longer length so

[PATCH v4] hsdk: initial port for HSDK board

This initial port adds support of ARC HS Development Kit board with some basic features such serial port, USB, SD/MMC and Ethernet. Essentially we run Linux kernel on all 4 cores (i.e. utilize SMP) and heavily use IO Coherency for speeding-up DMA-aware peripherals. Note as opposed to other ARC

[resend RFC 0/6] Add support for Heterogeneous Memory Attribute Table

[ Apologies for the resend. The de...@acpica.org list rejected my first posting because I wasn't subscribed. ] Quick summary This series adds kernel support for the Heterogeneous Memory Attribute Table (HMAT) table, newly defined in ACPI 6.2:

[PATCH v4] hsdk: initial port for HSDK board

This initial port adds support of ARC HS Development Kit board with some basic features such serial port, USB, SD/MMC and Ethernet. Essentially we run Linux kernel on all 4 cores (i.e. utilize SMP) and heavily use IO Coherency for speeding-up DMA-aware peripherals. Note as opposed to other ARC

[resend RFC 0/6] Add support for Heterogeneous Memory Attribute Table

[ Apologies for the resend. The de...@acpica.org list rejected my first posting because I wasn't subscribed. ] Quick summary This series adds kernel support for the Heterogeneous Memory Attribute Table (HMAT) table, newly defined in ACPI 6.2:

Re: [PATCH v3 00/27] Thunderbolt security levels and NVM firmware upgrade

On Mon, Jun 05, 2017 at 07:01:10PM +0200, Andreas Noever wrote: > On Mon, Jun 5, 2017 at 9:18 AM, Mika Westerberg > wrote: > > On Sat, Jun 03, 2017 at 06:17:04PM +0900, Greg Kroah-Hartman wrote: > >> On Fri, Jun 02, 2017 at 05:04:57PM +0300, Mika Westerberg wrote:

Re: [PATCH v3 00/27] Thunderbolt security levels and NVM firmware upgrade

On Mon, Jun 05, 2017 at 07:01:10PM +0200, Andreas Noever wrote: > On Mon, Jun 5, 2017 at 9:18 AM, Mika Westerberg > wrote: > > On Sat, Jun 03, 2017 at 06:17:04PM +0900, Greg Kroah-Hartman wrote: > >> On Fri, Jun 02, 2017 at 05:04:57PM +0300, Mika Westerberg wrote: > >> > Hi, > >> > > >> > This is

Re: workqueue list corruption

Hello, On Sun, Jun 04, 2017 at 12:30:03PM -0700, Cong Wang wrote: > On Tue, Apr 18, 2017 at 8:08 PM, Samuel Holland wrote: > > Representative backtraces follow (the warnings come in sets). I have > > kernel .configs and extended netconsole output from several occurrences > >

Re: workqueue list corruption

Hello, On Sun, Jun 04, 2017 at 12:30:03PM -0700, Cong Wang wrote: > On Tue, Apr 18, 2017 at 8:08 PM, Samuel Holland wrote: > > Representative backtraces follow (the warnings come in sets). I have > > kernel .configs and extended netconsole output from several occurrences > > available upon

Re: [PATCH] virtio_net: lower limit on buffer size

On Sat, Jun 03, 2017 at 11:17:30PM +0300, Sergei Shtylyov wrote: > On 06/02/2017 11:25 PM, J. Bruce Fields wrote: > > >>>commit d85b758f72b0 "virtio_net: fix support for small rings" > >> > >> Commit d85b758f72b0 ("virtio_net: fix support for small rings") > >> > >>>was supposed to increase the

Re: [PATCH] virtio_net: lower limit on buffer size

On Sat, Jun 03, 2017 at 11:17:30PM +0300, Sergei Shtylyov wrote: > On 06/02/2017 11:25 PM, J. Bruce Fields wrote: > > >>>commit d85b758f72b0 "virtio_net: fix support for small rings" > >> > >> Commit d85b758f72b0 ("virtio_net: fix support for small rings") > >> > >>>was supposed to increase the

Re: [PATCH v2] um: Avoid longjmp/setjmp symbol clashes with libpthread.a

Florian, Am 05.06.2017 um 21:32 schrieb Florian Fainelli: > On 05/23/2017 05:32 PM, Florian Fainelli wrote: >> Building a statically linked UML kernel on a Centos 6.9 host resulted in >> the following linking failure (GCC 4.4, glibc-2.12): >> >>

Re: [PATCH v2] um: Avoid longjmp/setjmp symbol clashes with libpthread.a

Florian, Am 05.06.2017 um 21:32 schrieb Florian Fainelli: > On 05/23/2017 05:32 PM, Florian Fainelli wrote: >> Building a statically linked UML kernel on a Centos 6.9 host resulted in >> the following linking failure (GCC 4.4, glibc-2.12): >> >>

PM / Suspend: Print wall time at suspend entry and exit

Permits power state and battery life diagnosis. Signed-off-by: Todd Poynor Signed-off-by: Mark Salyzyn --- kernel/power/suspend.c | 15 +++ 1 file changed, 15 insertions(+) diff --git a/kernel/power/suspend.c b/kernel/power/suspend.c

PM / Suspend: Print wall time at suspend entry and exit

Permits power state and battery life diagnosis. Signed-off-by: Todd Poynor Signed-off-by: Mark Salyzyn --- kernel/power/suspend.c | 15 +++ 1 file changed, 15 insertions(+) diff --git a/kernel/power/suspend.c b/kernel/power/suspend.c index c0248c74d6d4..464175f04bc5 100644 ---

PM / Hibernation: Print wall time at hibernation entry and exit

Permits power state and battery life diagnosis. Signed-off-by: Mark Salyzyn --- kernel/power/hibernate.c | 2 ++ kernel/power/power.h | 1 + kernel/power/suspend.c | 2 +- 3 files changed, 4 insertions(+), 1 deletion(-) diff --git a/kernel/power/hibernate.c

PM / Hibernation: Print wall time at hibernation entry and exit

Permits power state and battery life diagnosis. Signed-off-by: Mark Salyzyn --- kernel/power/hibernate.c | 2 ++ kernel/power/power.h | 1 + kernel/power/suspend.c | 2 +- 3 files changed, 4 insertions(+), 1 deletion(-) diff --git a/kernel/power/hibernate.c b/kernel/power/hibernate.c

Re: [PATCH v2] um: Avoid longjmp/setjmp symbol clashes with libpthread.a

On 05/23/2017 05:32 PM, Florian Fainelli wrote: > Building a statically linked UML kernel on a Centos 6.9 host resulted in > the following linking failure (GCC 4.4, glibc-2.12): > > /usr/lib/gcc/x86_64-redhat-linux/4.4.7/../../../../lib64/libpthread.a(libpthread.o): > In function `siglongjmp': >

Re: [PATCH v2] um: Avoid longjmp/setjmp symbol clashes with libpthread.a

On 05/23/2017 05:32 PM, Florian Fainelli wrote: > Building a statically linked UML kernel on a Centos 6.9 host resulted in > the following linking failure (GCC 4.4, glibc-2.12): > > /usr/lib/gcc/x86_64-redhat-linux/4.4.7/../../../../lib64/libpthread.a(libpthread.o): > In function `siglongjmp': >

Re: [PATCH] Documentation: seq_file: Convert seq_file to rst format

On Mon, 5 Jun 2017 23:58:30 +0530 sayli karnik wrote: > Add seq_file.rst to a filesystems subsection in the docs tree. Thanks for doing this. There are a few things we'll have to get fixed before we can consider merging this one, though. For filesystem-related

Re: [PATCH 1/4] mfd: da903x: Make it explicitly non-modular

[RE: [PATCH 1/4] mfd: da903x: Make it explicitly non-modular] On 05/06/2017 (Mon 10:30) Steve Twiss wrote: > Hi Paul, > > On 03 June 2017 14:04 Paul Gortmaker wrote: > > > To: linux-kernel@vger.kernel.org > > Cc: Paul Gortmaker; Support Opensource; Lee Jones; Eric Miao; Mike Rapoport > >

Re: [PATCH] Documentation: seq_file: Convert seq_file to rst format

On Mon, 5 Jun 2017 23:58:30 +0530 sayli karnik wrote: > Add seq_file.rst to a filesystems subsection in the docs tree. Thanks for doing this. There are a few things we'll have to get fixed before we can consider merging this one, though. For filesystem-related stuff, it would be good to CC Al

Re: [PATCH 1/4] mfd: da903x: Make it explicitly non-modular

[RE: [PATCH 1/4] mfd: da903x: Make it explicitly non-modular] On 05/06/2017 (Mon 10:30) Steve Twiss wrote: > Hi Paul, > > On 03 June 2017 14:04 Paul Gortmaker wrote: > > > To: linux-kernel@vger.kernel.org > > Cc: Paul Gortmaker; Support Opensource; Lee Jones; Eric Miao; Mike Rapoport > >

[PATCH 2/5] Protectable Memory Allocator

The MMU available in many systems runnign Linux can often provide R/O protection to the memory pages it handles. However, this works efficiently only when said pages contain only data that does not need to be modified. This can work well for statically allocated variables, however it doe not fit

[PATCH 0/5] ARM: sunxi: Enable dwmac-sun8i on more boards

Hello This serie enable dwmac-sun8i on more boards. The first 3 patch enable dwmac-sun8i on some h3/h5 boards. The last 2 add dwmac-sun8i on a83t. Corentin Labbe (5): ARM: sun8i: orangepi-plus: Enable dwmac-sun8i ARM: sun8i: bananapi-m2-plus: Enable dwmac-sun8i ARM: sun50i: orangepi-pc2:

[PATCH 1/5] ARM: sun8i: orangepi-plus: Enable dwmac-sun8i

The dwmac-sun8i hardware is present on the Orange PI plus. It uses an external PHY rtl8211e via RGMII. This patch create the needed regulator, emac and phy nodes. Signed-off-by: Corentin Labbe --- arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 32

[PATCH 2/5] Protectable Memory Allocator

The MMU available in many systems runnign Linux can often provide R/O protection to the memory pages it handles. However, this works efficiently only when said pages contain only data that does not need to be modified. This can work well for statically allocated variables, however it doe not fit

[PATCH 0/5] ARM: sunxi: Enable dwmac-sun8i on more boards

Hello This serie enable dwmac-sun8i on more boards. The first 3 patch enable dwmac-sun8i on some h3/h5 boards. The last 2 add dwmac-sun8i on a83t. Corentin Labbe (5): ARM: sun8i: orangepi-plus: Enable dwmac-sun8i ARM: sun8i: bananapi-m2-plus: Enable dwmac-sun8i ARM: sun50i: orangepi-pc2:

[PATCH 1/5] ARM: sun8i: orangepi-plus: Enable dwmac-sun8i

The dwmac-sun8i hardware is present on the Orange PI plus. It uses an external PHY rtl8211e via RGMII. This patch create the needed regulator, emac and phy nodes. Signed-off-by: Corentin Labbe --- arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 32 1 file changed,

[PATCH 3/5] ARM: sun50i: orangepi-pc2: Enable dwmac-sun8i

The dwmac-sun8i hardware is present on the Orange PI PC2. It uses an external PHY rtl8211e via RGMII. This patch create the needed regulator, emac and phy nodes. Signed-off-by: Corentin Labbe --- .../boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts | 27

[PATCH 3/5] ARM: sun50i: orangepi-pc2: Enable dwmac-sun8i

The dwmac-sun8i hardware is present on the Orange PI PC2. It uses an external PHY rtl8211e via RGMII. This patch create the needed regulator, emac and phy nodes. Signed-off-by: Corentin Labbe --- .../boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts | 27 ++ 1 file changed, 27

[PATCH 3/5] Protectable Memory Allocator - Debug interface

Debugfs interface: it creates a file /sys/kernel/debug/pmalloc/pools which exposes statistics about all the pools and memory nodes in use. Signed-off-by: Igor Stoppa --- mm/Kconfig | 11 ++ mm/pmalloc.c | 113

[PATCH 3/5] Protectable Memory Allocator - Debug interface

Debugfs interface: it creates a file /sys/kernel/debug/pmalloc/pools which exposes statistics about all the pools and memory nodes in use. Signed-off-by: Igor Stoppa --- mm/Kconfig | 11 ++ mm/pmalloc.c | 113 +++ 2 files changed,

[no subject]

Subject: [RFC v4 PATCH 0/5] NOT FOR MERGE - ro protection for dynamic data This patchset introduces the possibility of protecting memory that has been allocated dynamically. The memory is managed in pools: when a pool is made R/O, all the memory that is part of it, will become R/O. A R/O pool

[PATCH 4/5] Make LSM Writable Hooks a command line option

This patch shows how it is possible to take advantage of pmalloc: instead of using the build-time option __lsm_ro_after_init, to decide if it is possible to keep the hooks modifiable, now this becomes a boot-time decision, based on the kernel command line. This patch relies on: "Convert

[no subject]

Subject: [RFC v4 PATCH 0/5] NOT FOR MERGE - ro protection for dynamic data This patchset introduces the possibility of protecting memory that has been allocated dynamically. The memory is managed in pools: when a pool is made R/O, all the memory that is part of it, will become R/O. A R/O pool

[PATCH 4/5] Make LSM Writable Hooks a command line option

This patch shows how it is possible to take advantage of pmalloc: instead of using the build-time option __lsm_ro_after_init, to decide if it is possible to keep the hooks modifiable, now this becomes a boot-time decision, based on the kernel command line. This patch relies on: "Convert

[PATCH 2/5] ARM: sun8i: bananapi-m2-plus: Enable dwmac-sun8i

The dwmac-sun8i hardware is present on the Banana Pi M2+ It uses an external PHY rtl8211e via RGMII. This patch create the needed regulator, emac and phy nodes. Signed-off-by: Corentin Labbe --- arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts | 29

[PATCH 2/5] ARM: sun8i: bananapi-m2-plus: Enable dwmac-sun8i

The dwmac-sun8i hardware is present on the Banana Pi M2+ It uses an external PHY rtl8211e via RGMII. This patch create the needed regulator, emac and phy nodes. Signed-off-by: Corentin Labbe --- arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts | 29 + 1 file changed, 29

[PATCH 1/5] LSM: Convert security_hook_heads into explicit array of struct list_head

From: Tetsuo Handa Commit 3dfc9b02864b19f4 ("LSM: Initialize security_hook_heads upon registration.") treats "struct security_hook_heads" as an implicit array of "struct list_head" so that we can eliminate code for static initialization. Although we haven't

[PATCH 1/5] LSM: Convert security_hook_heads into explicit array of struct list_head

From: Tetsuo Handa Commit 3dfc9b02864b19f4 ("LSM: Initialize security_hook_heads upon registration.") treats "struct security_hook_heads" as an implicit array of "struct list_head" so that we can eliminate code for static initialization. Although we haven't encountered compilers which do not

[PATCH 4/5] ARM: sun8i: a83t: Add dt node for the syscon control module

This patch add the dt node for the syscon register present on the Allwinner A83T Signed-off-by: Corentin Labbe --- arch/arm/boot/dts/sun8i-a83t.dtsi | 6 ++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi

[PATCH 5/5] ARM: sun8i: a83t: add dwmac-sun8i ethernet driver

The dwmac-sun8i is an ethernet MAC hardware that support 10/100/1000 speed. This patch enable the dwmac-sun8i on the Allwinner a83t SoC Device-tree. Signed-off-by: Corentin Labbe --- arch/arm/boot/dts/sun8i-a83t.dtsi | 28 1 file changed,

[PATCH 4/5] ARM: sun8i: a83t: Add dt node for the syscon control module

This patch add the dt node for the syscon register present on the Allwinner A83T Signed-off-by: Corentin Labbe --- arch/arm/boot/dts/sun8i-a83t.dtsi | 6 ++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index

[PATCH 5/5] ARM: sun8i: a83t: add dwmac-sun8i ethernet driver

The dwmac-sun8i is an ethernet MAC hardware that support 10/100/1000 speed. This patch enable the dwmac-sun8i on the Allwinner a83t SoC Device-tree. Signed-off-by: Corentin Labbe --- arch/arm/boot/dts/sun8i-a83t.dtsi | 28 1 file changed, 28 insertions(+) diff

Re: [PATCH v7 00/23] FSI device driver implementation

On 6/3/17 4:25 PM, Steven Rostedt wrote: On Sat, 3 Jun 2017 19:05:10 +0900 Greg KH wrote: On Wed, May 31, 2017 at 12:17:05PM -0500, Christopher Bostic wrote: Hi Greg, Are there any further changes you require for this patch set? This has been extensively tested

Re: [PATCH v7 00/23] FSI device driver implementation

On 6/3/17 4:25 PM, Steven Rostedt wrote: On Sat, 3 Jun 2017 19:05:10 +0900 Greg KH wrote: On Wed, May 31, 2017 at 12:17:05PM -0500, Christopher Bostic wrote: Hi Greg, Are there any further changes you require for this patch set? This has been extensively tested internally and all is

Re: [PATCH v7 00/23] FSI device driver implementation

On 6/3/17 5:05 AM, Greg KH wrote: On Wed, May 31, 2017 at 12:17:05PM -0500, Christopher Bostic wrote: Hi Greg, Are there any further changes you require for this patch set? This has been extensively tested internally and all is working as expected. Would it be possible to move forward with

Re: [PATCH v7 00/23] FSI device driver implementation

On 6/3/17 5:05 AM, Greg KH wrote: On Wed, May 31, 2017 at 12:17:05PM -0500, Christopher Bostic wrote: Hi Greg, Are there any further changes you require for this patch set? This has been extensively tested internally and all is working as expected. Would it be possible to move forward with

Re: [PATCH] arch/sparc: support NR_CPUS = 4096

Hi, David, On 06/04/2017 04:46 PM, David Miller wrote: From: Jane Chu Date: Thu, 1 Jun 2017 15:39:13 -0600 diff --git a/arch/sparc/kernel/irq_64.c b/arch/sparc/kernel/irq_64.c index 4d0248a..5b19108 100644 --- a/arch/sparc/kernel/irq_64.c +++

Re: [PATCH] arch/sparc: support NR_CPUS = 4096

Hi, David, On 06/04/2017 04:46 PM, David Miller wrote: From: Jane Chu Date: Thu, 1 Jun 2017 15:39:13 -0600 diff --git a/arch/sparc/kernel/irq_64.c b/arch/sparc/kernel/irq_64.c index 4d0248a..5b19108 100644 --- a/arch/sparc/kernel/irq_64.c +++ b/arch/sparc/kernel/irq_64.c @@ -1034,12

Re: [PATCH 3.18 01/33] Revert "stackprotector: Increase the per-task stack canarys random range from 32 bits to 64 bits on 64-bit platforms"

On Mon, Jun 5, 2017 at 9:16 AM, Greg Kroah-Hartman wrote: > 3.18-stable review patch. If anyone has any objections, please let me know. > > -- > > From: Greg Kroah-Hartman > > This reverts commit

Re: [PATCH 3.18 01/33] Revert "stackprotector: Increase the per-task stack canarys random range from 32 bits to 64 bits on 64-bit platforms"

On Mon, Jun 5, 2017 at 9:16 AM, Greg Kroah-Hartman wrote: > 3.18-stable review patch. If anyone has any objections, please let me know. > > -- > > From: Greg Kroah-Hartman > > This reverts commit 609a3e81550b0b4ea87197b0f59455a7bcff975a which is > commit

[PATCH v6 6/6] platform/x86: intel_bxtwc_tmu: Remove first level IRQ unmask

From: Kuppuswamy Sathyanarayanan Currently in WCOVE PMIC MFD driver, all second level IRQ chips are chained to the respective first level IRQs. So there is no need for explicitly unmasking the first level IRQ in this driver. This patches removes this

[PATCH v6 6/6] platform/x86: intel_bxtwc_tmu: Remove first level IRQ unmask

From: Kuppuswamy Sathyanarayanan Currently in WCOVE PMIC MFD driver, all second level IRQ chips are chained to the respective first level IRQs. So there is no need for explicitly unmasking the first level IRQ in this driver. This patches removes this level 1 IRQ unmask support. Signed-off-by:

[PATCH v6 1/6] mfd: intel_soc_pmic_bxtwc: Fix TMU interrupt index

From: Kuppuswamy Sathyanarayanan TMU interrupts are registered as a separate interrupt chip, and hence it should start its interrupt index(BXTWC_TMU_IRQ) number from 0. But currently, BXTWC_TMU_IRQ is defined as part of enum bxtwc_irqs_level2 and its

[PATCH v6 1/6] mfd: intel_soc_pmic_bxtwc: Fix TMU interrupt index

From: Kuppuswamy Sathyanarayanan TMU interrupts are registered as a separate interrupt chip, and hence it should start its interrupt index(BXTWC_TMU_IRQ) number from 0. But currently, BXTWC_TMU_IRQ is defined as part of enum bxtwc_irqs_level2 and its index value is 11. Since this index value is

[PATCH v6 2/6] mfd: intel_soc_pmic_bxtwc: Remove thermal second level IRQs

From: Kuppuswamy Sathyanarayanan Since all second level thermal IRQs are consumed by the same device(bxt_wcove_thermal), there is no need to expose them as separate interrupts. We can just export only the first level IRQs for thermal and let the

[PATCH v6 3/6] mfd: intel_soc_pmic_bxtwc: Remove second level IRQ for gpio device

From: Kuppuswamy Sathyanarayanan Currently all PMIC GPIO domain IRQs are consumed by the same device(bxt_wcove_gpio), so there is no need to export them as separate interrupts. We can just export only the first level GPIO IRQ(BXTWC_GPIO_LVL1_IRQ) as an

[PATCH v6 2/6] mfd: intel_soc_pmic_bxtwc: Remove thermal second level IRQs

From: Kuppuswamy Sathyanarayanan Since all second level thermal IRQs are consumed by the same device(bxt_wcove_thermal), there is no need to expose them as separate interrupts. We can just export only the first level IRQs for thermal and let the device(bxt_wcove_thermal) driver handle the second

[PATCH v6 3/6] mfd: intel_soc_pmic_bxtwc: Remove second level IRQ for gpio device

From: Kuppuswamy Sathyanarayanan Currently all PMIC GPIO domain IRQs are consumed by the same device(bxt_wcove_gpio), so there is no need to export them as separate interrupts. We can just export only the first level GPIO IRQ(BXTWC_GPIO_LVL1_IRQ) as an IRQ resource and let the GPIO device

[PATCH v6 4/6] mfd: intel_soc_pmic_bxtwc: Utilize devm_* functions in driver probe

From: Kuppuswamy Sathyanarayanan Cleanup the resource allocation/free code in probe function by using devm_* calls. Signed-off-by: Kuppuswamy Sathyanarayanan Acked-for-MFD-by: Lee Jones

[PATCH v6 4/6] mfd: intel_soc_pmic_bxtwc: Utilize devm_* functions in driver probe

From: Kuppuswamy Sathyanarayanan Cleanup the resource allocation/free code in probe function by using devm_* calls. Signed-off-by: Kuppuswamy Sathyanarayanan Acked-for-MFD-by: Lee Jones Reviewed-by: Andy Shevchenko --- drivers/mfd/intel_soc_pmic_bxtwc.c | 54

[PATCH v6 5/6] mfd: intel_soc_pmic_bxtwc: Use chained IRQs for second level IRQ chips

From: Kuppuswamy Sathyanarayanan Whishkey cove PMIC has support to mask/unmask interrupts at two levels. At first level we can mask/unmask interrupt domains like TMU, GPIO, ADC, CHGR, BCU THERMAL and PWRBTN and at second level, it provides facility to

[PATCH v6 0/6] mfd: intel_soc_pmic_bxtwc: Add chained IRQ support

From: Kuppuswamy Sathyanarayanan Following patch set adds chained IRQ support to WCOVE PMIC driver. Changes since v3: * Added fix for typec wcove driver. Changes since v4: * Squashed following two commits, to keep the patch set bisectable. usb:

[PATCH v6 5/6] mfd: intel_soc_pmic_bxtwc: Use chained IRQs for second level IRQ chips

From: Kuppuswamy Sathyanarayanan Whishkey cove PMIC has support to mask/unmask interrupts at two levels. At first level we can mask/unmask interrupt domains like TMU, GPIO, ADC, CHGR, BCU THERMAL and PWRBTN and at second level, it provides facility to mask/unmask individual interrupts belong

[PATCH v6 0/6] mfd: intel_soc_pmic_bxtwc: Add chained IRQ support

From: Kuppuswamy Sathyanarayanan Following patch set adds chained IRQ support to WCOVE PMIC driver. Changes since v3: * Added fix for typec wcove driver. Changes since v4: * Squashed following two commits, to keep the patch set bisectable. usb: typec: typec_wcove: Use charger irq chip to

Re: [PATCH 1/3] Documentation: DT: add Keystone DSP remoteproc binding

On Mon, Jun 5, 2017 at 1:21 PM, Suman Anna wrote: > Hi Rob, > >>> >>> On 05/31/2017 02:12 PM, Rob Herring wrote: On Fri, May 26, 2017 at 11:53:15AM -0500, Suman Anna wrote: > Add the device tree bindings document for the Texas Instrument's > Keystone 2 DSP remoteproc

Re: [PATCH 1/3] Documentation: DT: add Keystone DSP remoteproc binding

On Mon, Jun 5, 2017 at 1:21 PM, Suman Anna wrote: > Hi Rob, > >>> >>> On 05/31/2017 02:12 PM, Rob Herring wrote: On Fri, May 26, 2017 at 11:53:15AM -0500, Suman Anna wrote: > Add the device tree bindings document for the Texas Instrument's > Keystone 2 DSP remoteproc devices. >

[PATCH 00/10] patches for fpga

Hi Greg, Please take these patches for FPGA that have been reviewed on the mailing lists. Thanks, Alan Anatolij Gustschin (1): fpga: Add flag to indicate SPI bitstream is bit-reversed Joel Holdsworth (1): of: Add vendor prefix for Lattice Semiconductor Joshua Clayton (5): doc: dt:

[PATCH 00/10] patches for fpga

Hi Greg, Please take these patches for FPGA that have been reviewed on the mailing lists. Thanks, Alan Anatolij Gustschin (1): fpga: Add flag to indicate SPI bitstream is bit-reversed Joel Holdsworth (1): of: Add vendor prefix for Lattice Semiconductor Joshua Clayton (5): doc: dt:

[PATCH 02/10] Make FPGA a menuconfig to ease disabling it all

From: Vincent Legoll No need to get into the submenu to disable all FPGA-related config entries Signed-off-by: Vincent Legoll Acked-by: Moritz Fischer Signed-off-by: Alan Tull --- drivers/fpga/Kconfig | 6

[PATCH 03/10] fpga: allow to compile-test Altera FPGA bridge drivers

From: Tobias Klauser Add COMPILE_TEST to the Kconfig entry for the Altera SoCFPGA FPGA Bridge. The Altera FPGA Freeze Bridge can also be used on Altera PEIe FPGAs, so the driver shouldn't depend on ARCH_SOCFPGA in the first place. This allows test-compiling the drivers on

[PATCH 02/10] Make FPGA a menuconfig to ease disabling it all

From: Vincent Legoll No need to get into the submenu to disable all FPGA-related config entries Signed-off-by: Vincent Legoll Acked-by: Moritz Fischer Signed-off-by: Alan Tull --- drivers/fpga/Kconfig | 6 +- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git

[PATCH 03/10] fpga: allow to compile-test Altera FPGA bridge drivers

From: Tobias Klauser Add COMPILE_TEST to the Kconfig entry for the Altera SoCFPGA FPGA Bridge. The Altera FPGA Freeze Bridge can also be used on Altera PEIe FPGAs, so the driver shouldn't depend on ARCH_SOCFPGA in the first place. This allows test-compiling the drivers on other architectures to

[PATCH 05/10] doc: dt: document altera-passive-serial binding

From: Joshua Clayton Describe an altera-passive-serial devicetree entry, required features Signed-off-by: Joshua Clayton Acked-by: Rob Herring Signed-off-by: Alan Tull ---

[PATCH 01/10] dt-bindings: fpga: Add bindings document for Xilinx LogiCore PR Decoupler

From: Moritz Fischer This adds the binding documentation for the Xilinx LogiCORE PR Decoupler soft core. Signed-off-by: Moritz Fischer Signed-off-by: Michal Simek Cc: Sören Brinkmann Cc:

[PATCH 05/10] doc: dt: document altera-passive-serial binding

From: Joshua Clayton Describe an altera-passive-serial devicetree entry, required features Signed-off-by: Joshua Clayton Acked-by: Rob Herring Signed-off-by: Alan Tull --- .../bindings/fpga/altera-passive-serial.txt| 29 ++ 1 file changed, 29 insertions(+)

[PATCH 01/10] dt-bindings: fpga: Add bindings document for Xilinx LogiCore PR Decoupler

From: Moritz Fischer This adds the binding documentation for the Xilinx LogiCORE PR Decoupler soft core. Signed-off-by: Moritz Fischer Signed-off-by: Michal Simek Cc: Sören Brinkmann Cc: linux-kernel@vger.kernel.org Cc: devicet...@vger.kernel.org Acked-by: Rob Herring Signed off-by: Alan

[PATCH 07/10] ARM: dts: imx6q-evi: support altera-ps-spi

From: Joshua Clayton Add support for Altera FPGA connected to an spi port to the evi devicetree file Signed-off-by: Joshua Clayton Signed-off-by: Alan Tull --- arch/arm/boot/dts/imx6q-evi.dts | 16 1 file

[PATCH 07/10] ARM: dts: imx6q-evi: support altera-ps-spi

From: Joshua Clayton Add support for Altera FPGA connected to an spi port to the evi devicetree file Signed-off-by: Joshua Clayton Signed-off-by: Alan Tull --- arch/arm/boot/dts/imx6q-evi.dts | 16 1 file changed, 16 insertions(+) diff --git

[PATCH 04/10] fpga: Add flag to indicate SPI bitstream is bit-reversed

From: Anatolij Gustschin Add a flag that is passed to the write_init() callback, indicating that the SPI bitstream starts with LSB first. SPI controllers usually send data with MSB first. If an FPGA expects bitstream data as LSB first, the data must be reversed either by the SPI

Re: [PATCH v2 2/2] pinctrl: sprd: Add Spreadtrum pin control driver

Hi Baolin, [auto build test WARNING on robh/for-next] [also build test WARNING on v4.12-rc4] [cannot apply to pinctrl/devel next-20170605] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/Baolin

[PATCH 04/10] fpga: Add flag to indicate SPI bitstream is bit-reversed

From: Anatolij Gustschin Add a flag that is passed to the write_init() callback, indicating that the SPI bitstream starts with LSB first. SPI controllers usually send data with MSB first. If an FPGA expects bitstream data as LSB first, the data must be reversed either by the SPI controller or by

Re: [PATCH v2 2/2] pinctrl: sprd: Add Spreadtrum pin control driver

Hi Baolin, [auto build test WARNING on robh/for-next] [also build test WARNING on v4.12-rc4] [cannot apply to pinctrl/devel next-20170605] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/Baolin

[PATCH 06/10] fpga manager: Add altera-ps-spi driver for Altera FPGAs

From: Joshua Clayton altera-ps-spi loads FPGA firmware over SPI, using the "passive serial" interface on Altera Arria 10, Cyclone V or Stratix V FPGAs. This is one of the simpler ways to set up an FPGA at runtime. The signal interface is close to unidirectional SPI

[PATCH 06/10] fpga manager: Add altera-ps-spi driver for Altera FPGAs

From: Joshua Clayton altera-ps-spi loads FPGA firmware over SPI, using the "passive serial" interface on Altera Arria 10, Cyclone V or Stratix V FPGAs. This is one of the simpler ways to set up an FPGA at runtime. The signal interface is close to unidirectional SPI with lsb first.

[PATCH 10/10] of: Add vendor prefix for Lattice Semiconductor

From: Joel Holdsworth Lattice Semiconductor Corporation is a manufacturer of integrated circuits and IP products, including low-power FPGAs, video connectivity devices and millimeter wave wireless products. Website: http://latticesemi.com Signed-off-by: Joel

[PATCH 08/10] lib: add bitrev8x4()

From: Joshua Clayton Add a function to reverse bytes within a 32 bit word. Operate on a u32 rather than individual bytes. Signed-off-by: Joshua Clayton Signed-off-by: Alan Tull --- include/linux/bitrev.h | 19

[PATCH 10/10] of: Add vendor prefix for Lattice Semiconductor

From: Joel Holdsworth Lattice Semiconductor Corporation is a manufacturer of integrated circuits and IP products, including low-power FPGAs, video connectivity devices and millimeter wave wireless products. Website: http://latticesemi.com Signed-off-by: Joel Holdsworth Acked-by: Rob Herring

[PATCH 08/10] lib: add bitrev8x4()

From: Joshua Clayton Add a function to reverse bytes within a 32 bit word. Operate on a u32 rather than individual bytes. Signed-off-by: Joshua Clayton Signed-off-by: Alan Tull --- include/linux/bitrev.h | 19 +++ 1 file changed, 19 insertions(+) diff --git

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