Add support for Moxa UC-8100-ME-T open platform
The UC-8100-ME-T computing platform is designed
for embedded data acquisition industrial applications
The features of UC-8100-ME-T series are:
* eMMC
* SPI flash
* SD slot
* 2x LAN
* 2 RS-232/422/485 ports, software-selectable
* Mini PCIe form facto
Hi Dave,
Commits
663ebbf63180 "drm/amdgpu: trace VM flags as 64bits"
5327dd8acf05 "drm/amdgpu: remove stale TODO comment"
eabd76cef900 "drm/amd/sched: print sched job id in amd_sched_job trace"
a69c7e0138fc "drm/amdgpu: update pctl1 ram index/data for mmhub on raven"
7504938f8e73 "drm/a
Hi Kishon,
On 2017/8/2 13:03, Kishon Vijay Abraham I wrote:
Hi,
On Tuesday 01 August 2017 01:42 PM, Frank Wang wrote:
The registers of usb-phy are distributed in grf and usbgrf on some
Rockchip SoCs (e.g RV1108), this patch add a quirk to support this
companion grf design.
Signed-off-by: Fran
Hi LinusW and Rob,
On 14 July 2017 at 16:08, Baolin Wang wrote:
> In some scenarios, we should set some pins as input/output/pullup/pulldown
> when the specified system goes into deep sleep mode, then when the system
> goes into deep sleep mode, these pins will be set automatically by hardware.
>
This patchset includes following function points:
1: Let usermodehelper function possible to set pid namespace
done by: [PATCH_v4.1_1/3] Make call_usermodehelper_exec possible
to set namespaces
2: Let pipe_type core_pattern write dump into container's rootfs
done by: [PATCH_v4.1_2/3] Limit
Hi all,
Changes since 20170801:
The drm-misc tree gained a conflict against Linus' tree.
The tip tree gained a conflict against the fbdev tree.
The tty tree gained a conflict against the tty.current tree.
I again reverted a commit from the staging tree that was causing overnight
Current call_usermodehelper_work() can not set namespaces for
the executed program.
This patch add above function for call_usermodehelper_work().
The init_intermediate is introduced for init works which should
be done before fork(). So that we get a method to set namespaces
for children. The clean
Currently when we set core_pattern to a pipe, the pipe program is
forked by kthread running with root's permission, and write dumpfile
into host's filesystem.
Same thing happened for container, the dumper and dumpfile are also
in host(not in container).
It have following program:
1: Not consistent
Currently, each container shared one copy of coredump setting
with the host system, if host system changed the setting, each
running containers will be affected.
Same story happened when container changed core_pattern, both
host and other container will be affected.
For container based on namespac
Hi,
On Thursday 27 July 2017 04:26 AM, Jon Mason wrote:
> From: Yendapally Reddy Dhananjaya Reddy
>
> This patch adds support for Broadcom NS2 USB3 PHY
>
> Signed-off-by: Yendapally Reddy Dhananjaya Reddy
>
> Signed-off-by: Jon Mason
> ---
> drivers/phy/broadcom/Kconfig| 9 +
>
Hi Steve,
I am using a 3.10 based kernel, and when I enable function_graph with one
particular x86_64 machine, I encounter rcu_sched stall.
echo function_graph > /sys/kernel/debug/tracing/current_tracer
echo 1 > /sys/kernel/debug/tracing/tracing_on
If I use 4.13-rc2, then its better, but stil
Hi all,
On Wed, 2 Aug 2017 15:45:54 +1000 Stephen Rothwell
wrote:
>
> On Tue, 01 Aug 2017 09:08:01 -0400 "Zi Yan" wrote:
> >
> > I found two possible fixes.
> >
> > 1. This uses C++ zero initializer, GCC is OK with it.
> > I tested with GCC 4.9.3 (has the initialization bug) and GCC 6.4.0.
> >
Signed-off-by: H. Nikolaus Schaller
---
drivers/misc/Kconfig | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 8136dc7e863d..41781d61eac7 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -5,10 +5,13 @@
menu "M
Enable the gmac2phy, make the gmac2phy work on
the rk3328-evb board.
Signed-off-by: David Wu
---
arch/arm64/boot/dts/rockchip/rk3328-evb.dts | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-evb.dts
b/arch/arm64/boot/dts/rockchip/rk3328-e
Hello I have some minor comment below
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
in alphabetic order please
[...]
> +static int rockchip_init_tstmode(struct phy_device *phydev)
> +{
> + int ret;
> +
> + /* Enable access to Analog and DSP register ba
The gmac2phy controller of rk3328 is connected to internal phy
directly inside, add the node for the internal phy support.
Signed-off-by: David Wu
---
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 25 +
1 file changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/rockc
This patch enables the internal phy for rk3228 evb board
by default.
To use the external 1000M phy on evb board, need to make
some switch of evb board to be on.
Signed-off-by: David Wu
---
arch/arm/boot/dts/rk3228-evb.dts | 20
1 file changed, 20 insertions(+)
diff --git a/
This patch adds internal mac phy clock and internal mac phy reset
for rk gmac using.
Signed-off-by: David Wu
---
arch/arm/boot/dts/rk322x.dtsi | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
index f3e4ffd..
There are two mac controllers in the rk3328, the one connects
to external phy, and the other one connects to internal phy.
Like the mac of external phy, the internal phy's mac also needs to
configure the related mac registers at GRF.
Signed-off-by: David Wu
---
drivers/net/ethernet/stmicro/stmma
There is only one mac controller in rk3228, which could connect to
external phy or internal phy, use the grf_com_mux bit15 to route
external/internal phy.
Signed-off-by: David Wu
---
drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 12
1 file changed, 12 insertions(+)
diff --git a/
To make internal phy work, need to configure the phy_clock,
phy cru_reset and related registers.
Signed-off-by: David Wu
---
.../devicetree/bindings/net/rockchip-dwmac.txt | 6 +-
drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 81 ++
2 files changed, 86 insertions(
66AK2G SoC has ECAP subsystem that is used as pwm-backlight provider for
display. Hence, enable pwm-tiecap driver to be built for Keystone
architecture.
Signed-off-by: Vignesh R
---
drivers/pwm/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pwm/Kconfig b/driv
This is wrong setting for rk3328_set_to_rmii(), so remove it.
Signed-off-by: David Wu
---
drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index f0
Make the rockchip phy driver built into the kernel.
Signed-off-by: David Wu
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 6c7d147..925bd478 100644
--- a/arch/arm64/configs/defconfig
+++ b/arc
Support internal ethernet phy currently.
Signed-off-by: David Wu
---
drivers/net/phy/Kconfig| 5 +
drivers/net/phy/Makefile | 1 +
drivers/net/phy/rockchip.c | 229 +
3 files changed, 235 insertions(+)
create mode 100644 drivers/net/phy/rock
Enable the rockchip phy for multi_v7_defconfig builds.
Signed-off-by: David Wu
---
arch/arm/configs/multi_v7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/multi_v7_defconfig
b/arch/arm/configs/multi_v7_defconfig
index 4d19c1b..94d7e71 100644
--- a/arch/arm/confi
The rk3228 and rk3328 support internal phy inside, let's enable
it to work. And the internal phy need to do some special setting, so
register the rockchip internal phy driver.
David Wu (11):
net: phy: Add rockchip phy driver support
multi_v7_defconfig: Make rockchip phy built-in
arm64: defco
On Tue 01-08-17 18:52:42, Michal Hocko wrote:
> On Wed 02-08-17 00:30:33, Tetsuo Handa wrote:
[...]
> > > - if (gfp_pfmemalloc_allowed(gfp_mask))
> > > - alloc_flags = ALLOC_NO_WATERMARKS;
> > > + /*
> > > + * Distinguish requests which really need access to whole memory
> > > + * reserve
On 07/19/2017 05:17 PM, Abhishek Sahu wrote:
The memset in clear_read_regs is overhead. All the register data
will be filled by DMA during NAND operation so making these
register variables zero is not required.
Yeah, that's a good point.
Reviewed-by: Archit Taneja
Signed-off-by: Abhishek
On Tue, 2017-08-01 at 17:14 +0800, Yingjoe Chen wrote:
>
> Hi Zhiyong,
>
>
>
> On Mon, 2017-07-31 at 16:22 +0800, Zhiyong Tao wrote:
> <...>
> > 3)Add "spec_dir_set" and "spec_dir_get" in "mtk_pinctrl_devdata".
> > 4)Change "spec_dir_set" and add "spec_dir_get" in "pinctrl-mt2701.c"
> > and "
On 07/19/2017 05:17 PM, Abhishek Sahu wrote:
Each NAND page consist of multiple codewords. Following is
sequence for NAND page write according to hardware guide.
1. Program Power-up configuration, page row, page column
address and flash configuration registers.
2. Write NAND_FLASH_CMD foll
On Mon, Jul 24, 2017 at 10:56:44PM -0700, Bjorn Andersson wrote:
> This driver register as a subsystem restart notifier and will send out
> notifications to remote processors that has opened the "glink_ssr" GLINK
> channel.
>
> This mechanism is used to signal any GLINK participants that a 3rd par
On 07/19/2017 05:17 PM, Abhishek Sahu wrote:
Each NAND page consist of multiple codewords. Following is
sequence for NAND page read according to hardware guide.
1. Program Power-up configuration, page row, page column
address and flash configuration registers.
2. Write NAND_FLASH_CMD followed
Hi,
On Tuesday 01 August 2017 11:31 PM, Santosh Shilimkar wrote:
> On 7/31/2017 9:54 PM, Vignesh R wrote:
>> This series adds support for Cadence QSPI for 66AK2G SoC. The first
>> three patches enhance the cadence-quadspi driver to support loopback
>> clock and pm_runtime and tweaks for 66AK2G SoC
On 07/19/2017 05:17 PM, Abhishek Sahu wrote:
Currently the compatible “qcom,nandcs” is being used for each
connected NAND device to support for multiple NAND devices in the
same bus. The same thing can be achieved by looking reg property
for each sub nodes which contains the chip select number
Hi YASUAKI,
On Tue, Aug 01, 2017 at 03:21:38PM -0400, YASUAKI ISHIMATSU wrote:
> Hi Joey,
>
> On 07/23/2017 05:18 AM, joeyli wrote:
[...snip]
> >>>
> >>
> >> At least Yasuaki raised similar behavior for container in 2013.
> >> It's similar to the DVD player case, user space application needs
> >>
On 07/19/2017 05:17 PM, Abhishek Sahu wrote:
The current driver is failing without complete bootchain since
NAND_DEV_CMD_VLD value is not valid.
Reviewed-by: Archit Taneja
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/qcom_nandc.c | 4
1 file changed, 4 insertions(+)
diff --
On 07/19/2017 05:17 PM, Abhishek Sahu wrote:
The configuration for BCH is not correct in the current driver.
The ECC_CFG_ECC_DISABLE bit defines whether to enable or disable the
BCH ECC in which
0x1 : BCH_DISABLED
0x0 : BCH_ENABLED
But currently host->bch_enabled is being assi
From: mohamedalrshah
Date: Wed, 2 Aug 2017 12:37:01 +0800
> +//#define NS_PROTOCOL "tcp_agilesd.c"
> +//#include "../ns-linux-c.h"
> +//#include "../ns-linux-util.h"
> +//#include
There is no way this submission will be considered seriously with all of
this cruft in it.
Your new module needs
Hi Zi,
On Tue, 01 Aug 2017 09:08:01 -0400 "Zi Yan" wrote:
>
> I found two possible fixes.
>
> 1. This uses C++ zero initializer, GCC is OK with it.
> I tested with GCC 4.9.3 (has the initialization bug) and GCC 6.4.0.
>
> --- a/include/linux/swapops.h~a
> +++ a/include/linux/swapops.h
> @@ -217
- Original Message -
> From: "Eric Dumazet"
> To: "Paolo Bonzini"
> Cc: linux-kernel@vger.kernel.org, "Peter Zijlstra"
> Sent: Tuesday, August 1, 2017 10:52:14 PM
> Subject: Re: [PATCH 2/3] jump_labels: do not use unserialized
> static_key_enabled
>
> On Tue, 2017-08-01 at 17:24 +020
This patch adds Broadcom FlexRM low-level reset for
VFIO platform.
It will do the following:
1. Disable/Deactivate each FlexRM ring
2. Flush each FlexRM ring
The cleanup sequence for FlexRM rings is adapted from
Broadcom FlexRM mailbox driver.
Signed-off-by: Anup Patel
Reviewed-by: Oza Oza
Rev
This patchset primarily adds Broadcom FlexRM reset module for
VFIO platform driver.
The patches are based on Linux-4.13-rc3 and can also be
found at flexrm-vfio-v4 branch of
https://github.com/Broadcom/arm64-linux.git
Changes since v3:
- Improve "depends on" for Kconfig option
VFIO_PLATFORM_B
On Wed, Aug 2, 2017 at 10:39 AM, Kishon Vijay Abraham I wrote:
> Vivek,
>
> On Monday 31 July 2017 10:58 AM, Vivek Gautam wrote:
>> Hi Kishon,
>>
>>
>> On Tue, Jun 20, 2017 at 11:27 AM, Vivek Gautam
>> wrote:
>>> Fixing the clk enable failure path in qcom_qmp_phy_init()
>>> and cleanup the reset
On Tue, Aug 01, 2017 at 10:14:08AM +0800, jiaheng.fan wrote:
The purpose of the title is to describe the change, ERR010812 doesnt mean
anything to wider audience, so please describe the change in title and log
while keeping the errate number and details..
> ERR010812:
> Enqueue rejection occurs a
On Tue, Aug 01, 2017 at 10:14:07AM +0800, jiaheng.fan wrote:
> +#define FSL_QDMA_DMR 0x0
> +#define FSL_QDMA_DSR 0x4
> +#define FSL_QDMA_DEIER 0xe00
> +#define FSL_QDMA_DEDR0xe04
> +#define FSL_QDMA_DECFDW0R0
> -Original Message-
> From: platform-driver-x86-ow...@vger.kernel.org [mailto:platform-driver-
> x86-ow...@vger.kernel.org] On Behalf Of
> sathyanarayanan.kuppusw...@linux.intel.com
> Sent: Tuesday, August 1, 2017 11:44 PM
> To: x...@kernel.org; mi...@redhat.com; Zha, Qipeng
> ; h...@zyt
On Monday 17 July 2017 06:50 AM, Chanwoo Choi wrote:
> This patch replaces the deprecated extcon API as following:
> - extcon_set_cable_state_() -> extcon_get_state()
>
> Cc: Kishon Vijay Abraham I
> Cc: Raviteja Garimella
> Signed-off-by: Chanwoo Choi
Acked-by: Kishon Vijay Abraham I
> ---
On Monday 17 July 2017 06:50 AM, Chanwoo Choi wrote:
> This patch uses the resource-managed extcon API for extcon_register_notifier()
> and replaces the deprecated extcon API as following:
> - extcon_get_cable_state_() -> extcon_get_state()
> - extcon_set_cable_state_() -> extcon_set_state_sync()
Vivek,
On Monday 31 July 2017 10:58 AM, Vivek Gautam wrote:
> Hi Kishon,
>
>
> On Tue, Jun 20, 2017 at 11:27 AM, Vivek Gautam
> wrote:
>> Fixing the clk enable failure path in qcom_qmp_phy_init()
>> and cleanup the reset control deassertion failure path in
>> qcom_qmp_phy_com_init().
>>
>> Fixe
Hi Chen,
On Wed, Aug 02, 2017 at 11:17:19AM +0800, Chen Zhong wrote:
> This patch add support to handle MediaTek PMIC MT6397/MT6323 key
> interrupts including pwrkey and homekey, also add setting for
> long press key shutdown behavior.
>
> Signed-off-by: Chen Zhong
> ---
> drivers/input/keyboar
Hi,
On Monday 31 July 2017 12:04 PM, Varadarajan Narayanan wrote:
> v6:
> Added 'Reviewed-by: Vivek Gautam ' and fixed
> white space issues as mentioned by Vivek.
> phy: qcom-qmp: Fix phy pipe clock name
> dt-bindings: phy: qmp: Add support for QMP phy in IPQ8074
merged the 1st fo
On Tue, Aug 1, 2017 at 6:26 AM, SZ Lin wrote:
> Add support for Moxa UC-8100-ME-T open platform
>
> The UC-8100-ME-T computing platform is designed
> for embedded data acquisition industrial applications
>
> The features of UC-8100-ME-T series are:
> * eMMC
> * SPI flash
> * SD slot
> * 2x LAN
> *
PERHATIAN
Kotak surat Anda telah melebihi batas penyimpanan, yaitu 5 GB seperti yang
didefinisikan oleh administrator, yang saat ini berjalan pada 10.9GB, Anda
mungkin tidak dapat mengirim atau menerima surat baru sampai Anda kembali
memvalidasi email mailbox Anda. Untuk memvalidasi ulang kotak
在 2017-08-02 12:47，Jernej Škrabec 写道：
Hi Icenowy,
Dne torek, 01. avgust 2017 ob 15:12:58 CEST je Icenowy Zheng
napisal(a):
As we have already the support for the DE2 on Allwinner H3, add the
display engine pipeline device tree nodes to its DTSI file.
The H5 pipeline has some differences and w
On Tue, Aug 01, 2017 at 10:14:05AM +0800, jiaheng.fan wrote:
> The FSL qDMA controller transfers blocks of data between one source
> and one destination.The blocks of data transferred can be represented
> in memory as contiguous or noncontiguous using scatter/gather table(s).
> Channel virtualizati
PERHATIAN
Kotak surat Anda telah melebihi batas penyimpanan, yaitu 5 GB seperti yang
didefinisikan oleh administrator, yang saat ini berjalan pada 10.9GB, Anda
mungkin tidak dapat mengirim atau menerima surat baru sampai Anda kembali
memvalidasi email mailbox Anda. Untuk memvalidasi ulang kotak
Hi,
On Tuesday 01 August 2017 01:42 PM, Frank Wang wrote:
> The registers of usb-phy are distributed in grf and usbgrf on some
> Rockchip SoCs (e.g RV1108), this patch add a quirk to support this
> companion grf design.
>
> Signed-off-by: Frank Wang
> ---
> .../bindings/phy/phy-rockchip-inno-us
在 2017-08-02 12:53，Jernej Škrabec 写道：
Hi Icenowy,
Dne torek, 01. avgust 2017 ob 15:12:52 CEST je Icenowy Zheng
napisal(a):
Allwinner H3 features a "Display Engine 2.0".
Add device tree bindings for the following parts:
- H3 TCONs
- H3 Mixers
- H3 Display engine
Signed-off-by: Icenowy Zheng
Hi Matthias,
On Tue, 2017-08-01 at 16:06 +0200, Matthias Brugger wrote:
> Hi Erin,
>
> On 08/01/2017 09:03 AM, Erin Lo wrote:
> > This patch series based on v4.13-rc1, include MT2701 ethernet/disp
> > bls/display/usb3 function DT nodes.
> >
> > Chunfeng Yun (1):
> >arm: dts: mt2701: Add usb
Hi Icenowy,
Dne torek, 01. avgust 2017 ob 15:12:52 CEST je Icenowy Zheng napisal(a):
> Allwinner H3 features a "Display Engine 2.0".
>
> Add device tree bindings for the following parts:
> - H3 TCONs
> - H3 Mixers
> - H3 Display engine
>
> Signed-off-by: Icenowy Zheng
> ---
> .../bindings/disp
PERHATIAN
Kotak surat Anda telah melebihi batas penyimpanan, yaitu 5 GB seperti yang
didefinisikan oleh administrator, yang saat ini berjalan pada 10.9GB, Anda
mungkin tidak dapat mengirim atau menerima surat baru sampai Anda kembali
memvalidasi email mailbox Anda. Untuk memvalidasi ulang kotak
On Tue, Aug 01, 2017 at 09:32:50AM +, Pierre Yves MORDRET wrote:
>
>
> On 07/31/2017 02:31 PM, Vinod Koul wrote:
> > On Wed, Jul 26, 2017 at 07:38:02AM +, Pierre Yves MORDRET wrote:
> >> +
> >> +#ifndef __DMA_STM32_DMAMUX_H
> >> +#define __DMA_STM32_DMAMUX_H
> >> +
> >
On Mon, Jul 31, 2017 at 09:35:53AM -0700, Dave Jiang wrote:
> On 07/31/2017 05:34 AM, Vinod Koul wrote:
> >
> > Are you asking for using DMA_PREP_CMD, for that I think should be ok
> >
> > If you asking about adding a new flag with DMA_PREP_CMD, then it would no
>
> Vinod, I wonder if we should
Check user-given gpio number and reject it before
calling gpio_to_desc() because gpio_to_desc() is
for kernel driver and it expects given gpio number
is valid (means 0 to 511).
If given number is invalid, gpio_to_desc() calls
WARN() and dump registers and stack for debug.
This means user can easily
Hi Icenowy,
Dne torek, 01. avgust 2017 ob 15:12:58 CEST je Icenowy Zheng napisal(a):
> As we have already the support for the DE2 on Allwinner H3, add the
> display engine pipeline device tree nodes to its DTSI file.
>
> The H5 pipeline has some differences and will be enabled later.
>
> Signed-
Hi João Paulo,
On Tue, 2017-08-01 at 15:58 -0700, João Paulo Rechi Vita wrote:
> Hello Luca,
>
> On Mon, Jul 24, 2017 at 4:01 AM, Coelho, Luciano
> wrote:
> > On Fri, 2017-07-21 at 07:51 -0700, João Paulo Rechi Vita wrote:
>
> (...)
>
> > > Currently these messages are presented to the user d
On Tue, Aug 1, 2017 at 9:12 PM, Icenowy Zheng wrote:
> Allwinner H3 features a "Display Engine 2.0", which needs some support
> to be present in the DRM driver.
>
> This patchset is now a basical version, which dropped some features I
> used to submitted:
> - TVE support (not so high priority now)
For the AST2500 and compatible watchdog controllers the external reset
signal can be configured for push-pull or open-drain drive types, and in
the case of push-pull driving, active low or high.
Signed-off-by: Andrew Jeffery
---
Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt | 10
Hello,
This two-patch series builds on top of Chris Bostic's changes introducing the
aspeed,external-signal devicetree property (currently v5):
https://lkml.org/lkml/2017/7/17/777
Additional characteristics such as pulse width, push-pull vs open-drain driving
and active high or low polarity
Add support for configuring the drive strength and polarity on the
AST2500, and the pulse duration on both the AST2400 and AST2500.
Signed-off-by: Andrew Jeffery
Tested-by: Matt Spinler
---
drivers/watchdog/aspeed_wdt.c | 105 --
1 file changed, 102 inser
On Tue, 1 Aug 2017 23:44:13 -0400
Sinan Kaya wrote:
> An endpoint is allowed to issue Configuration Request Retry Status (CRS)
> following a Function Level Reset (FLR) request to indicate that it is
> not ready to accept new requests. CRS is defined in PCIe r3.1, sec 2.3.1.
> Request Handling Ru
Published:
Alrshah, M.A., Othman, M., Ali, B. and Hanapi, Z.M., 2015. Agile-SD: a
Linux-based
TCP congestion control algorithm for supporting high-speed and short-distance
networks.
Journal of Network and Computer Applications, 55, pp.181-190.
Agile-SD is a new loss-based and RTT-independent TC
On Sat, Jul 29, 2017 at 10:17 PM, wrote:
> From: Marcus Cooper
>
> The sun8i-h3 introduces a lot of changes to the i2s block such
> as different register locations, extended clock division and
> more operational modes. As we have to consider the earlier
> implementation then these changes need t
Published:
Alrshah, M.A., Othman, M., Ali, B. and Hanapi, Z.M., 2015. Agile-SD: a
Linux-based
TCP congestion control algorithm for supporting high-speed and short-distance
networks.
Journal of Network and Computer Applications, 55, pp.181-190.
Agile-SD is a new loss-based and RTT-independent TC
On Mon, 2017-07-17 at 14:25 -0500, Christopher Bostic wrote:
> Describe device tree optional properties:
>
> * aspeed,reset-type = "cpu|soc|system|none"
> One of three different, mutually exclusive, values
>
> "cpu" : ARM CPU reset on signal
> "soc" : 'System on chip' reset
>
Hi Greg,
Today's linux-next merge of the tty tree got a conflict in:
drivers/tty/serial/8250/8250_core.c
between commit:
9527b82ae3af ("Revert "serial: Delete dead code for CIR serial ports"")
from the tty.current tree and commit:
c7ac15ce8924 ("serial: core: move UPF_NO_TXEN_TEST to qu
Minchan Kim writes:
> From 0ffbd3c8769fdf56e2f14908f890f9d1703ed32e Mon Sep 17 00:00:00 2001
> From: Minchan Kim
> Date: Tue, 25 Jul 2017 15:15:18 +0900
> Subject: [PATCH] zram: do not free pool->size_class
>
> Mike reported kernel goes oops with ltp:zram03 testcase.
...
>
> He bisected the probl
Declare fiemap_for_stripe as static to fix sparse warnings:
> warning: symbol 'fiemap_for_stripe' was not declared. Should it be
> static?
Signed-off-by: David Wittman
---
drivers/staging/lustre/lustre/lov/lov_object.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git
On Wed, Aug 02, 2017 at 09:28:20AM +0900, Akinobu Mita wrote:
>Commit 1203c8e6fb0a ("fault-inject: simplify access check for fail-nth")
>unintentionally broke a conditional statement in should_fail(). Any faults
>are not injected in the task context by the change when the systematic
>fault injecti
On Mon, Jul 24, 2017 at 02:07:51PM -0500, Brijesh Singh wrote:
> From: Tom Lendacky
>
> In order for memory pages to be properly mapped when SEV is active, we
> need to use the PAGE_KERNEL protection attribute as the base protection.
> This will insure that memory mapping of, e.g. ACPI tables, re
On Sat, Jul 29, 2017 at 10:17 PM, wrote:
> From: Marcus Cooper
>
> The default value of the config register is different on newer
> SoCs and therefore enabling/disabling with a register write
> will clear bits used to set the direction of the clock and frame
> pins.
>
> Signed-off-by: Marcus Coo
внимания;
Ваши сообщения превысил лимит памяти, который составляет 5 Гб, определенных
администратором, который в настоящее время работает на 10.9GB, Вы не сможете
отправить или получить новую почту, пока вы повторно не проверить ваш почтовый
ящик почты. Чтобы восстановить работоспособность Ваше
On Tuesday 01 August 2017 11:40 PM, Santosh Shilimkar wrote:
>
> On 7/31/2017 9:41 PM, Lokesh Vutla wrote:
>> This series adds DT nodes and documentation for eDMA and MMC IPs on
>> Keystone 66AK2G SoC. Also enable the required configs in
>> keystone_defconfig.
>>
>> This series depends on Keerth
On Sat, Jul 29, 2017 at 10:17 PM, wrote:
> From: Marcus Cooper
>
> The newer SoCs do not have this setting. Instead they set the pin
> direction. Add a check to see if the bit is valid and if so set
> it accordingly.
>
> Signed-off-by: Marcus Cooper
> ---
> sound/soc/sunxi/sun4i-i2s.c | 38 +++
On 28-07-17, 10:36, Sébastien Szymanski wrote:
> Setting the frequency higher than 528Mhz actually sets the ARM
> clock to 528MHz. That's because PLL2 is used as the root clock when the
> frequency is higher than 396MHz.
>
> cpupower frequency-set -f 792000
>
> arm_clk_root on the CCM_CLKO2 signa
Hi David, Florian, Andrew
(resent in plain text)
On Fri, Jul 28, 2017 at 2:56 PM, David.Wu wrote:
>
> Hi Florian,
>
> 在 2017/7/28 0:54, Florian Fainelli 写道:
>>
>> - if you need knowledge about this PHY connection type prior to binding
>> the PHY device and its driver (that is, before of_phy_conn
On 08/02/2017 12:22 AM, Heiko Stuebner wrote:
From: Elaine Zhang
From Rockchips fractional divider description:
3.1.9 Fractional divider usage
To get specific frequency, clocks of I2S, SPDIF, UARTcan be generated by
fractional divider. Generally you must set that denominator is 20
hi,heiko:
This a good solution.And I tested it on RK SOCs.It's work well.
On 08/02/2017 12:21 AM, Heiko Stuebner wrote:
From: Elaine Zhang
Fractional dividers may have special requirements concerning numerator
and denominator selection that differ from just getting the best
approximation.
Fo
Code is currently allowing PCIe devices to extend polling time up to 1
second. Reducing the wait time for virtual functions to 100ms maximum to
satisfy spec requirement mentioned in PCIe r3.1, sec 6.6.2. Function-Level
Reset (FLR).
SR-IOV r1.1, sec 2.2.2 also mentions that the virtual function's p
On 01-08-17, 16:30, Pavan Kondeti wrote:
> Currently sugov threads in the schedutil governor are pinned to the
> policy CPUs. schedutil can now make use of this new
> dvfs_possible_from_any_cpu flag and avoid the pinning, right?
Actually yes and it would be something as simple as below. Will send
An endpoint is allowed to issue Configuration Request Retry Status (CRS)
following a Function Level Reset (FLR) request to indicate that it is
not ready to accept new requests. CRS is defined in PCIe r3.1, sec 2.3.1.
Request Handling Rules and CRS usage in FLR context is mentioned in
PCIe r3.1, sec
On 08/01/2017 03:29 PM, Alexey Brodkin wrote:
It is necessary to explicitly set both SLC_AUX_RGN_START1 and SLC_AUX_RGN_END1
which hold MSB bits of the physical address correspondingly of region start
and end otherwise SLC region operation is executed in unpredictable manner,
for example on HSDK
On Sat, Jul 29, 2017 at 10:17 PM, wrote:
> From: Marcus Cooper
>
> On the newer SoCs the bits to configure the operational mode are
The subject says "format". Which is it? And please be clear what
"mode" or "format" this configures. Is it the DAI controller's
overall mode (PCM/I2S/Left-Justifie
Hi,
I am observing following rcu_sched stall while executing `perf record -a --
sleep 1` with one of the arm64 platform. It looks like that stalled cpu was
waiting in csd_lock_wait() from where it never came out,and so the stall. Any
help/pointer for further debugging would be very helpful. P
Fix minor typos in comments.
Signed-off-by: NeilBrown
---
drivers/staging/lustre/lustre/llite/namei.c | 2 +-
drivers/staging/lustre/lustre/mdc/mdc_locks.c | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/staging/lustre/lustre/llite/namei.c
b/drivers/staging/l
Many of the inlines in dcache.h were changed to accept
const struct pointers in commit f0d3b3ded999 ("constify dcache.c
inlined helpers where possible").
This patch allows 'const' in a couple that were added since then.
Signed-off-by: NeilBrown
---
include/linux/dcache.h | 4 ++--
1 file change
Hi all,
Today's linux-next merge of the tip tree got a conflict in:
drivers/video/fbdev/core/fbmem.c
between commit:
6104c37094e7 ("fbcon: Make fbcon a built-time depency for fbdev")
from the fbdev tree and commit:
95cf9264d5f3 ("x86, drm, fbdev: Do not specify encrypted memory for vide
On 01-08-17, 20:48, Leonard Crestez wrote:
> > > I found this by enabling the power:cpu_frequency tracepoint event and
> > > checking for deltas with a script. Enabling CPU_FREQ_STAT show this:
> > >
> > > time_in_state:
> > >
> > > 396000 1609
> > So we still stay at the lowest frequency most of
'lapic_irq' is a local variable and its 'level' field isn't
initialized, so 'level' is random, it doesn't matter but
makes UBSAN unhappy:
UBSAN: Undefined behaviour in .../lapic.c:...
load of value 10 is not a valid value for type '_Bool'
...
Call Trace:
[] dump_stack+0x1e/0x20
[] ubsan_epilogue
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