On 12/06/18 09:59 AM, Jon Mason wrote:
>> Patches for ntb_pingpong and ntb_perf follow (which are broken
>> otherwise) to support hardware that doesn't have port numbers. This is
>> important not only to not break support with existing drivers but for
>> the cross link topology which, due to
Now that the sole use of the whole smpboot_*cpumask() API is gone,
remove it.
Suggested-by: Oleg Nesterov
Signed-off-by: Peter Zijlstra (Intel)
---
include/linux/smpboot.h | 15 -
kernel/smpboot.c| 54
2 files changed, 6
- On Jun 12, 2018, at 9:11 AM, Florian Weimer fwei...@redhat.com wrote:
> On 06/11/2018 10:04 PM, Mathieu Desnoyers wrote:
>> - On Jun 11, 2018, at 3:55 PM, Florian Weimer fwei...@redhat.com wrote:
>>
>>> On 06/11/2018 09:49 PM, Mathieu Desnoyers wrote:
It should be noted that there
Oleg explains the reason we could hit park+park is that
smpboot_update_cpumask_percpu_thread()'s
for_each_cpu_and(cpu, , cpu_online_mask)
smpboot_park_kthread();
turns into:
for ((cpu) = 0; (cpu) < 1; (cpu)++, (void)mask, (void)and)
smpboot_park_kthread();
on UP, ignoring
Gaurav reports that commit:
85f1abe0019f ("kthread, sched/wait: Fix kthread_parkme() completion issue")
isn't working for him. Because of the following race:
> controller Thread CPUHP Thread
> takedown_cpu
> kthread_park
> kthread_parkme
> Set KTHREAD_SHOULD_PARK
Changes since last time:
- folded the smp_call_on_cpu() fix
- re-add missing softlockup_threads_initialized check
- rewrote changelog for completion revert
Oleg suggested to replace the "watchdog/%u" threads with
cpu_stop_work. That removes one thread per cpu while at the same time
fixes softlockup vs SCHED_DEADLINE.
But more importantly, it does away with the single
smpboot_update_cpumask_percpu_thread() user, which allows
cleanups/shrinkage of the
On 12/06/18 09:59 AM, Jon Mason wrote:
>> Patches for ntb_pingpong and ntb_perf follow (which are broken
>> otherwise) to support hardware that doesn't have port numbers. This is
>> important not only to not break support with existing drivers but for
>> the cross link topology which, due to
On Thu, Jun 7, 2018 at 4:09 PM, Stefan Popa wrote:
> The AD5758 is a single channel DAC with 16-bit precision which uses the SPI
> interface that operates at clock rates up to 50MHz.
>
> The output can be configured as voltage or current and is available on a
> single terminal.
>
> Datasheet:
>
On Thu, Jun 7, 2018 at 4:09 PM, Stefan Popa wrote:
> The AD5758 is a single channel DAC with 16-bit precision which uses the SPI
> interface that operates at clock rates up to 50MHz.
>
> The output can be configured as voltage or current and is available on a
> single terminal.
>
> Datasheet:
>
Hi, Linus,
Please pull from
git://git.kernel.org/pub/scm/linux/kernel/git/evalenti/linux-soc-
thermal.git linus
to receive the latest Thermal SoC management updates for v4.18-rc1 with
top-most commit 6d7c70d1cd6526dc79e3d3b3faae1c40c1681168:
thermal: qcom: tsens: Allow number of sensors to
Hi, Linus,
Please pull from
git://git.kernel.org/pub/scm/linux/kernel/git/evalenti/linux-soc-
thermal.git linus
to receive the latest Thermal SoC management updates for v4.18-rc1 with
top-most commit 6d7c70d1cd6526dc79e3d3b3faae1c40c1681168:
thermal: qcom: tsens: Allow number of sensors to
Use sign_extend32 kernel function instead of code duplication,
Safe also for 16 bit. and remove declaration of bits variable not needed.
Signed-off-by: Karim Eshapa
>On Tue, 2018-06-12 at 01:38 +0200, Karim Eshapa wrote:
>> Use sign_extend32 kernel function instead of code duplication.
>> Safe
Use sign_extend32 kernel function instead of code duplication,
Safe also for 16 bit. and remove declaration of bits variable not needed.
Signed-off-by: Karim Eshapa
>On Tue, 2018-06-12 at 01:38 +0200, Karim Eshapa wrote:
>> Use sign_extend32 kernel function instead of code duplication.
>> Safe
On 12/06/18 09:48 AM, Jon Mason wrote:
> ntb.c is more of a glue layer, and this is more device specific.
> While I like adding it here for more common code, it should probably
> reside in the ntb_hw_*.c files to enforce the hw specific code all
> reside in that layer. So, this probably needs
On 12/06/18 09:48 AM, Jon Mason wrote:
> ntb.c is more of a glue layer, and this is more device specific.
> While I like adding it here for more common code, it should probably
> reside in the ntb_hw_*.c files to enforce the hw specific code all
> reside in that layer. So, this probably needs
From: Anna-Maria Gleixner
There are in-tree users of refcount_dec_and_lock() which must acquire the
spin lock with interrupts disabled. To workaround the lack of an irqsave
variant of refcount_dec_and_lock() they use local_irq_save() at the call
site. This causes extra code and creates in some
From: Anna-Maria Gleixner
There are in-tree users of refcount_dec_and_lock() which must acquire the
spin lock with interrupts disabled. To workaround the lack of an irqsave
variant of refcount_dec_and_lock() they use local_irq_save() at the call
site. This causes extra code and creates in some
From: Anna-Maria Gleixner
There are in-tree users of atomic_dec_and_lock() which must acquire the
spin lock with interrupts disabled. To workaround the lack of an irqsave
variant of atomic_dec_and_lock() they use local_irq_save() at the call
site. This causes extra code and creates in some
From: Anna-Maria Gleixner
There are in-tree users of atomic_dec_and_lock() which must acquire the
spin lock with interrupts disabled. To workaround the lack of an irqsave
variant of atomic_dec_and_lock() they use local_irq_save() at the call
site. This causes extra code and creates in some
This patchset introduces atomic_dec_and_lock_irqsave() and
refcount_dec_and_lock_irqsave(). The individual user are not part of
this series.
The custom Alpha implementation of atomic_dec_and_lock() is removed
because the decrement operation is not a RELEASE operation (pointed out
by Peter
This patchset introduces atomic_dec_and_lock_irqsave() and
refcount_dec_and_lock_irqsave(). The individual user are not part of
this series.
The custom Alpha implementation of atomic_dec_and_lock() is removed
because the decrement operation is not a RELEASE operation (pointed out
by Peter
On Tue, Jun 12, 2018 at 03:22:42PM +, Bart Van Assche wrote:
> On Tue, 2018-05-15 at 09:00 -0700, Matthew Wilcox wrote:
> > diff --git a/drivers/scsi/qla2xxx/qla_target.c
> > b/drivers/scsi/qla2xxx/qla_target.c
> > index 025dc2d3f3de..cdf671c2af61 100644
> > ---
On Tue, Jun 12, 2018 at 03:22:42PM +, Bart Van Assche wrote:
> On Tue, 2018-05-15 at 09:00 -0700, Matthew Wilcox wrote:
> > diff --git a/drivers/scsi/qla2xxx/qla_target.c
> > b/drivers/scsi/qla2xxx/qla_target.c
> > index 025dc2d3f3de..cdf671c2af61 100644
> > ---
Hi, Linus,
Please pull from
git://git.kernel.org/pub/scm/linux/kernel/git/rzhang/linux.git next
to receive the latest Thermal Management updates for v4.18-rc1 with
top-most commit e9ed3ee61aa62ce280aadeeea1ec959f0c66a290:
Merge branches 'thermal-core' and 'thermal-intel' into next
Hi, Linus,
Please pull from
git://git.kernel.org/pub/scm/linux/kernel/git/rzhang/linux.git next
to receive the latest Thermal Management updates for v4.18-rc1 with
top-most commit e9ed3ee61aa62ce280aadeeea1ec959f0c66a290:
Merge branches 'thermal-core' and 'thermal-intel' into next
On Fri, Jun 8, 2018 at 8:08 PM, Logan Gunthorpe wrote:
> When the commit adding ntb_default_port_number() and
> ntb_default_peer_port_number() entered the kernel there was no
> users of it so it was impossible to tell what the API needed.
>
> When a user finally landed a year later
On Fri, Jun 8, 2018 at 8:08 PM, Logan Gunthorpe wrote:
> When the commit adding ntb_default_port_number() and
> ntb_default_peer_port_number() entered the kernel there was no
> users of it so it was impossible to tell what the API needed.
>
> When a user finally landed a year later
On Tue, Jun 12, 2018 at 04:37:17PM +0200, Daniel Lezcano wrote:
> On 12/06/2018 16:06, Peter Zijlstra wrote:
> > On Tue, Jun 12, 2018 at 03:02:14PM +0200, Daniel Lezcano wrote:
> >> On 12/06/2018 14:52, Peter Zijlstra wrote:
> >>> In this case, you can do:
> >>
> >> That is what we had before but
On Tue, Jun 12, 2018 at 04:37:17PM +0200, Daniel Lezcano wrote:
> On 12/06/2018 16:06, Peter Zijlstra wrote:
> > On Tue, Jun 12, 2018 at 03:02:14PM +0200, Daniel Lezcano wrote:
> >> On 12/06/2018 14:52, Peter Zijlstra wrote:
> >>> In this case, you can do:
> >>
> >> That is what we had before but
On Tue, Jun 12, 2018 at 5:10 AM, Wu Hao wrote:
Hi Hao,
> Documentation/ABI/testing/sysfs-class-fpga-manager | 24 +++
> drivers/fpga/fpga-mgr.c| 28
> ++
> include/linux/fpga/fpga-mgr.h | 9 +++
> 3
On Tue, Jun 12, 2018 at 5:10 AM, Wu Hao wrote:
Hi Hao,
> Documentation/ABI/testing/sysfs-class-fpga-manager | 24 +++
> drivers/fpga/fpga-mgr.c| 28
> ++
> include/linux/fpga/fpga-mgr.h | 9 +++
> 3
On Tue, Jun 12, 2018 at 5:10 AM, Wu Hao wrote:
> For feature devices drivers, both the FPGA Management Engine (FME) and
> Accelerated Function Unit (AFU) driver need to expose user interfaces via
> the device file, for example, mmap and ioctls.
>
> This patch adds chardev support in the dfl
On Tue, Jun 12, 2018 at 5:10 AM, Wu Hao wrote:
> For feature devices drivers, both the FPGA Management Engine (FME) and
> Accelerated Function Unit (AFU) driver need to expose user interfaces via
> the device file, for example, mmap and ioctls.
>
> This patch adds chardev support in the dfl
On Tue 12 Jun 06:23 PDT 2018, Niklas Cassel wrote:
> Add a dummy qcom_scm_assign_mem() to enable building drivers when
> CONFIG_COMPILE_TEST=y && CONFIG_QCOM_SCM=n.
>
> All other qcom_scm_* functions already have a dummy version.
>
> Signed-off-by: Niklas Cassel
Reviewed-by: Bjorn Andersson
On Tue 12 Jun 06:23 PDT 2018, Niklas Cassel wrote:
> Add a dummy qcom_scm_assign_mem() to enable building drivers when
> CONFIG_COMPILE_TEST=y && CONFIG_QCOM_SCM=n.
>
> All other qcom_scm_* functions already have a dummy version.
>
> Signed-off-by: Niklas Cassel
Reviewed-by: Bjorn Andersson
On 12/06/18 16:24, Sudeep Holla wrote:
On Tue, Jun 12, 2018 at 3:55 PM, Srinivas Kandagatla
wrote:
GICR_WAKER can be a secured register, check this before accessing it
as its done in power management code.
Without this patch Qualcomm DB820c board crashes.
Are you sure this is the one
On 12/06/18 16:24, Sudeep Holla wrote:
On Tue, Jun 12, 2018 at 3:55 PM, Srinivas Kandagatla
wrote:
GICR_WAKER can be a secured register, check this before accessing it
as its done in power management code.
Without this patch Qualcomm DB820c board crashes.
Are you sure this is the one
On Mon, Jun 11, 2018 at 10:54:17AM -0700, Roman Gushchin wrote:
> Explicitly propagate effective memory min/low values down by the tree.
>
> If there is the global memory pressure, it's not really necessary.
> Effective memory guarantees will be propagated automatically as we
> traverse memory
On Mon, Jun 11, 2018 at 10:54:17AM -0700, Roman Gushchin wrote:
> Explicitly propagate effective memory min/low values down by the tree.
>
> If there is the global memory pressure, it's not really necessary.
> Effective memory guarantees will be propagated automatically as we
> traverse memory
On Fri, Jun 8, 2018 at 8:08 PM, Logan Gunthorpe wrote:
> Commit 417cf39cfea9 ("NTB: Set dma mask and dma coherent mask to NTB
> devices") added code to set the DMA mask for the NTB device
> to each driver individually. However, it neglected to set it for the
> Switchtec driver. So when the
On Fri, Jun 8, 2018 at 8:08 PM, Logan Gunthorpe wrote:
> Commit 417cf39cfea9 ("NTB: Set dma mask and dma coherent mask to NTB
> devices") added code to set the DMA mask for the NTB device
> to each driver individually. However, it neglected to set it for the
> Switchtec driver. So when the
On Tue 12 Jun 07:48 PDT 2018, Srinivas Kandagatla wrote:
> Access to UART0 is disabled by bootloaders. By leaving it enabled by
> default would reboot the board.
> Disable this for now, this would alteast give a board which boots.
>
> Signed-off-by: Srinivas Kandagatla
Reviewed-by: Bjorn
On Tue 12 Jun 07:48 PDT 2018, Srinivas Kandagatla wrote:
> Access to UART0 is disabled by bootloaders. By leaving it enabled by
> default would reboot the board.
> Disable this for now, this would alteast give a board which boots.
>
> Signed-off-by: Srinivas Kandagatla
Reviewed-by: Bjorn
On Tue, Jun 12, 2018 at 5:10 AM, Wu Hao wrote:
> Device Feature List (DFL) defines a feature list structure that creates
> a link list of feature headers within the MMIO space to provide an
> extensible way of adding features. This patch introduces a kernel module
> to provide basic
On Tue, Jun 12, 2018 at 5:10 AM, Wu Hao wrote:
> Device Feature List (DFL) defines a feature list structure that creates
> a link list of feature headers within the MMIO space to provide an
> extensible way of adding features. This patch introduces a kernel module
> to provide basic
Adding a flag which will use the kernels's idle
page tracking to mark pages idle. As the tool already
prints the idle flag if set, subsequent runs will show
which pages have been accessed since last run.
Signed-off-by: Christian Hansen
---
tools/vm/page-types.c | 47
Adding a flag which will use the kernels's idle
page tracking to mark pages idle. As the tool already
prints the idle flag if set, subsequent runs will show
which pages have been accessed since last run.
Signed-off-by: Christian Hansen
---
tools/vm/page-types.c | 47
Adding a new flag that will read kpagecount for each PFN
and print out the number of time the page is mapped along
with the flags in the listing view.
Signed-off-by: Christian Hansen
---
tools/vm/page-types.c | 73 +--
1 file changed, 59
Adding a new flag that will read kpagecount for each PFN
and print out the number of time the page is mapped along
with the flags in the listing view.
Signed-off-by: Christian Hansen
---
tools/vm/page-types.c | 73 +--
1 file changed, 59
On Tue, 2018-06-12 at 16:53 +0200, Jiri Kosina wrote:
> On Sun, 10 Jun 2018, Srinivas Pandruvada wrote:
>
> > From: Even Xu
> >
> > Current ish driver only register resume/suspend PM callbacks which
> > don't support hibernation (suspend to disk). Now use the
> > SIMPLE_DEV_PM_OPS() MACRO
On Tue, 2018-06-12 at 16:53 +0200, Jiri Kosina wrote:
> On Sun, 10 Jun 2018, Srinivas Pandruvada wrote:
>
> > From: Even Xu
> >
> > Current ish driver only register resume/suspend PM callbacks which
> > don't support hibernation (suspend to disk). Now use the
> > SIMPLE_DEV_PM_OPS() MACRO
Those pins would be used by many boards.
Signed-off-by: Randy Li
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 97 +++-
1 file changed, 83 insertions(+), 14 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
Those pins would be used by many boards.
Signed-off-by: Randy Li
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 97 +++-
1 file changed, 83 insertions(+), 14 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
Hi,
On 06/12/2018 03:10 AM, Wu Hao wrote:
>
> diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> index a0aa163..e3b140e 100644
> --- a/drivers/fpga/Kconfig
> +++ b/drivers/fpga/Kconfig
> @@ -174,6 +174,15 @@ config FPGA_DFL_FME_REGION
> help
> Say Y to enable FPGA Region
Hi,
On 06/12/2018 03:10 AM, Wu Hao wrote:
>
> diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> index a0aa163..e3b140e 100644
> --- a/drivers/fpga/Kconfig
> +++ b/drivers/fpga/Kconfig
> @@ -174,6 +174,15 @@ config FPGA_DFL_FME_REGION
> help
> Say Y to enable FPGA Region
Hi,
On 06/12/2018 03:10 AM, Wu Hao wrote:
> From: Kang Luwei
>
>
> diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> index 5faab48..45e9220 100644
> --- a/drivers/fpga/Kconfig
> +++ b/drivers/fpga/Kconfig
> @@ -146,6 +146,16 @@ config FPGA_DFL
> Gate Array (FPGA) solutions
Hi,
On 06/12/2018 03:10 AM, Wu Hao wrote:
> From: Kang Luwei
>
>
> diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> index 5faab48..45e9220 100644
> --- a/drivers/fpga/Kconfig
> +++ b/drivers/fpga/Kconfig
> @@ -146,6 +146,16 @@ config FPGA_DFL
> Gate Array (FPGA) solutions
Hi,
On 06/12/2018 03:10 AM, Wu Hao wrote:
>
> diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> index ee9c542..4052532 100644
> --- a/drivers/fpga/Kconfig
> +++ b/drivers/fpga/Kconfig
> @@ -130,4 +130,20 @@ config OF_FPGA_REGION
> Support for loading FPGA images by applying a
Hi,
On 06/12/2018 03:10 AM, Wu Hao wrote:
> From: Zhang Yi
>
> diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> index 4052532..5faab48 100644
> --- a/drivers/fpga/Kconfig
> +++ b/drivers/fpga/Kconfig
> @@ -146,4 +146,19 @@ config FPGA_DFL
> Gate Array (FPGA) solutions which
Hi,
On 06/12/2018 03:10 AM, Wu Hao wrote:
>
> diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> index ee9c542..4052532 100644
> --- a/drivers/fpga/Kconfig
> +++ b/drivers/fpga/Kconfig
> @@ -130,4 +130,20 @@ config OF_FPGA_REGION
> Support for loading FPGA images by applying a
Hi,
On 06/12/2018 03:10 AM, Wu Hao wrote:
> From: Zhang Yi
>
> diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> index 4052532..5faab48 100644
> --- a/drivers/fpga/Kconfig
> +++ b/drivers/fpga/Kconfig
> @@ -146,4 +146,19 @@ config FPGA_DFL
> Gate Array (FPGA) solutions which
On 6/12/18 3:17 AM, Stefan Agner wrote:
> [also added Jens Axboe]
>
> On 12.06.2018 10:27, Boris Brezillon wrote:
>> On Tue, 12 Jun 2018 10:06:42 +0200
>> Stefan Agner wrote:
>>
>>> On 12.06.2018 02:03, Dmitry Osipenko wrote:
On Monday, 11 June 2018 23:52:22 MSK Stefan Agner wrote:
>
On 6/12/18 3:17 AM, Stefan Agner wrote:
> [also added Jens Axboe]
>
> On 12.06.2018 10:27, Boris Brezillon wrote:
>> On Tue, 12 Jun 2018 10:06:42 +0200
>> Stefan Agner wrote:
>>
>>> On 12.06.2018 02:03, Dmitry Osipenko wrote:
On Monday, 11 June 2018 23:52:22 MSK Stefan Agner wrote:
>
On Tue, Jun 12, 2018 at 3:55 PM, Srinivas Kandagatla
wrote:
> GICR_WAKER can be a secured register, check this before accessing it
> as its done in power management code.
>
> Without this patch Qualcomm DB820c board crashes.
>
Are you sure this is the one causing the crash ?
As per GIC
On Tue, Jun 12, 2018 at 3:55 PM, Srinivas Kandagatla
wrote:
> GICR_WAKER can be a secured register, check this before accessing it
> as its done in power management code.
>
> Without this patch Qualcomm DB820c board crashes.
>
Are you sure this is the one causing the crash ?
As per GIC
On Tue 12-06-18 16:08:03, Punit Agrawal wrote:
> Michal Hocko writes:
[...]
> > Well, the standard way to handle memory less NUMA nodes is to simply
> > fallback to the closest NUMA node. We even have an API for that
> > (numa_mem_id).
>
> CONFIG_HAVE_MEMORYLESS node is not enabled on arm64
On Tue 12-06-18 16:08:03, Punit Agrawal wrote:
> Michal Hocko writes:
[...]
> > Well, the standard way to handle memory less NUMA nodes is to simply
> > fallback to the closest NUMA node. We even have an API for that
> > (numa_mem_id).
>
> CONFIG_HAVE_MEMORYLESS node is not enabled on arm64
Tianyu Lan writes:
> Register tlb_remote_flush callback for vmcs when hyperv capability of
> nested guest mapping flush is detected. The interface can help to reduce
> overhead when flush ept table among vcpus for nested VM. The tradition way
> is to send IPIs to all affected vcpus and executes
Tianyu Lan writes:
> Register tlb_remote_flush callback for vmcs when hyperv capability of
> nested guest mapping flush is detected. The interface can help to reduce
> overhead when flush ept table among vcpus for nested VM. The tradition way
> is to send IPIs to all affected vcpus and executes
On Tue, 12 Jun 2018, Mikulas Patocka wrote:
>
>
> On Tue, 12 Jun 2018, Alan Stern wrote:
>
> > On Tue, 12 Jun 2018, Mikulas Patocka wrote:
> >
> > > I have a single-core machine with usb2 soundcard. When I increase mplayer
> > > priority (to real-time or high non-realtime priority), the sound
On Tue, 12 Jun 2018, Mikulas Patocka wrote:
>
>
> On Tue, 12 Jun 2018, Alan Stern wrote:
>
> > On Tue, 12 Jun 2018, Mikulas Patocka wrote:
> >
> > > I have a single-core machine with usb2 soundcard. When I increase mplayer
> > > priority (to real-time or high non-realtime priority), the sound
On 11.6.2018 14:36, Michal Vokáč wrote:
Ahoj,
To configure individual pad's characteristics on i.MX6 SoC a
fsl,pins = property can be used. Is there any convenient
way to configure the pad group control registers?
The issue is that some bits (DDR_SEL and ODT) in the individual RGMII pad
On 11.6.2018 14:36, Michal Vokáč wrote:
Ahoj,
To configure individual pad's characteristics on i.MX6 SoC a
fsl,pins = property can be used. Is there any convenient
way to configure the pad group control registers?
The issue is that some bits (DDR_SEL and ODT) in the individual RGMII pad
Michal Hocko writes:
> On Mon 11-06-18 08:43:03, Bjorn Helgaas wrote:
>> On Mon, Jun 11, 2018 at 08:32:10PM +0800, Xie XiuQi wrote:
>> > Hi Michal,
>> >
>> > On 2018/6/11 16:52, Michal Hocko wrote:
>> > > On Mon 11-06-18 11:23:18, Xie XiuQi wrote:
>> > >> Hi Michal,
>> > >>
>> > >> On 2018/6/7
Michal Hocko writes:
> On Mon 11-06-18 08:43:03, Bjorn Helgaas wrote:
>> On Mon, Jun 11, 2018 at 08:32:10PM +0800, Xie XiuQi wrote:
>> > Hi Michal,
>> >
>> > On 2018/6/11 16:52, Michal Hocko wrote:
>> > > On Mon 11-06-18 11:23:18, Xie XiuQi wrote:
>> > >> Hi Michal,
>> > >>
>> > >> On 2018/6/7
On Friday, June 8, 2018 6:04:13 AM CEST Viresh Kumar wrote:
> On 08-06-18, 09:07, Chen Yu wrote:
> > According to current code implementation, detecting the long
> > idle period is done by checking if the interval between two
> > adjacent utilization update handers is long enough. Although
> >
On Friday, June 8, 2018 6:04:13 AM CEST Viresh Kumar wrote:
> On 08-06-18, 09:07, Chen Yu wrote:
> > According to current code implementation, detecting the long
> > idle period is done by checking if the interval between two
> > adjacent utilization update handers is long enough. Although
> >
Tianyu Lan writes:
> Register tlb_remote_flush callback for vmcs when hyperv capability of
> nested guest mapping flush is detected. The interface can help to reduce
> overhead when flush ept table among vcpus for nested VM. The tradition way
> is to send IPIs to all affected vcpus and executes
Tianyu Lan writes:
> Register tlb_remote_flush callback for vmcs when hyperv capability of
> nested guest mapping flush is detected. The interface can help to reduce
> overhead when flush ept table among vcpus for nested VM. The tradition way
> is to send IPIs to all affected vcpus and executes
On Tuesday, June 5, 2018 11:42:38 PM CEST Srinivas Pandruvada wrote:
> v1 (Compared to RFC/RFT v3)
> - Minor suggestion for intel_pstate for coding
> - Add SKL desktop model used in some Xeons
>
> Tested-by: Giovanni Gherdovich
>
> This series has an overall positive performance impact on IO
On Tuesday, June 5, 2018 11:42:38 PM CEST Srinivas Pandruvada wrote:
> v1 (Compared to RFC/RFT v3)
> - Minor suggestion for intel_pstate for coding
> - Add SKL desktop model used in some Xeons
>
> Tested-by: Giovanni Gherdovich
>
> This series has an overall positive performance impact on IO
On Wednesday, June 6, 2018 6:09:29 AM CEST Viresh Kumar wrote:
> On 05-06-18, 13:44, Arnd Bergmann wrote:
> > Building the kryo cpufreq driver while QCOM_SMEM is a loadable module
> > results in a link error:
> >
> > drivers/cpufreq/qcom-cpufreq-kryo.o: In function `qcom_cpufreq_kryo_probe':
> >
On Wednesday, June 6, 2018 6:09:29 AM CEST Viresh Kumar wrote:
> On 05-06-18, 13:44, Arnd Bergmann wrote:
> > Building the kryo cpufreq driver while QCOM_SMEM is a loadable module
> > results in a link error:
> >
> > drivers/cpufreq/qcom-cpufreq-kryo.o: In function `qcom_cpufreq_kryo_probe':
> >
On Monday, June 4, 2018 9:11:41 AM CEST Viresh Kumar wrote:
> On 01-06-18, 14:05, Colin King wrote:
> > From: Colin Ian King
> >
> > The function acpi_cpufreq_fast_switch is local to the source and does
> > not need to be in global scope, so make it static.
> >
> > Cleans up sparse warning:
> >
On Monday, June 4, 2018 9:11:41 AM CEST Viresh Kumar wrote:
> On 01-06-18, 14:05, Colin King wrote:
> > From: Colin Ian King
> >
> > The function acpi_cpufreq_fast_switch is local to the source and does
> > not need to be in global scope, so make it static.
> >
> > Cleans up sparse warning:
> >
On Friday, June 1, 2018 12:21:42 AM CEST Suman Anna wrote:
> Hi Rafael,
>
> This is a repost of the v2 patches Ccing the proper linux-pm list.
> There are no code changes, I have picked up Viresh's acks and
> also added the stable kernel versions the first patch needs to be
> applied to.
>
>
On Friday, June 1, 2018 12:21:42 AM CEST Suman Anna wrote:
> Hi Rafael,
>
> This is a repost of the v2 patches Ccing the proper linux-pm list.
> There are no code changes, I have picked up Viresh's acks and
> also added the stable kernel versions the first patch needs to be
> applied to.
>
>
Alistair Strachan writes:
> On Mon, Jun 11, 2018 at 6:22 PM Eric W. Biederman
> wrote:
>>
>> Alistair Strachan writes:
>>
>> > In commit e94591d0d90c "proc: Convert proc_mount to use mount_ns"
>> > the parsing of mount parameters for the proc filesystem was broken.
>> >
>> > The SB_KERNMOUNT
On 12.06.2018 17:39, Kirill A. Shutemov wrote:
> Kernel need to have a way to access encrypted memory. We are going to
> use per-KeyID direct mapping to facilitate the access with minimal
> overhead.
>
> Direct mapping for each KeyID will be put next to each other in the
> virtual address
On Monday, June 11, 2018 7:38:27 AM CEST Shawn Guo wrote:
> On Tue, May 22, 2018 at 08:28:51AM +0200, Sébastien Szymanski wrote:
> > Check the max speed supported from the fuses for i.MX6ULL and update the
> > operating points table accordingly.
> >
> > Signed-off-by: Sébastien Szymanski
>
>
Alistair Strachan writes:
> On Mon, Jun 11, 2018 at 6:22 PM Eric W. Biederman
> wrote:
>>
>> Alistair Strachan writes:
>>
>> > In commit e94591d0d90c "proc: Convert proc_mount to use mount_ns"
>> > the parsing of mount parameters for the proc filesystem was broken.
>> >
>> > The SB_KERNMOUNT
On 12.06.2018 17:39, Kirill A. Shutemov wrote:
> Kernel need to have a way to access encrypted memory. We are going to
> use per-KeyID direct mapping to facilitate the access with minimal
> overhead.
>
> Direct mapping for each KeyID will be put next to each other in the
> virtual address
On Monday, June 11, 2018 7:38:27 AM CEST Shawn Guo wrote:
> On Tue, May 22, 2018 at 08:28:51AM +0200, Sébastien Szymanski wrote:
> > Check the max speed supported from the fuses for i.MX6ULL and update the
> > operating points table accordingly.
> >
> > Signed-off-by: Sébastien Szymanski
>
>
On Thursday, May 31, 2018 12:59:54 PM CEST Ulf Hansson wrote:
> Changes in v3:
> - Drop patch 1->4 as they have already been applied.
> - Collected tags, for tests and reviews.
> - Minor update to function descriptions in patch 4 (earlier 8) and 5
> (earlier9).
> -
On Thursday, May 31, 2018 12:59:54 PM CEST Ulf Hansson wrote:
> Changes in v3:
> - Drop patch 1->4 as they have already been applied.
> - Collected tags, for tests and reviews.
> - Minor update to function descriptions in patch 4 (earlier 8) and 5
> (earlier9).
> -
GICR_WAKER can be a secured register, check this before accessing it
as its done in power management code.
Without this patch Qualcomm DB820c board crashes.
Signed-off-by: Srinivas Kandagatla
---
drivers/irqchip/irq-gic-v3.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
GICR_WAKER can be a secured register, check this before accessing it
as its done in power management code.
Without this patch Qualcomm DB820c board crashes.
Signed-off-by: Srinivas Kandagatla
---
drivers/irqchip/irq-gic-v3.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
Hi James,
thanks for the review.
On 2018/6/11 21:36, James Morse wrote:
> Hi Dongjiu Geng,
>
> Please only put 'RESEND' in the subject if the patch content is identical.
> This patch is not the same as v4.
Yes, it should
>
> On 08/06/18 20:48, Dongjiu Geng wrote:
>> For the migrating VMs,
Hi James,
thanks for the review.
On 2018/6/11 21:36, James Morse wrote:
> Hi Dongjiu Geng,
>
> Please only put 'RESEND' in the subject if the patch content is identical.
> This patch is not the same as v4.
Yes, it should
>
> On 08/06/18 20:48, Dongjiu Geng wrote:
>> For the migrating VMs,
701 - 800 of 1386 matches
Mail list logo
