On Wed, 5 Jun 2019 at 18:54, Lukasz Luba wrote:
>
> Add new table rate for BPLL for Exynos5422 SoC supporting Dynamic Memory
> Controller frequencies for driver's DRAM timings.
>
> Acked-by: Chanwoo Choi
> Signed-off-by: Lukasz Luba
> ---
> drivers/clk/samsung/clk-exynos5420.c | 17
From: Yunsheng Lin
This patch adds a new hns3_get_new_flow_lvl function to calculate
the packet flow level, which is used to decide the interrupt
coalescence parameter, in order to make the flow level calculation
code more readable and make the future calculation ajdustment easier.
This patch-set includes code optimizations, cleanups and bugfixes for
the HNS3 ethernet controller driver.
[patch 1/12] logs more detail error info for ROCE RAS errors.
[patch 2/12] fixes a wrong size issue for mailbox responding.
[patch 3/12] makes HW GRO handing compliant with SW one.
[patch
From: Yunsheng Lin
This patch replaces numa_node_id with numa_mem_id when doing buffer
reusing checking, because the buffer still can be reused when the
buffer is from the nearest node and the local node has no memory
attached.
Signed-off-by: Yunsheng Lin
Signed-off-by: Peng Li
Signed-off-by:
From: Yunsheng Lin
Currently when a GRO packet is assembled by HW, the checksum is
modified to reflect the entire packet by HW and skb->ip_summed is
set to CHECKSUM_UNNECESSARY, which is not compliant with SW GRO.
This patch sets up skb's network and transport header, sets the
GRO packet's
From: Xiaofei Tan
This patch logs detail error info of ROCEE ECC and AXI errors for
debug purpose, and remove unnecessary reset for ROCEE overflow
errors.
Signed-off-by: Xiaofei Tan
Signed-off-by: Huazhong Tan
---
.../net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h | 2 +
From: Weihang Li
We trigger PF reset when a RAS error of NIC named over_8bd_nfe_err
occurred before. But it is possible that a VF causes that error, it's
reasonable to trigger VF reset instead of PF reset in this case.
This patch add detection of vf_id if a over_8bd_nfe_err occurs, if
vf_id is
From: Zhongzhu Liu
According to user manual, the maximum size of mailbox responding
data is 8 bytes, the macro HCLGE_MBX_MAX_RESP_DATA_SIZE
should be defined as 8 instead of 16.
Fixes: 9194d18b0577 ("net: hns3: fix the problem that the supported port is
empty")
Signed-off-by: Zhongzhu Liu
On Wed, 5 Jun 2019 at 18:54, Lukasz Luba wrote:
>
> Define new IDs for clocks used by Dynamic Memory Controller in
> Exynos5422 SoC.
>
> Acked-by: Rob Herring
> Acked-by: Chanwoo Choi
> Signed-off-by: Lukasz Luba
> ---
> include/dt-bindings/clock/exynos5420.h | 18 +-
> 1 file
From: Yufeng Mo
This patch adds some macros instead of magic numbers in serval places
Signed-off-by: Yufeng Mo
Signed-off-by: Weihang Li
Signed-off-by: Yunsheng Lin
Signed-off-by: Huazhong Tan
---
drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c | 5 ++-
From: Yufeng Mo
In order to make it more readable, this patch modifies PF/VF's
RSS hash key configuring function.
Signed-off-by: Yufeng Mo
Signed-off-by: Jian Shen
Signed-off-by: Weihang Li
Signed-off-by: Huazhong Tan
---
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 15
From: Yufeng Mo
This patch deletes some redundant code and refactors some bloated
functions.
Signed-off-by: Yufeng Mo
Signed-off-by: Weihang Li
Signed-off-by: Yonglong Liu
Signed-off-by: Huazhong Tan
---
drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c | 32 +++
From: Yonglong Liu
Since HNAE3_CLIENT_UNIC and HNAE3_DEV_UNIC is not used any more,
this patch removes the redundant codes.
Signed-off-by: Yonglong Liu
Signed-off-by: Peng Li
Signed-off-by: Huazhong Tan
---
drivers/net/ethernet/hisilicon/hns3/hnae3.c| 21 -
From: Jian Shen
In order to improve readability, this patch uses macros to
replace some magic numbers, and adds some comments for some
others.
Signed-off-by: Jian Shen
Signed-off-by: Peng Li
Signed-off-by: Huazhong Tan
---
.../ethernet/hisilicon/hns3/hns3pf/hclge_main.c| 118
From: Weihang Li
This patch fixes some coding style issues reported by some static code
analysis tools and code review, such as modify some comments, rename
some variables, log some errors in detail, and fixes some alignment
errors.
BTW, these cleanups do not change the logic of code.
Ravi Bangoria wrote:
Powerpc hw triggers watchpoint before executing the instruction.
To make trigger-after-execute behavior, kernel emulates the
instruction. If the instruction is 'load something into non-
volatile register', exception handler should restore emulated
register state while
On Thu, 6 Jun 2019 at 09:49, Quentin Perret wrote:
>
> Hi Vincent,
>
> On Thursday 06 Jun 2019 at 09:05:16 (+0200), Vincent Guittot wrote:
> > Hi Quentin,
> >
> > On Wed, 5 Jun 2019 at 19:21, Quentin Perret wrote:
> > >
> > > On Friday 17 May 2019 at 14:55:19 (-0700), Stephen Boyd wrote:
> > > >
Hi Sergei,
On Thursday, June 06, 2019 16:17 Sergei Shtylyov wrote:
>
> Hello!
>
> On 06.06.2019 5:54, Ran Wang wrote:
>
> > When DWC3 is set to host mode by programming register DWC3_GCTL, VBUS
> > (or its control signal) will turn on immediately on related Root Hub
> > ports. Then the VBUS
On 05.06.19 23:35, Jeff Kletsky wrote:
> From: Jeff Kletsky
>
> These Paragon chips are very similar to other 1Gb/2Gb chips
> in terms of their layout and command timings.
>
> One notable difference is that "Minimum number of valid blocks"
> (Nvb) is 1003 per Gb, rather than the common 1004. As
Hi,
On Thu, Jun 06, 2019 at 09:33:20AM +0800, anson.hu...@nxp.com wrote:
> From: Anson Huang
>
> Add the clock binding doc for i.MX8MN.
>
> Signed-off-by: Anson Huang
> ---
> Changes since V3:
> - switch binding doc from .txt to .yaml.
> ---
>
On 05.06.2019 09:04, Andrey Smirnov wrote:
> Simplify tc_set_video_mode() by replacing explicit shifting using
> macros from . No functional change intended.
>
> Signed-off-by: Andrey Smirnov
> Cc: Archit Taneja
> Cc: Andrzej Hajda
> Cc: Laurent Pinchart
> Cc: Tomi Valkeinen
> Cc: Andrey
On Thu, 2019-06-06 at 09:55 +0200, Rolf Eike Beer wrote:
> +CRYPTO_LIBS = $(shell $(PKG_CONFIG) --libs libcrypto 2> /dev/null ||
> -lcrypto)
That's going to run:
$ pkg-config --libs libcrypto || -lcrypto
If libcrypto.pc isn't there, it's going to get this:
-lcrypto: command not found
I
Hello!
On 06.06.2019 5:54, Ran Wang wrote:
When DWC3 is set to host mode by programming register DWC3_GCTL, VBUS
(or its control signal) will turn on immediately on related Root Hub
ports. Then the VBUS will be de-asserted for a little while during xhci
reset (conducted by xhci driver) for a
> This example really does point out a weakness in the LKMM's handling of
> data races. Herbert's litmus test is a great starting point:
>
>
> C xu
>
> {}
>
> P0(int *a, int *b)
> {
> WRITE_ONCE(*a, 1);
> synchronize_rcu();
> *b = 2;
> }
>
> P1(int *a, int *b)
> {
>
On Mon, 2019-06-03 at 12:57 +0200, Matthias Schiffer wrote:
> For some time (050d18d1c651 "ARM: 8650/1: module: handle negative
> R_ARM_PREL31 addends correctly", v4.11+), building a kernel without
> CONFIG_MODULE_UNLOAD would lead to module loads failing on ARM
> systems with
> certain memory
On 18/04/2019 16:36, Yue Haibing wrote:
> From: YueHaibing
>
> Fix sparse warning:
>
> drivers/phy/ti/phy-am654-serdes.c:250:12: warning:
> symbol 'serdes_am654_xlate' was not declared. Should it be static?
>
> Reported-by: Hulk Robot
> Signed-off-by: YueHaibing
Acked-by: Roger Quadros
On Thu, 06 Jun 2019, Bjorn Andersson wrote:
> On Wed 05 Jun 22:50 PDT 2019, Lee Jones wrote:
>
> > On Tue, 23 Apr 2019, Jeffrey Hugo wrote:
> >
> > > This adds the initial DT for the Lenovo Miix 630 laptop. Supported
> > > functionality includes USB (host), microSD-card, keyboard, and
On Thursday 06 Jun 2019 at 08:22:04 (+0530), Viresh Kumar wrote:
> On 05-06-19, 10:16, Quentin Perret wrote:
> > Hi Viresh,
> >
> > On Tuesday 04 Jun 2019 at 12:31:52 (+0530), Viresh Kumar wrote:
> > > The same formula to check utilization against capacity (after
> > > considering
On Thu, Jun 06, 2019 at 10:03:15AM +0200, Peter Zijlstra wrote:
> On Wed, Jun 05, 2019 at 01:52:15PM -0700, Linus Torvalds wrote:
> > On Wed, Jun 5, 2019 at 1:19 PM Peter Zijlstra wrote:
> > >
> > > Urgh, that's another things that's been on the TODO list for a long long
> > > time, write code to
On Fri, May 31, 2019 at 05:56:39PM +0800, Jason Wang wrote:
> On 2019/5/31 下午4:18, Stefano Garzarella wrote:
> > On Thu, May 30, 2019 at 07:59:14PM +0800, Jason Wang wrote:
> > > On 2019/5/30 下午6:10, Stefano Garzarella wrote:
> > > > On Thu, May 30, 2019 at 05:46:18PM +0800, Jason Wang wrote:
> >
Define the ring buffer size as a constant expression because it should
not depend on the guest page size.
Signed-off-by: Maya Nakamura
---
drivers/input/serio/hyperv-keyboard.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/input/serio/hyperv-keyboard.c
On Wed, 05 Jun 2019 12:14:50 -0700 (PDT)
David Miller wrote:
> From: Ivan Khoronzhuk
> Date: Wed, 5 Jun 2019 16:20:02 +0300
>
> > This patchset adds XDP support for TI cpsw driver and base it on
> > page_pool allocator. It was verified on af_xdp socket drop,
> > af_xdp l2f, ebpf XDP_DROP,
Define the ring buffer size as a constant expression because it should
not depend on the guest page size.
Signed-off-by: Maya Nakamura
---
drivers/hid/hid-hyperv.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/hid/hid-hyperv.c b/drivers/hid/hid-hyperv.c
index
On 6/1/2019 12:05 AM, Douglas Anderson wrote:
In commit abb621844f6a ("usb: ch9: make usb_endpoint_maxp() return
only packet size") the API to usb_endpoint_maxp() changed. It used to
just return wMaxPacketSize but after that commit it returned
wMaxPacketSize with the high bits (the multiplier)
Replace PAGE_SIZE with HV_HYP_PAGE_SIZE because the guest page size may
not be 4096 on all architectures and Hyper-V always runs with a page
size of 4096.
Signed-off-by: Maya Nakamura
---
drivers/hv/hyperv_vmbus.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git
at 15:55, Kai-Heng Feng wrote:
at 18:22, Kai-Heng Feng wrote:
at 00:01, Kai-Heng Feng wrote:
On Jan 30, 2019, at 16:21, Greg KH wrote:
On Thu, Jan 24, 2019 at 02:16:43PM +0800, Kai-Heng Feng wrote:
The QCA Rome USB Bluetooth controller has several issues once LPM gets
enabled:
- Fails
Introduce two new functions, hv_alloc_hyperv_page() and
hv_free_hyperv_page(), to allocate/deallocate memory with the size and
alignment that Hyper-V expects as a page. Although currently they are
not used, they are ready to be used to allocate/deallocate memory on x86
when their ARM64
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On Wed, Jun 05, 2019 at 01:16:46PM -0700, Linus Torvalds wrote:
> On Wed, Jun 5, 2019 at 6:49 AM Jan Glauber wrote:
> >
> > Add an upper bound to the loop to force the fallback to spinlocks
> > after some time. A retry value of 100 should not impact any hardware
> > that does not have this issue.
On Wed, Jun 05, 2019 at 01:52:15PM -0700, Linus Torvalds wrote:
> On Wed, Jun 5, 2019 at 1:19 PM Peter Zijlstra wrote:
> >
> > Urgh, that's another things that's been on the TODO list for a long long
> > time, write code to verify the alignment of allocations :/ I'm
> > suspecting quite a lot of
Define HV_HYP_PAGE_SHIFT, HV_HYP_PAGE_SIZE, and HV_HYP_PAGE_MASK because
the Linux guest page size and hypervisor page size concepts are
different, even though they happen to be the same value on x86.
Also, replace PAGE_SIZE with HV_HYP_PAGE_SIZE.
Signed-off-by: Maya Nakamura
---
On Wed, Jun 05, 2019 at 01:07:25PM -0400, Douglas Gilbert wrote:
> On 2019-06-05 2:00 a.m., Jiri Slaby wrote:
> >On 23. 05. 19, 4:38, Gen Zhang wrote:
> >>In sg_write(), the opcode of the command is fetched the first time from
> >>the userspace by __get_user(). Then the whole command, the opcode
>
The Linux guest page size and hypervisor page size concepts are
different, even though they happen to be the same value on x86. Hyper-V
code mixes up the two, so this patchset begins to address that by
creating and using a set of Hyper-V specific page definitions.
A major benefit of those new
To build this program successfully with clang, there have three
compiler options need to be specified:
- Header file path: tools/perf/include/bpf;
- Specify architecture;
- Define macro __NR_CPUS__.
This patch add comments to explain the reasons for building failure and
give two examples
This patch adds support for arm64 raw syscall numbers so that we can use
it on arm64 platform.
After applied this patch, we need to specify macro -D__aarch64__ or
-D__x86_64__ in compilation option so Clang can use the corresponding
syscall numbers for arm64 or x86_64 respectively, other
On my Juno board with ARM64 CPUs, perf trace command reports the eBPF
program building failure but the command will not exit and continue to
run. If we define an eBPF event in config file, the event will be
parsed with below flow:
perf_config()
`> trace__config()
`>
When I tried to run the trace on arm64 platform with eBPF program
augmented_raw_syscalls, it reports several failures for eBPF program
compilation. So tried to resolve these issues and this patch set is
the working result.
0001 patch lets perf command to exit directly if find eBPF program
The macro SYS_EXECVE has been defined twice, remove the duplicate one.
Signed-off-by: Leo Yan
---
tools/perf/examples/bpf/augmented_raw_syscalls.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/tools/perf/examples/bpf/augmented_raw_syscalls.c
>From cca931322233827dc21c7609f21f4042d78f220e Mon Sep 17 00:00:00 2001
From: Rolf Eike Beer
Date: Thu, 22 Nov 2018 16:40:49 +0100
Subject: scripts: use pkg-config to locate libcrypto
Otherwise build fails if the headers are not in the default location. While at
it also ask pkg-config for the
Commit-ID: e35faeb64146f2015f2aec14b358ae508e4066db
Gitweb: https://git.kernel.org/tip/e35faeb64146f2015f2aec14b358ae508e4066db
Author: Kan Liang
AuthorDate: Mon, 3 Jun 2019 06:41:20 -0700
Committer: Borislav Petkov
CommitDate: Thu, 6 Jun 2019 09:42:36 +0200
x86/CPU: Add more Icelake
On 5/31/2019 8:14 AM, Borislav Petkov wrote:
On Fri, May 31, 2019 at 01:15:33AM +, Herrenschmidt, Benjamin wrote:
This isn't terribly helpful, there's nothing telling anybody which of
those files corresponds to an ARM SoC :-)
drivers/edac/altera_edac.c is one example.
Also, James and
On Thu, 2019-06-06 at 08:05 +0100, Marc Zyngier wrote:
>
> > I disagree Marc. This is a rather bad error which indicates that the
> > device-tree is probably incorrect (or the HW was wired in a way that
> > cannot work).
>
> But surely that's something you'll spot pretty quickly.
Not really. A
Am Donnerstag, 6. Juni 2019, 09:38:41 CEST schrieb Rolf Eike Beer:
> Greg KH wrote:
> > On Wed, Jun 05, 2019 at 05:19:40PM +0200, Rolf Eike Beer wrote:
> > > I decided to dig out a toy project which uses a DragonBoard 410c. This
> > > has
> > > been "running" with kernel 4.9, which I would keep
śr., 5 cze 2019 o 17:12 Keerthy napisał(a):
>
>
>
> On 05/06/19 7:56 PM, Bartosz Golaszewski wrote:
> > śr., 5 cze 2019 o 10:02 Keerthy napisał(a):
> >>
> >> Add new compatible for K3 AM654 SoCs.
> >>
> >> Signed-off-by: Keerthy
> >> ---
> >> drivers/gpio/gpio-davinci.c | 1 +
> >> 1 file
On Thu, May 30, 2019 at 08:00:12AM -0700, Paul E. McKenney wrote:
> The sync_exp_work_done() function uses smp_mb__before_atomic(), but
> there is no obvious atomic in the ensuing code. The ordering is
> absolutely required for grace periods to work correctly, so this
> commit upgrades the
Hi Vincent,
On Thursday 06 Jun 2019 at 09:05:16 (+0200), Vincent Guittot wrote:
> Hi Quentin,
>
> On Wed, 5 Jun 2019 at 19:21, Quentin Perret wrote:
> >
> > On Friday 17 May 2019 at 14:55:19 (-0700), Stephen Boyd wrote:
> > > Quoting Amit Kucheria (2019-05-16 04:54:45)
> > > > (cc'ing Andy's
On 6/5/19 11:53 PM, Shuah Khan wrote:
> Fix the following cppcheck error:
>
> Checking drivers/media/v4l2-core/v4l2-ioctl.c ...
> Checking drivers/media/v4l2-core/v4l2-ioctl.c: CONFIG_VIDEO_ADV_DEBUG...
> [drivers/media/v4l2-core/v4l2-ioctl.c:2470]: (error) Uninitialized variable:
> sd
This is
On 05.06.2019 21:42, syzbot wrote:
> Hello,
>
> syzbot found the following crash on:
>
> HEAD commit: b2924447 Add linux-next specific files for 20190605
> git tree: linux-next
> console output: https://syzkaller.appspot.com/x/log.txt?x=17e867eea0
> kernel config:
The vCPU lbr event relies on the host to save/restore all the lbr
related MSRs. So add the LBR_SELECT save/restore to the related
functions for the vCPU case.
Signed-off-by: Wei Wang
Cc: Peter Zijlstra
Cc: Andi Kleen
---
arch/x86/events/intel/lbr.c | 7 +++
arch/x86/events/perf_event.h |
In some cases, an event may be created without needing a counter
allocation. For example, an lbr event may be created by the host
only to help save/restore the lbr stack on the vCPU context switching.
This patch adds a new interface to allow users to create a perf event
without the need of
When the vCPU is scheduled in:
- if the lbr feature was used in the last vCPU time slice, set the lbr
stack to be interceptible, so that the host can capture whether the
lbr feature will be used in this time slice;
- if the lbr feature wasn't used in the last vCPU time slice, disable
the
From: Like Xu
This patch adds support to enable/disable the host side save/restore
for the guest lbr stack on vCPU switching. To enable that, the host
creates a perf event for the vCPU, and the event attributes are set
to the user callstack mode lbr so that all the conditions are meet in
the
Introduce KVM_CAP_X86_GUEST_LBR to allow per-VM enabling of the guest
lbr feature.
Signed-off-by: Wei Wang
Cc: Paolo Bonzini
Cc: Andi Kleen
Cc: Peter Zijlstra
---
arch/x86/include/asm/kvm_host.h | 2 ++
arch/x86/kvm/x86.c | 14 ++
include/uapi/linux/kvm.h|
The debugctl msr is not completely identical on AMD and Intel CPUs, for
example, FREEZE_LBRS_ON_PMI is supported by Intel CPUs only. Now, this
msr is handled separatedly in svm.c and intel_pmu.c. So remove the
common debugctl msr handling code in kvm_get/set_msr_common.
Signed-off-by: Wei Wang
The MSR variable type can be "unsigned int", which uses less memory than
the longer unsigned long. The lbr nr won't be a negative number, so make
it "unsigned int" as well.
Suggested-by: Peter Zijlstra
Signed-off-by: Wei Wang
Cc: Peter Zijlstra
Cc: Andi Kleen
---
arch/x86/events/perf_event.h
Arch v4 supports streamlined Freeze_LBR_on_PMI. According to the SDM,
the LBR_FRZ bit is set to global status when debugctl.freeze_lbr_on_pmi
has been set and a PMI is generated. The CTR_FRZ bit is set when
debugctl.freeze_perfmon_on_pmi is set and a PMI is generated.
Signed-off-by: Wei Wang
Cc:
Last Branch Recording (LBR) is a performance monitor unit (PMU) feature
on Intel CPUs that captures branch related info. This patch series enables
this feature to KVM guests.
Here is a conclusion of the fundamental methods that we use:
1) the LBR feature is enabled per guest via QEMU setting of
This patch changes kvm_pmu_get_msr to get the msr_data struct, because
The host_initiated field from the struct could be used by get_msr. This
also makes this API be consistent with kvm_pmu_set_msr.
Signed-off-by: Wei Wang
Cc: Paolo Bonzini
Cc: Andi Kleen
---
arch/x86/kvm/pmu.c | 4
The lbr stack is architecturally specific, for example, SKX has 32 lbr
stack entries while HSW has 16 entries, so a HSW guest running on a SKX
machine may not get accurate perf results. Currently, we forbid the
guest lbr enabling when the guest and host see different lbr stack
entries or the host
The LBR stack MSRs are architecturally specific. The perf subsystem has
already assigned the abstracted MSR values based on the CPU architecture.
This patch enables a caller outside the perf subsystem to get the LBR
stack info. This is useful for hyperviosrs to prepare the lbr feature
for the
On 6/5/19 11:20 PM, Christoph Hellwig wrote:
On Wed, Jun 05, 2019 at 11:01:17PM -0700, John Hubbard wrote:
I started reviewing this one patch, and it's kind of messy figuring out
if the code motion preserves everything because of
all the consolidation from other places, plus having to move
Bits [0, 5] of MSR_IA32_PERF_CAPABILITIES tell about the format of
the addresses stored in the LBR stack. Expose those bits to the guest
when the guest lbr feature is enabled.
Signed-off-by: Wei Wang
Cc: Paolo Bonzini
Cc: Andi Kleen
---
arch/x86/include/asm/perf_event.h | 2 ++
Hi Borut,
Please remove unused "flags" variable declaration.
Erwan.
On 6/4/19 3:55 PM, Erwan LE RAY wrote:
>
>> Hi Borut,
>>
>> Please add the following line in the commit message (before your
>> sign-off) in a V2 of your patch:
>>
>> Fixes: 1bcda09d291081 ("serial: stm32: add support for
On Thu, Jun 06, 2019 at 07:01:26AM +0200, Jiri Slaby wrote:
> On 05. 06. 19, 17:35, Gen Zhang wrote:
> > On Wed, Jun 05, 2019 at 08:41:11AM +0200, Jiri Slaby wrote:
> >> On 31. 05. 19, 3:27, Gen Zhang wrote:
> >>> In sg_write(), the opcode of the command is fetched the first time from
> >>> the
From: Eugen Hristev
Checkpatch complaining that locks do not have comments,
unaligned code and macro reuse of same argument in to_isc_clk.
Fixed them by renaming, realigning and adding struct comments
Signed-off-by: Eugen Hristev
---
Changes in v3:
- new patch, addresses the checkpatch issues
On Wed, Jun 5, 2019 at 5:19 PM George Hung wrote:
>
> Add device tree documentation for Nuvoton BMC ECC
>
> Signed-off-by: George Hung
Reviewed-by: Avi Fishman
> ---
> .../bindings/edac/npcm7xx-sdram-edac.txt| 17 +
> 1 file changed, 17 insertions(+)
> create mode
On Wed, Jun 5, 2019 at 5:18 PM George Hung wrote:
>
> Add support for the Nuvoton NPCM7xx SoC EDAC driver
>
> NPCM7xx ECC datasheet from nuvoton.israel-Poleg:
> "Cadence DDR Controller User’s Manual For DDR3 & DDR4 Memories"
>
> Tested: Forcing an ECC error event
>
> Write a value to the
Hi Jones,
> Subject
>
> Re: [PATCH v13 3/3] dt-bindings: mfd: Document Renesas R-Car Gen3 RPC-IF
> controller bindings
>
> Hello!
>
> On 06/03/2019 04:04 PM, Lee Jones wrote:
>
> >>> Document the bindings used by the Renesas R-Car Gen3 RPC-IF
controller.
> >>>
> >>> Signed-off-by: Mason
From: Guo Ren
Support 4 triger types:
- IRQ_TYPE_LEVEL_HIGH
- IRQ_TYPE_LEVEL_LOW
- IRQ_TYPE_EDGE_RISING
- IRQ_TYPE_EDGE_FALLING
All of above could be set in DeviceTree file and it still compatible
with the old DeviceTree format.
Signed-off-by: Guo Ren
Cc: Marc Zyngier
---
From: Guo Ren
Add trigger type setting for csky,mpintc. The driver also could
support #interrupt-cells <1> and it wouldn't invalidate existing
DTs. Here we only show the complete format.
Signed-off-by: Guo Ren
Reviewed-by: Rob Herring
Cc: Marc Zyngier
---
From: Guo Ren
csky_mpintc_handler()
->handle_domain_irq()
->irq_exit()
->invoke_softirq()
->__do_softirq()
->local_irq_enable()
If new interrupt coming, it'll get into interrupt trap before return to
csky_mpintc_handler(). So there is no need loop in
From: Guo Ren
Here are some patches for irq-csky-mpintc. Any feedback is welcome.
Changes for V5:
- Remove "auto irq deliver patch" in this patchset, because it has been
queued as a fix already.
- Move "remove INTCL_HPPIR define" into remove-unnecessary-loop.patch
to make patch's
Fix checkpatch.pl warning(s)/error(s)/check(s) in i2c-tegra.c
Remove redundant BUG_ON calls or replace with WARN_ON_ONCE
as needed. Replace BUG() with error handling code.
Define I2C_ERR_UNEXPECTED_STATUS for error handling.
Signed-off-by: Bitan Biswas
---
drivers/i2c/busses/i2c-tegra.c | 67
On Thu, Jun 06, 2019 at 07:13:18AM +, Zhuo, Qiuxu wrote:
> During internal co-work, based on Kan's original patch, I got the
> "#define" in the Ice Lake group sorted by model number(the header of
> the file requires the sorting) and added my SOB. Dropping my SOB or
> adding a text "[Qiuxu: Get
Hi Greg,
This is a pull request containing fixes to be merged to 5.2-rc4/5.
It contains 3 bug fixes. See the tag comment for more details.
Thanks,
Oded
The following changes since commit 8aa75b72e3e6f0f566cd963606ec5da11b195c0b:
Merge tag 'misc-habanalabs-fixes-2019-05-24' of
On 06/06/2019 05:35 AM, Eric Hankland wrote:
Right - I'm aware there are other ways of detecting this - it's still
a class of events that some people don't want to surface. I'll ask if
there are any better examples.
I asked and it sounds like we are treating all events as potentially
insecure
On Thu, Jun 6, 2019 at 9:28 AM Oleg Nesterov wrote:
>
> On 06/05, Oleg Nesterov wrote:
> >
> > +int set_user_sigmask(const sigset_t __user *umask, size_t sigsetsize)
> > {
> > - if (!usigmask)
> > - return 0;
> > + sigset_t *kmask;
>
> Typo, this obviously should be
>
>
Powerpc hw triggers watchpoint before executing the instruction.
To make trigger-after-execute behavior, kernel emulates the
instruction. If the instruction is 'load something into non-
volatile register', exception handler should restore emulated
register state while returning back, otherwise
On Thu 06 Jun 00:26 PDT 2019, Vivek Gautam wrote:
> Hi Bjorn,
>
> On Thu, Jun 6, 2019 at 10:10 AM Bjorn Andersson
> wrote:
> >
> > This adds an initial dts for the Dragonboard 845. Supported
> > functionality includes Debug UART, UFS, USB-C (peripheral), USB-A
> > (host), microSD-card and
On 06/05, Oleg Nesterov wrote:
>
> +int set_user_sigmask(const sigset_t __user *umask, size_t sigsetsize)
> {
> - if (!usigmask)
> - return 0;
> + sigset_t *kmask;
Typo, this obviously should be
sigset_t kmask;
I'll send v2.
Dear Kbuild Test Robot, thank you very
Hi Bjorn,
On Thu, Jun 6, 2019 at 10:10 AM Bjorn Andersson
wrote:
>
> This adds an initial dts for the Dragonboard 845. Supported
> functionality includes Debug UART, UFS, USB-C (peripheral), USB-A
> (host), microSD-card and Bluetooth.
>
> Initializing the SMMU is clearing the mapping used for
On 6/5/2019 6:12 PM, Marc Zyngier wrote:
On 05/06/2019 15:38, Shenhar, Talel wrote:
FIC only support two sensing modes, rising-edge and level.
Yes, I can tell. Yet, this code will let EDGE_BOTH pass through, even if
it cannot handle it.
Will handle on v4
Indeed we use interrupt specifier
On Thu, May 30, 2019 at 02:29:22PM +0100, ufo19890607 wrote:
> From: yuzhoujian
>
> One can just record callchains in the kernel or user space with
> this new options. We can use it together with "--all-kernel" options.
> This two options is used just like print_stack(sys) or print_ustack(usr)
>
On Wed 05 Jun 22:50 PDT 2019, Lee Jones wrote:
> On Tue, 23 Apr 2019, Jeffrey Hugo wrote:
>
> > This adds the initial DT for the Lenovo Miix 630 laptop. Supported
> > functionality includes USB (host), microSD-card, keyboard, and trackpad.
> >
> > Signed-off-by: Jeffrey Hugo
> > ---
> >
On 6/5/2019 6:49 PM, Eduardo Valentin wrote:
On Wed, Jun 05, 2019 at 01:52:00PM +0300, Talel Shenhar wrote:
+- compatible: should be "amazon,al-fic"
+- reg: physical base address and size of the registers
+- interrupt-controller: identifies the node as an interrupt controller
+-
On Thu, 06 Jun 2019 05:49:45 +0100,
Bharat Kumar Gogada wrote:
>
> > On 31/05/2019 17:09, Lorenzo Pieralisi wrote:
> > > [+Marc]
> > >
> > > On Wed, May 29, 2019 at 06:07:49PM +0530, Bharat Kumar Gogada wrote:
> > >> The current Multi MSI data programming fails if multiple end points
> > >>
On Wed 05 Jun 23:36 PDT 2019, Avri Altman wrote:
>
> > static int ufshcd_hba_init(struct ufs_hba *hba)
> > {
> > int err;
> > @@ -7425,9 +7460,15 @@ static int ufshcd_hba_init(struct ufs_hba *hba)
> > if (err)
> > goto out_disable_vreg;
> >
> > + err =
On 06/06/2019 07:41, Sameer Pujar wrote:
>
> On 6/6/2019 11:30 AM, Peter Ujfalusi wrote:
>> Hi Sameer,
>>
>> On 06/06/2019 6.49, Sameer Pujar wrote:
>>> Sorry for late reply.
>>> [Resending the reply since delivery failed for few recipients]
>>> I discussed this internally with HW folks and
> From: Borislav Petkov [mailto:b...@alien8.de]
> ...
> > From: Kan Liang
> >
> > Add the CPUID model number of Icelake (ICL) desktop and server
> > processors to the Intel family list.
> >
> > Signed-off-by: Kan Liang
> > Signed-off-by: Qiuxu Zhuo
>
> You're sending this patch but it has
On Wed, 05 Jun 2019 23:02:13 +0100,
Benjamin Herrenschmidt wrote:
>
> On Wed, 2019-06-05 at 13:22 +0100, Marc Zyngier wrote:
> >
> > > + * This is generally fixed depending on what pieces of HW it's wired up
> > > + * to.
> > > + *
> > > + * We configure it based on the sensitivity of the
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