On Mon 05-08-19 15:20:17, john.hubb...@gmail.com wrote:
> From: John Hubbard
>
> For pages that were retained via get_user_pages*(), release those pages
> via the new put_user_page*() routines, instead of via put_page() or
> release_pages().
Hmm, this is an interesting code path. There seems to
On Fri, Jun 28, 2019 at 03:34:23PM +0800, Jianjun Wang wrote:
> These series patches modify pcie-mediatek.c and dt-bindings compatible
> string to support MT7629 PCIe host.
>
> Jianjun Wang (2):
> dt-bindings: PCI: Add support for MT7629
> PCI: mediatek: Add controller support for MT7629
>
>
On Tue, Aug 06, 2019 at 03:34:34PM -0400, Qian Cai wrote:
> diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c
> index 876055e37352..a0c495a3f4fd 100644
> --- a/arch/arm64/kernel/cpuinfo.c
> +++ b/arch/arm64/kernel/cpuinfo.c
> @@ -34,10 +34,7 @@ DEFINE_PER_CPU(struct cpuinfo_arm
Hi,
On 06/08/2019 20:30:45+0200, Ondřej Jirman wrote:
> Maybe whether XO or DCXO is used also matters if you want to do some fine
> tunning of DCXO (control register has pletny of options), but that's probably
> better done in u-boot. And there's still no need to read HOSC source from DT.
> The dr
On Wed, Aug 7, 2019 at 12:45 PM Christoph Hellwig wrote:
>
> On Wed, Aug 07, 2019 at 11:48:33AM +0200, Rafael J. Wysocki wrote:
> > So I think I know what the problem is here.
> >
> > If ASPM is disabled for the NVMe device (which is the case on my machine by
> > default),
> > skipping the bus-le
On Tue, Aug 06, 2019 at 03:34:34PM -0400, Qian Cai wrote:
> The commit 155433cb365e ("arm64: cache: Remove support for ASID-tagged
> VIVT I-caches") introduced some compiation warnings from GCC (and
> Clang),
>
> arch/arm64/kernel/cpuinfo.c:38:26: warning: initialized field
> overwritten [-Woverri
According to the latest am572x[1] and dra74x[2] data manuals, mmc3
default, hs, sdr12 and sdr25 modes use iodelay values given in
MMC3_MANUAL1. Set the MODE_SELECT bit for these so that manual mode is
selected and correct iodelay values can be configured.
[1] http://www.ti.com/lit/ds/symlink/am572
On Wed, Aug 07, 2019 at 08:26:23AM +, Philippe Schenker wrote:
> Add the phy-node and mdio bus to the fec-node, represented as is on
> hardware.
> This commit includes micrel,led-mode that is set to the default
> value, prepared for someone who wants to change this.
>
> Signed-off-by: Philippe
On Tue, Aug 06, 2019 at 06:41:44PM +0200, Oliver Hartkopp wrote:
> I compiled the code (the original version), but I do not get that "Should it
> be static?" warning:
>
> user@box:~/net-next$ make C=1
> CALLscripts/checksyscalls.sh
> CALLscripts/atomic/check-atomics.sh
> DESCEND obj
On Wed, Aug 07, 2019 at 11:48:33AM +0200, Rafael J. Wysocki wrote:
> So I think I know what the problem is here.
>
> If ASPM is disabled for the NVMe device (which is the case on my machine by
> default),
> skipping the bus-level PM in nvme_suspend() causes the PCIe link of it to
> stay up and
>
From: Erin Lo
Add a DT binding documentation of SCP for the
MT8183 SoC from Mediatek.
Signed-off-by: Erin Lo
Signed-off-by: Pi-Hsun Shih
Reviewed-by: Rob Herring
---
Changes from v14, v13, v12, v11, v10, v9, v8, v7, v6:
- No change.
Changes from v5:
- Remove dependency on CONFIG_RPMSG_MTK_
From: Erin Lo
Provide a basic driver to control Cortex M4 co-processor
Signed-off-by: Erin Lo
Signed-off-by: Nicolas Boichat
Signed-off-by: Pi-Hsun Shih
---
Changes from v14:
- No change.
Changes from v13:
- Move include/linux/platform_data/mtk_scp.h to
include/linux/remoteproc/mtk_scp.
From: Eddie Huang
Add scp node to mt8183 and mt8183-evb
Signed-off-by: Erin Lo
Signed-off-by: Pi-Hsun Shih
Signed-off-by: Eddie Huang
---
Changes from v14:
- No change.
Changes from v13:
- Change the size of the cfg register region.
Changes from v12, v11, v10:
- No change.
Changes from
From: Erin Lo
Add memory table mapping API for other driver to lookup
reserved physical and virtual memory
Signed-off-by: Erin Lo
Signed-off-by: Pi-Hsun Shih
---
Changes from v14:
- Fix a typo in variable name in DEBUG section.
Changes from v13:
- Add one more reserved region.
- Rename scp
Add a simple rpmsg support for mt8183 SCP, that use IPI / IPC directly.
Signed-off-by: Pi-Hsun Shih
---
Changes from v14:
- Change year on Copyright header to 2019.
Changes from v13:
- No change.
Changes from v12:
- Use strscpy instead of strncpy.
Changes from v11:
- Fix a bug that when rp
Add support for controlling and communicating with mt8183's system
control processor (SCP), using the remoteproc & rpmsg framework.
And also add a cros_ec driver for CrOS EC host command over rpmsg.
The overall structure of the series is:
* remoteproc/mtk_scp.c: Control the start / stop of SCP (Pa
> + if (pm_suspend_via_firmware() || !ctrl->npss ||
> !pcie_aspm_enabled(pdev)) {
> + mutex_lock(&aspm_lock);
> + aspm_enabled = bridge->link_state ? bridge->link_state->aspm_enabled :
> 0;
Please fix the overly long lines..
Hi Paul,
I will not be able to make these changes to support modularity any more.
Although the support.opensou...@diasemi.com e-mail address for Support
is still working, I will not be able to review your patches if you were to
re-send
them again.
Regards,
Stephen
On 07 December 2018 20:30, Pa
Signed-off-by: Gerd Hoffmann
---
include/drm/drm_gem_vram_helper.h | 7 +--
drivers/gpu/drm/drm_gem_vram_helper.c | 48 ---
.../gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c | 2 +-
drivers/gpu/drm/Kconfig | 1 +
4 files changed, 4 insertio
Now with ttm_buffer_object being a subclass of drm_gem_object we can
easily lookup ttm_buffer_object for a given drm_gem_object, which in
turm allows to create common helper functions. This patch starts off
with dump mmap helpers.
v2:
- drop drm_gem_ttm_mmap_offset().
- improve kerneldocs.
Sig
On 8/6/19 8:51 PM, Helen Koike wrote:
> Hi Hans,
>
> On 7/30/19 3:42 PM, Helen Koike wrote:
>> From: Jacob Chen
>>
>> Add the subdev driver for rockchip isp1.
>>
>> Signed-off-by: Jacob Chen
>> Signed-off-by: Shunqian Zheng
>> Signed-off-by: Yichong Zhong
>> Signed-off-by: Jacob Chen
>> Signe
bcache_allocator can call the following:
bch_allocator_thread()
-> bch_prio_write()
-> bch_bucket_alloc()
-> wait on &ca->set->bucket_wait
But the wake up event on bucket_wait is supposed to come from
bch_allocator_thread() itself => deadlock:
[ 1158.490744] INFO: task bcache_all
On Wed, Aug 07, 2019 at 11:34:45AM +0100, Julien Grall wrote:
> The ptrace trace SVE flags are prefixed with SVE_PT_*. Update the
> comment accordingly.
>
> Signed-off-by: Julien Grall
> ---
> arch/arm64/kernel/ptrace.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/ar
On Wed, Aug 07, 2019 at 10:17:50AM +0200, Philipp Zabel wrote:
> On Tue, 2019-08-06 at 18:02 +0100, Sudeep Holla wrote:
> > SCMIv2.0 adds a new Reset Management Protocol to manage various reset
> > states a given device or domain can enter. Device(s) that can be
> > collectively reset through a com
The ptrace trace SVE flags are prefixed with SVE_PT_*. Update the
comment accordingly.
Signed-off-by: Julien Grall
---
arch/arm64/kernel/ptrace.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/kernel/ptrace.c b/arch/arm64/kernel/ptrace.c
index 17525da8d5c8..0de3ea
On Wed, Aug 07, 2019 at 10:04:26AM +0200, Philipp Zabel wrote:
> On Tue, 2019-08-06 at 18:02 +0100, Sudeep Holla wrote:
> > On some ARM based systems, a separate Cortex-M based System Control
> > Processor(SCP) provides the overall power, clock, reset and system
> > control. System Control and Mana
On Tue, Aug 06, 2019 at 02:29:16PM -0700, Nathan Huckleberry wrote:
> I'm not sure that we should disable a broken feature instead of
> attempting a fix.
>
> CONFIG_FUNCTION_GRAPH_TRACER is dependent on CONFIG_FRAME_POINTER and
> there have been reports by MediaTek that the frame pointer unwinder
On Tuesday, August 6, 2019 5:00:06 PM CEST Rafael J. Wysocki wrote:
> On Tue, Aug 6, 2019 at 4:02 PM wrote:
> >
> >
> >
> > > -Original Message-
> > > From: Rafael J. Wysocki
> > > Sent: Monday, August 5, 2019 4:29 PM
> > > To: Kai-Heng Feng
> > > Cc: Rafael J. Wysocki; Limonciello, Mario
On Wed, Aug 07, 2019 at 09:23:41AM +, Peng Fan wrote:
> > Subject: [PATCH v2 1/5] firmware: arm_scmi: Add discovery of SCMI v2.0
> > performance fastchannels
> >
> > SCMI v2.0 adds support for "FastChannel", a lightweight unidirectional
> > channel that is dedicated to a single SCMI message typ
On Tue, Aug 06, 2019 at 05:29:15PM -0700, Paul E. McKenney wrote:
> On Tue, Aug 06, 2019 at 05:20:41PM -0400, Joel Fernandes (Google) wrote:
> > This test runs kfree_rcu in a loop to measure performance of the new
> > kfree_rcu, with and without patch.
> >
> > To see improvement, run with boot par
On Wed, 07 Aug 2019 11:08:51 +0200,
Wenwen Wang wrote:
>
> In hiface_pcm_init(), 'rt' is firstly allocated through kzalloc(). Later
> on, hiface_pcm_init_urb() is invoked to initialize 'rt->out_urbs[i]'. In
> hiface_pcm_init_urb(), 'rt->out_urbs[i].buffer' is allocated through
> kzalloc(). Howeve
On 2019/8/7 5:25 下午, Andrea Righi wrote:
> On Tue, Aug 06, 2019 at 07:36:48PM +0200, Andrea Righi wrote:
>> On Tue, Aug 06, 2019 at 11:18:01AM +0200, Andrea Righi wrote:
>>> bcache_allocator() can call the following:
>>>
>>> bch_allocator_thread()
>>> -> bch_prio_write()
>>> -> bch_bucket_a
On Wed, Aug 07, 2019 at 10:26:50AM +0200, Philipp Zabel wrote:
> On Tue, 2019-08-06 at 18:02 +0100, Sudeep Holla wrote:
> > SCMIv2.0 adds a new Reset Management Protocol to manage various reset
> > states a given device or domain can enter. Extend the existing SCMI
> > bindings to add reset protoco
Hi Hugues,
Can you provide the output of the most recent v4l2-compliance?
Use 'v4l2-compliance -s'.
Also, just to confirm, with this v4 there are no /dev/mediaX or
/dev/v4l-subdevX devices created anymore, right?
This v4 looks good to me, I just want to have these final checks
done.
Regards,
On Wednesday, August 7, 2019 11:53:44 AM CEST Rafael J. Wysocki wrote:
> From: Rafael J. Wysocki
>
> One of the modifications made by commit d916b1be94b6 ("nvme-pci: use
> host managed power state for suspend") was adding a pci_save_state()
> call to nvme_suspend() in order to prevent the PCI bus
Sai,
On 07/08/2019 11:08, Sai Prakash Ranjan wrote:
Hi Suzuki,
On 7/31/2019 11:35 AM, Sai Prakash Ranjan wrote:
Hi Suzuki,
On 7/31/2019 11:28 AM, Sai Prakash Ranjan wrote:
Add coresight components found on Qualcomm SDM845 SoC.
Signed-off-by: Sai Prakash Ranjan
Reviewed-by: Mathieu Poirier
Hi Shiva,
shiva.linuxwo...@gmail.com wrote on Mon, 22 Jul 2019 07:56:21 +0200:
"with multiple dies" in the title
> From: Shivamurthy Shastri
>
> Some of the Micron flashes has multi-die, and need to select the die
have multiple dies and
> each time while accessing
Hi Suzuki,
On 7/31/2019 11:35 AM, Sai Prakash Ranjan wrote:
Hi Suzuki,
On 7/31/2019 11:28 AM, Sai Prakash Ranjan wrote:
Add coresight components found on Qualcomm SDM845 SoC.
Signed-off-by: Sai Prakash Ranjan
Reviewed-by: Mathieu Poirier
Acked-by: Suzuki K Poulose
---
arch/arm64/boot/dts
> Subject: [PATCH v2 4/5] firmware: arm_scmi: Add RESET protocol in SCMI
> v2.0
>
> SCMIv2.0 adds a new Reset Management Protocol to manage various reset
> states a given device or domain can enter. Device(s) that can be collectively
> reset through a common reset signal constitute a reset domain
Hi Shiva,
shiva.linuxwo...@gmail.com wrote on Mon, 22 Jul 2019 07:56:20 +0200:
> From: Shivamurthy Shastri
>
> M70A series flashes by default enable continuous read feature (BIT0 in
> configuration register). This feature will not expose the ECC to host
> and causing read failure.
This is not
On 8/6/19 5:16 PM, Pengfei Li wrote:
> Like commit 40cacbcb3240 ("mm, compaction: remove unnecessary zone
> parameter in some instances"), remove unnecessary zone parameter.
>
> No functional change.
>
> Signed-off-by: Pengfei Li
Acked-by: Vlastimil Babka
> ---
> mm/compaction.c | 13 ++-
Hi Shiva,
shiva.linuxwo...@gmail.com wrote on Mon, 22 Jul 2019 07:56:19 +0200:
> From: Shivamurthy Shastri
>
I am not sure the "turn implemenatation generic" title describes what
you do.
> Driver is redesigned using parameter page to support Micron SPI NAND
> flashes.
Redesigned is perhaps a
> Subject: [PATCH v2 2/5] firmware: arm_scmi: Make use SCMI v2.0
> fastchannel for performance protocol
>
> SCMI v2.0 adds support for "FastChannel" which do not use a message
> header as they are specialized for a single message.
>
> Only PERFORMANCE_LIMITS_{SET,GET} and
> PERFORMANCE_LEVEL_{SET
On 08/06, Peter Zijlstra wrote:
>
> On Tue, Aug 06, 2019 at 06:17:42PM +0200, Oleg Nesterov wrote:
>
> > but this will also wake all the pending readers up. Every reader will burn
> > CPU for no reason and likely delay the writer.
> >
> > In fact I'm afraid this can lead to live-lock, because every
From: Rafael J. Wysocki
One of the modifications made by commit d916b1be94b6 ("nvme-pci: use
host managed power state for suspend") was adding a pci_save_state()
call to nvme_suspend() in order to prevent the PCI bus-level PM from
being applied to the suspended NVMe devices, but if ASPM is not
en
On 02.08.19 18:04:54, James Morse wrote:
> After a shorter game of spot-the-difference:
> Reviewed-by: James Morse
>
> Previously here:
> https://lore.kernel.org/linux-edac/e566fe1d-ed06-53bc-6827-f6dfa32ee...@arm.com/
>
>
> Please pick up tags when posting a new version.
> If you don't do this
Hi Shiva,
shiva.linuxwo...@gmail.com wrote on Mon, 22 Jul 2019 07:56:18 +0200:
> From: Shivamurthy Shastri
>
"mtd: spinand: micron: Rename helpers and structures to be more generic"
> Generalize OOB layout structure and function names.
Change the prefix of Micron driver's functions and struc
On Thursday, August 1, 2019 12:19:56 AM CEST Keith Busch wrote:
> On Wed, Jul 31, 2019 at 11:25:51PM +0200, Rafael J. Wysocki wrote:
> >
> > A couple of remarks if you will.
> >
> > First, we don't know which case is the majority at this point. For
> > now, there is one example of each, but it m
Hi Shiva,
shiva.linuxwo...@gmail.com wrote on Mon, 22 Jul 2019 07:56:17 +0200:
"mtd: spinand: enable parameter page support"
> From: Shivamurthy Shastri
>
> Some of the SPI NAND devices has parameter page, which is similar to
- have a
> ONFI table.
regular raw NA
On Tue, Aug 06, 2019 at 04:56:31PM -0700, Paul E. McKenney wrote:
> On Tue, Aug 06, 2019 at 05:20:40PM -0400, Joel Fernandes (Google) wrote:
> > Recently a discussion about performance of system involving a high rate
> > of kfree_rcu() calls surfaced on the list [1] which led to another
> > discuss
On Monday, August 5, 2019 3:06:20 PM CEST Peter Zijlstra wrote:
> On Fri, Aug 02, 2019 at 11:46:28AM +0100, Qais Yousef wrote:
> > scale_irq_capacity() call in schedutil_cpu_util() does
> >
> > util *= (max - irq)
> > util /= max
> >
> > But the comment says
> >
> > util *= (1 - irq)
Post [1] and checkpatch tool indicate that usage of bool type
in structure is now no more allowed/advised.
This patch replaces bool by unsigned char (u8) and reorders
struct rproc fields to avoid padding.
[1] https://lkml.org/lkml/2017/11/21/384
Signed-off-by: Loic Pallardy
---
include/linux/re
This patch series introduces a new flag in remoteproc core to add
support of remote processor having their firmware loading by another
way than standard remoteproc core sequence.
Firmware could be ROMed, loaded by security or bootloader before kernel
boot or loaded by a special rproc platform driv
Remote processor could boot independently or be started before Linux
kernel by bootloader or any firmware.
This patch introduces a new property in rproc core, named preloaded,
to be able to allocate resources and sub-devices like vdev and to
synchronize with current state without loading firmware f
On Tue, 6 Aug 2019 09:18:26 -0500
Parav Pandit wrote:
> There is no single production driver who is interested in mdev device
> uuid. Currently UUID is mainly used to derive a device name.
> Additionally mdev device name is already available using core kernel
> API dev_name().
Well, the mdev co
On 8/2/19 10:58 AM, Peter Zijlstra wrote:
> On Thu, Aug 01, 2019 at 02:38:06PM +0200, Peter Zijlstra wrote:
>> If the consumer of the data are RT tasks as well (I hadn't expected that
>> from a TV capture device) then I'd propose to use FIFO-50 as default.
>>
>> The thing is, the moment you're doin
On Tue, Aug 06, 2019 at 07:36:48PM +0200, Andrea Righi wrote:
> On Tue, Aug 06, 2019 at 11:18:01AM +0200, Andrea Righi wrote:
> > bcache_allocator() can call the following:
> >
> > bch_allocator_thread()
> > -> bch_prio_write()
> > -> bch_bucket_alloc()
> > -> wait on &ca->set->buc
On Wed, Aug 07, 2019 at 10:09:29AM +0100, Will Deacon wrote:
> On Wed, Aug 07, 2019 at 12:58:51PM +0800, Jia He wrote:
> > diff --git a/arch/arm64/include/asm/pgtable.h
> > b/arch/arm64/include/asm/pgtable.h
> > index 5fdcfe237338..e09760ece844 100644
> > --- a/arch/arm64/include/asm/pgtable.h
> >
> Subject: [PATCH v2 1/5] firmware: arm_scmi: Add discovery of SCMI v2.0
> performance fastchannels
>
> SCMI v2.0 adds support for "FastChannel", a lightweight unidirectional
> channel that is dedicated to a single SCMI message type for controlling a
> specific platform resource. They do not use a
On Tue, 2019-08-06 at 22:15 -0700, Nathan Chancellor wrote:
> Just for everyone else (since I commented on our issue tracker), this is
> now fixed in Linus's tree as of commit 1f6607250331 ("iwlwifi: dbg_ini:
> fix compile time assert build errors").
I think this change is incomplete and suggest
On Tue, Jul 30, 2019 at 10:29:42AM -0700, Reinette Chatre wrote:
> Currently cache pseudo-locked regions only consider one cache level but
> cache pseudo-locked regions may span multiple cache levels.
>
> In preparation for support of pseudo-locked regions spanning multiple
> cache levels pseudo-l
On Wed, Aug 07, 2019 at 04:28:32PM +0800, Xiongfeng Wang wrote:
> On 2019/8/6 15:24, Lukas Wunner wrote:
> > I'd suggest something like the below instead, could you give it a whirl
> > and see if it reliably fixes the issue for you?
>
> I tested the below patch. It can fix the issue.
Thank you!
In hiface_pcm_init(), 'rt' is firstly allocated through kzalloc(). Later
on, hiface_pcm_init_urb() is invoked to initialize 'rt->out_urbs[i]'. In
hiface_pcm_init_urb(), 'rt->out_urbs[i].buffer' is allocated through
kzalloc(). However, if hiface_pcm_init_urb() fails, both 'rt' and
'rt->out_urbs[i].
Hi Shiva,
shiva.linuxwo...@gmail.com wrote on Mon, 22 Jul 2019 07:56:16 +0200:
> From: Shivamurthy Shastri
"Create one generic ONFI table parsing instance"
>
> ONFI table parsing is common, as most of the variables are common
> between raw and SPI NAND. The parsing function is instantiated in
On Wed, Aug 07, 2019 at 12:58:51PM +0800, Jia He wrote:
> diff --git a/arch/arm64/include/asm/pgtable.h
> b/arch/arm64/include/asm/pgtable.h
> index 5fdcfe237338..e09760ece844 100644
> --- a/arch/arm64/include/asm/pgtable.h
> +++ b/arch/arm64/include/asm/pgtable.h
> @@ -209,7 +209,7 @@ static inli
On 26/07/19 5:07 AM, Michael K. Johnson wrote:
> The GL9750 and GL9755 chipsets, and possibly others, require PLL Enable
> setup as part of the internal clock setup as described in 3.2.1 Internal
> Clock Setup Sequence of SD Host Controller Simplified Specification
> Version 4.20. This changes the
On 06-08-19, 11:50, Fabien Parent wrote:
> Add the compatible for MT8516 in order to take advantage of the
> MediaTek CPUFreq driver for Mediatek's MT8516 SoC.
>
> Signed-off-by: Fabien Parent
> ---
> drivers/cpufreq/mediatek-cpufreq.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/dr
Hi shiva.linuxwo...@gmail.com,
shiva.linuxwo...@gmail.com wrote on Mon, 22 Jul 2019 07:56:15 +0200:
> From: Shivamurthy Shastri
"mtd: nand: move ONFI specific helpers to nand/onfi.c"?
>
> These functions are support functions for enabling ONFI standard and
> common between raw NAND and SPI NA
On 02.08.19 18:04:46, James Morse wrote:
> On 24/06/2019 16:08, Robert Richter wrote:
> > The detail_location[] string in struct ghes_edac_pvt is complete
> > useless and data is just copied around. Put everything into
> > e->other_detail from the beginning.
I am updating the description here to c
Hello everyone,
This is Dario, from SUSE. I'm also interesting in core-scheduling, and
using it in virtualization use cases.
Just for context, I'm working in virt since a few years, mostly on Xen,
but I've done Linux stuff before, and I am getting back at it.
For now, I've been looking at the co
From: Ben Segal
Packets that arrive from the user and need to be parsed by the driver are
assumed to be in LE format.
This patch fix all the places where the code handles these packets and use
the correct endianness macros to handle them, as the driver handles the
packets in CPU format (LE or BE
From: Ben Segal
This patch fix the CQ irq handler to work in hosts with BE architecture.
It adds the correct endian-swapping macros around the relevant memory
accesses.
Signed-off-by: Ben Segal
Reviewed-by: Oded Gabbay
Signed-off-by: Oded Gabbay
---
drivers/misc/habanalabs/irq.c | 27 +++
The 08/07/2019 15:56, Jacob Wen wrote:
> I think the description is not correct. Consider using something like below.
Thank you for comments.
>
> In Xen environment, due to memory fragmentation ixgbe may allocate a 'DMA'
> buffer with pages that are not physically contiguous.
Actually, I didn't
This patch add mt8183 mipi_tx driver.
And also support other chips that use the same binding and driver.
Signed-off-by: Jitao Shi
---
drivers/gpu/drm/mediatek/Makefile | 1 +
drivers/gpu/drm/mediatek/mtk_mipi_tx.c| 2 +
drivers/gpu/drm/mediatek/mtk_mipi_tx.h| 1
Currently all OSTM devices are called "ostm", also in kernel messages.
As there can be multiple instances in an SoC, this can confuse the user.
Hence construct a unique name from the DT node name, like is done for
platform devices.
On RSK+RZA1, the boot log changes like:
-clocksource: ostm:
Fix various issues in the error path of ostm_init():
1. Drop error message printing on of_iomap() failure, as the memory
allocation core already takes of that,
2. Handle irq_of_parse_and_map() failures correctly: it returns
unsigned int, hence make irq unsigned int, and zero is an err
Use the DIV_ROUND_CLOSEST() helper instead of open-coding the same
operation.
Signed-off-by: Geert Uytterhoeven
---
v3:
- New.
---
drivers/clocksource/renesas-ostm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clocksource/renesas-ostm.c
b/drivers/clocksource/re
Hi all,
This patch series contains various improvements for the Renesas OSTM
timer driver, as used on the RZ/A1 and RZ/A2 SoCs.
The last patch is v3 of a patch that was sent before to a limited
audience:
-
https://lore.kernel.org/linux-renesas-soc/1507727130-17641-1-git-send-email-jaco
Clean up useless 'pfn' variable.
Signed-off-by: Pingfan Liu
Cc: "Jérôme Glisse"
Cc: Andrew Morton
Cc: Mel Gorman
Cc: Jan Kara
Cc: "Kirill A. Shutemov"
Cc: Michal Hocko
Cc: Mike Kravetz
Cc: Andrea Arcangeli
Cc: Matthew Wilcox
To: linux...@kvack.org
Cc: linux-kernel@vger.kernel.org
---
mm
Hi all,
Changes since 20190806:
The arm64 tree introduced a patch that stopped the powerpc ppc64_defconfig
build from completing so I reverted that commit.
The mips tree gained a conflict against Linus' tree.
The crypto tree still had its build failure for which I applied a patch.
The drm-misc
From: kbuild test robot
drivers/target/iscsi/cxgbit/cxgbit_target.c:1451:47-48: Unneeded semicolon
Remove unneeded semicolon.
Generated by: scripts/coccinelle/misc/semicolon.cocci
Fixes: d7840976e391 ("net: Use skb accessors in network drivers")
CC: Matthew Wilcox (Oracle)
Signed-off-by: kb
Hi Shiva,
shiva.linuxwo...@gmail.com wrote on Mon, 22 Jul 2019 07:56:14 +0200:
> From: Shivamurthy Shastri
>
> These functions will be used by both raw NAND and SPI NAND, which
> supports ONFI like standards.
This is not exactly what you do. Why not:
mtd: nand: export ONFI related functions t
Hi, Lukas
On 2019/8/6 15:24, Lukas Wunner wrote:
> On Thu, Jul 04, 2019 at 03:50:38PM +0800, Xiongfeng Wang wrote:
>> When I use the following command to power on a slot which has been
>> powered off already.
>> echo 1 > /sys/bus/pci/slots/22/power
>> It prints the following error:
>> -bash: echo:
Prepare FlexCAN use on SODIMM 55/63 178/188. Those SODIMM pins are
compatible for CAN bus use with several modules from the Colibri
family.
Add Better drivestrength and also add flexcan2.
Signed-off-by: Philippe Schenker
---
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/imx7-colibr
Add sleep pinmux to the fec so it can properly sleep.
Signed-off-by: Philippe Schenker
---
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/imx7-colibri.dtsi | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi
b/
This patch prepares the devicetree for the new Ixora V1.2 where we are
able to turn off the supply of the can transceiver. This implies to use
a sleep state on transmission pins in order to prevent backfeeding.
Signed-off-by: Philippe Schenker
---
Changes in v3: None
Changes in v2:
- Changed co
This commit adds the touchscreens from Toradex so one can enable it.
Signed-off-by: Philippe Schenker
---
Changes in v3:
- Fix commit title to "...imx6-apalis:..."
Changes in v2:
- Deleted touchrevolution downstream stuff
- Use generic node name
- Put a better comment in there
arch/arm/boot/
Add touch controller that is connected over an I2C bus.
Signed-off-by: Philippe Schenker
---
Changes in v3:
- Fix commit message
Changes in v2:
- Deleted touchrevolution downstream stuff
- Use generic node name
- Better comment
arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi | 24 +++
This adds the muxing for the optional pins usb-oc (overcurrent) and
usb-id.
Signed-off-by: Philippe Schenker
---
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/imx6qdl-colibri.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/imx6qdl-colibri.
In order for the otg ports, that these modules support, it is needed
that dr_mode is on otg. Switch to use that feature.
Signed-off-by: Philippe Schenker
---
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/imx6qdl-colibri.dtsi | 2 +-
arch/arm/boot/dts/imx7-colibri.dtsi| 2 +-
2
From: Stefan Agner
Add pinmuxing and do not specify voltage restrictions for the usdhc
instance available on the modules edge connector. This allows to use
SD-cards with higher transfer modes if supported by the carrier board.
Signed-off-by: Stefan Agner
Signed-off-by: Philippe Schenker
---
This adds the possibility to wake the module with an external signal
as defined in the Colibri standard
Signed-off-by: Philippe Schenker
---
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git
On Tue, 2019-08-06 at 18:02 +0100, Sudeep Holla wrote:
> SCMIv2.0 adds a new Reset Management Protocol to manage various reset
> states a given device or domain can enter. Extend the existing SCMI
> bindings to add reset protocol support by re-using the reset bindings
> for bothe reset providers an
This patch adds the watchdog to the imx6ull-colibri devicetree
Signed-off-by: Philippe Schenker
---
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/imx6ull-colibri.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi
b/arch/ar
From: Max Krummenacher
Add the pinmuxing and a inactive node for flexcan1 on SODIMM 55/63
and move the inactive flexcan nodes to imx6ull-colibri-eval-v3.dtsi
where they belong.
Note that this commit does not enable flexcan functionality, but rather
eases the effort needed to do so.
Signed-off-b
This adds the common touchscreen that is used with Toradex's
Eval Boards.
Signed-off-by: Philippe Schenker
---
Changes in v3: None
Changes in v2:
- Removed f0710a, that is downstream only
- Changed to generic node name
- Better comment
.../arm/boot/dts/imx6ull-colibri-eval-v3.dtsi | 24 ++
From: Max Krummenacher
Reduce the current drawn from VCC_BATT when the main power on the 3V3
pins to the module are switched off.
This switches off SoC internal pull resistors which are provided on the
module for TAMPER7 and TAMPER9 SoC pin and switches on a pull down
instead of a pullup for the
This commit adds UHS capability to Toradex Eval Boards
Signed-off-by: Philippe Schenker
---
Changes in v3:
- New patch to make use of ARM: dts: imx7-colibri: fix 1.8V/UHS support
Changes in v2: None
arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi | 11 +--
1 file changed, 9 insertions(+)
From: Stefan Agner
Force HS200 by masking bit 63 of the SDHCI capability register.
The i.MX ESDHC driver uses SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400. With
that the stack checks bit 63 to descide whether HS400 is available.
Using sdhci-caps-mask allows to mask bit 63. The stack then selects
HS200 as op
Add the phy-node and mdio bus to the fec-node, represented as is on
hardware.
This commit includes micrel,led-mode that is set to the default
value, prepared for someone who wants to change this.
Signed-off-by: Philippe Schenker
---
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/imx
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