On 2020/06/30 3:35, Kanchan Joshi wrote:
> On Fri, Jun 26, 2020 at 02:50:20AM +, Damien Le Moal wrote:
>> On 2020/06/26 2:18, Kanchan Joshi wrote:
>>> Introduce RWF_ZONE_APPEND flag to represent zone-append. User-space
>>> sends this with write. Add IOCB_ZONE_APPEND which is set in
>>> kiocb->k
On Mon, 29 Jun 2020 16:49:15 -0500 Alex Elder wrote:
> The INIT_HOL_BLOCK_EN and INIT_HOL_BLOCK_TIMER endpoint registers
> are only valid for RX endpoints.
>
> Have ipa_endpoint_modem_hol_block_clear_all() skip writing these
> registers for TX endpoints.
>
> Signed-off-by: Alex Elder
> ---
> dr
From: Po Liu
Date: Mon, 29 Jun 2020 14:54:16 +0800
> Since 'tcfp_burst' with TICK factor, driver side always need to recover
> it to the original value, this patch moves the generic calculation and
> recover to the 'burst' original value before offloading to device driver.
>
> Signed-off-by: Po
On 6/30/20 2:37 AM, Luc Van Oostenryck wrote:
On Tue, Jun 30, 2020 at 02:08:36AM +0800, kernel test robot wrote:
Hi Luc,
I love your patch! Perhaps something to improve:
[auto build test WARNING on next-20200626]
[cannot apply to linux/master linus/master v5.8-rc2 v5.8-rc1 v5.7 v5.8-rc3]
[I
For test and debug purposes, it's often necessary to enable or disable
clocks from shell. Add a new debugfs file (clk_prepare_enable) that
calls clk_prepare_enable() when writing "1" and clk_disable_unprepare()
when writing "0".
This can have security implications, so only support it when the code
From: Rajan Vaja
Use ZynqMP specific mux clock flags instead of using CCF flags.
Signed-off-by: Rajan Vaja
Signed-off-by: Amit Sunil Dhamne
---
drivers/clk/zynqmp/clk-mux-zynqmp.c | 14 +-
drivers/clk/zynqmp/clk-zynqmp.h | 8
2 files changed, 21 insertions(+), 1 dele
On 6/30/20 2:12 AM, Tony Lindgren wrote:
* kernel test robot [200617 17:28]:
Hi Adam,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on omap/for-next]
[cannot apply to balbi-usb/testing/next]
[if your patch is applied to the wrong git tree, please drop us a note
From: Rajan Vaja
Currently firmware passes CCF specific flags to ZynqMP clock driver.
So firmware needs to be updated if CCF flags are changed. The firmware
should have its own 'flag number space' that is distinct from the
common clk framework's 'flag number space'. So define and use ZynqMP
speci
This series adds supports for firmware specific flags. These include
- Common Flags
- Divider Flags
- Mux Flags
The intent is to remove firmware's dependency on CCF flag values by
having firmware specific flags with independent values.
Rajan Vaja (3):
clk: zynqmp: Use firmware specific common c
From: Rajan Vaja
Use ZynqMP specific divider clock flags instead of using CCF flags.
Signed-off-by: Rajan Vaja
Signed-off-by: Amit Sunil Dhamne
---
drivers/clk/zynqmp/clk-zynqmp.h | 9 +
drivers/clk/zynqmp/divider.c| 16 +++-
2 files changed, 24 insertions(+), 1 delet
On Thu, 25 Jun 2020 15:35:02 -0400 (EDT)
Mathieu Desnoyers wrote:
> >> So the reservation is not "just" an add instruction, it's actually an
> >> xadd on x86. Is that really faster than a cmpxchg ?
> >
> > I believe the answer is still yes. But I can run some benchmarks to
> > make sure.
>
> [auto build test ERROR on staging/staging-testing]
> > [also build test ERROR on v5.8-rc3 next-20200629]
> > [If your patch is applied to the wrong git tree, kindly drop us a note.
> > And when submitting patch, we suggest to use as documented in
> > https:/
On Mon, Jun 29, 2020 at 05:10:51PM -0700, Krishna Reddy wrote:
> Add global/context fault hooks to allow NVIDIA SMMU implementation
> handle faults across multiple SMMUs.
>
> Signed-off-by: Krishna Reddy
Reviewed-by: Nicolin Chen
On Mon, 29 Jun 2020 at 23:42, Sean Christopherson
wrote:
>
> On Mon, Jun 29, 2020 at 03:59:25PM +0200, Paolo Bonzini wrote:
> > On 29/06/20 15:46, Vitaly Kuznetsov wrote:
> > >> + if (!lapic_in_kernel(vcpu))
> > >> + return 1;
> > >> +
> > > I'm not sure how much we care about !lapic_in_
On Mon, Jun 29, 2020 at 05:10:49PM -0700, Krishna Reddy wrote:
> NVIDIA's Tegra194 SoC uses two ARM MMU-500s together to interleave
> IOVA accesses across them.
> Add NVIDIA implementation for dual ARM MMU-500s and add new compatible
> string for Tegra194 SoC SMMU topology.
>
> Signed-off-by: Kris
On Mon, 29 Jun 2020 14:18:01 -0700 Francesco Ruggeri wrote:
> We observed a panic in igb_reset_task caused by this race condition
> when doing a reboot -f:
>
> kworker reboot -f
>
> igb_reset_task
> igb_reinit_locked
> igb_down
> napi_synchronize
>
Hi Palmer,
On Tue, Jun 30, 2020 at 7:22 AM Palmer Dabbelt wrote:
>
> On Sun, 28 Jun 2020 09:25:24 PDT (-0700), mhira...@kernel.org wrote:
> > On Sun, 28 Jun 2020 16:07:37 +
> > guo...@kernel.org wrote:
> >
> >> From: Guo Ren
> >>
> >> Unfortunately, the current code couldn't be compiled:
> >
Andrew - fixup patch because I got a bug report where we were trying to do an
order 7 allocation here:
-- >8 --
Subject: [PATCH] fixup! fs: generic_file_buffered_read() now uses
find_get_pages_contig
We shouldn't try to pin too many pages at once, reads can be almost
arbitrarily big.
Signed-off
Add global/context fault hooks to allow NVIDIA SMMU implementation
handle faults across multiple SMMUs.
Signed-off-by: Krishna Reddy
---
drivers/iommu/arm-smmu-nvidia.c | 98 +
drivers/iommu/arm-smmu.c| 17 +-
drivers/iommu/arm-smmu.h| 3 +
3
Add binding for NVIDIA's Tegra194 SoC SMMU topology that is based
on ARM MMU-500.
Signed-off-by: Krishna Reddy
---
Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 5 +
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
b/Documentation
Changes in v8:
Fixed incorrect CB_FSR read issue during context bank fault.
Rebased and validated patches on top of
git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git next
v7 - https://lkml.org/lkml/2020/6/28/347
v6 - https://lkml.org/lkml/2020/6/4/1018
v5 - https://lkml.org/lkml/2020/5
NVIDIA's Tegra194 SoC uses two ARM MMU-500s together to interleave
IOVA accesses across them.
Add NVIDIA implementation for dual ARM MMU-500s and add new compatible
string for Tegra194 SoC SMMU topology.
Signed-off-by: Krishna Reddy
---
MAINTAINERS | 2 +
drivers/iommu/Make
On Mon, 29 Jun 2020 16:20:37 -0500 Alex Elder wrote:
> The AP LAN RX endpoint should not have download checksum offload
> enabled.
>
> The receive handler does properly accomodate the trailer that's
> added by the hardware, but we ignore it.
>
> Signed-off-by: Alex Elder
For this net series - w
A650 has a separate RSCC region, so dump RSCC registers separately, reading
them from the RSCC base. Without this change a GPU hang will cause a system
reset if CONFIG_DEV_COREDUMP is enabled.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 5 +
drivers/gpu/d
On Mon, 29 Jun 2020 16:37:36 -0500 Alex Elder wrote:
> We check the state of an event ring or channel both before and after
> any GSI command issued that will change that state. In most--but
> not all--cases, if the state is something different than expected we
> report an error message.
>
> Add
From: Tao Ren
Enable adc controller and corresponding voltage sensoring channels for
Wedge40.
Signed-off-by: Tao Ren
---
arch/arm/boot/dts/aspeed-bmc-facebook-wedge40.dts | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-wedge40.dts
b/arch/arm/
From: Tao Ren
Disable i2c bus #9, #10 and #13 as these i2c controllers are not used on
Wedge40.
Signed-off-by: Tao Ren
---
arch/arm/boot/dts/aspeed-bmc-facebook-wedge40.dts | 12
1 file changed, 12 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-wedge40.dts
b/arc
From: Tao Ren
Enable pwm_tacho device for fan control and monitoring in Wedge40.
Signed-off-by: Tao Ren
---
.../boot/dts/aspeed-bmc-facebook-wedge40.dts | 29 +++
1 file changed, 29 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-wedge40.dts
b/arch/arm/boot/
From: Tao Ren
The patch series update several devices' settings in Facebook Wedge40
device tree.
Patch #1 disables a few i2c controllers as they are not being used at
present.
Patch #2 enables adc device for voltage monitoring.
Patch #3 enables pwm_tacho device for fan control and monitoring.
What’s the version of kernel?
From: Grygorii Strashko
Date: Fri, 26 Jun 2020 21:17:03 +0300
> This series contains set of improvements for TI AM654x/J721E CPSW2G driver and
> adds support for TI AM654x SR2.0 SoC.
>
> Patch 1: adds vlans restoration after "if down/up"
> Patches 2-5: improvments
> Patch 6: adds support for TI
> common clk subsystem on Nios2
> date: 3 months ago
> config: nios2-randconfig-r033-20200629 (attached as .config)
> compiler: nios2-linux-gcc (GCC) 9.3.0
> reproduce (this is a W=1 build):
> wget
> https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/
On Sat, Jun 27, 2020 at 08:30:42PM +0200, Peter Zijlstra wrote:
> On Sat, Jun 27, 2020 at 08:32:54AM +1000, Dave Chinner wrote:
> > Observation from the outside:
> >
> > "However I'm having trouble convincing myself that's actually
> > possible on x86_64 "
>
> Using the weaker rules of LKMM (
x.git
> master
> head: 9ebcfadb0610322ac537dd7aa5d9cbc2b2894c68
> commit: 9b8303fc6efa724bd6a90656434fbde2cc6ceb2c nvmem: core: fix
> nvmem_cell_write inline function
> date: 8 months ago
> config: nios2-randconfig-r033-20200629 (attached as .config)
> compiler: nios2-linux-gc
On Mon, Jun 29, 2020 at 10:49:31PM +, Krishna Reddy wrote:
> >> + if (!nvidia_smmu->bases[0])
> >> + nvidia_smmu->bases[0] = smmu->base;
> >> +
> >> + return nvidia_smmu->bases[inst] + (page << smmu->pgshift); }
>
> >Not critical -- just a nit: why not put the bases[0] in i
Add support for the Image Processing Unit (IPU) found in all Ingenic
SoCs.
The IPU can upscale and downscale a source frame of arbitrary size
ranging from 4x4 to 4096x4096 on newer SoCs, with bicubic filtering
on newer SoCs, bilinear filtering on older SoCs. Nearest-neighbour can
also be obtained
Support multiple panels or bridges connected to the same DPI output of
the SoC. This setup can be found for instance on the GCW Zero, where the
same DPI output interfaces the internal 320x240 TFT panel, and the ITE
IT6610 HDMI chip.
Signed-off-by: Paul Cercueil
---
Notes:
v2: No change
dri
All Ingenic SoCs starting from the JZ4725B support OSD mode.
In this mode, two separate planes can be used. They can have different
positions and sizes, and one can be overlayed on top of the other.
Signed-off-by: Paul Cercueil
---
Notes:
v2: Use fallthrough; instead of /* fall-through */
The address of the DMA descriptor never changes. It can therefore be set
in the probe function.
Signed-off-by: Paul Cercueil
---
Notes:
v2: No change
drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/ingenic/i
Hi all,
After merging the clk tree, today's linux-next build (x86_64 allmodconfig)
produced this warning:
WARNING: modpost: missing MODULE_LICENSE() in drivers/clk/bcm/clk-bcm2711-dvp.o
Introduced by commit
1bc95972715a ("clk: bcm: Add BCM2711 DVP driver")
--
Cheers,
Stephen Rothwell
pgp5
Move the register definitions to ingenic-drm.h, to keep
ingenic-drm-drv.c tidy.
Signed-off-by: Paul Cercueil
---
Notes:
v2: Fix SPDX license tag
drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 116 +---
drivers/gpu/drm/ingenic/ingenic-drm.h | 126 ++
2 f
r
> for IDT 82P33 SMU.
> date: 4 months ago
> config: openrisc-randconfig-c003-20200629 (attached as .config)
> compiler: or1k-linux-gcc (GCC) 9.3.0
>
> If you fix the issue, kindly add following tag as appropriate
> Reported-by: kernel test robot
>
> All errors (new one
plane->index is NOT the index of the color plane in a YUV frame.
Actually, a YUV frame is represented by a single drm_plane, even though
it contains three Y, U, V planes.
Cc: sta...@vger.kernel.org # v5.3
Fixes: 90b86fcc47b4 ("DRM: Add KMS driver for the Ingenic JZ47xx SoCs")
Signed-off-by: Paul C
On Fri, Jun 26, 2020 at 04:23:12PM -0400, Mimi Zohar wrote:
> On Tue, 2020-06-23 at 17:26 -0300, Bruno Meneguele wrote:
>
>
> > diff --git a/security/integrity/ima/ima_main.c
> > b/security/integrity/ima/ima_main.c
> > index c1583d98c5e5..a760094e8f8d 100644
> > --- a/security/integrity/ima/ima_
Add documentation of the Device Tree bindings for the Image Processing
Unit (IPU) found in most Ingenic SoCs.
Signed-off-by: Paul Cercueil
---
Notes:
v2: Add missing 'const' in items list
.../bindings/display/ingenic,ipu.yaml | 65 +++
1 file changed, 65 insertions(
Full rename without any modification, except to the Makefile.
Renaming ingenic-drm.c to ingenic-drm-drv.c allow to decouple the module
name from the source file name in the Makefile. This will be useful
later when more source files are added.
Signed-off-by: Paul Cercueil
---
Notes:
v2: New
Convert the ingenic,lcd.txt to a new ingenic,lcd.yaml file.
In the process, the new ingenic,jz4780-lcd compatible string has been
added.
Reviewed-by: Rob Herring
Acked-by: Sam Ravnborg
Signed-off-by: Paul Cercueil
---
Notes:
v2: Add info about IPU at port@8
.../bindings/display/ingenic,
If you pass a string that is not terminated with a carriage return to
dev_err(), it will eventually be printed with a carriage return, but
not right away, since the kernel will wait for a pr_cont().
Signed-off-by: Paul Cercueil
---
Notes:
v2: New patch
drivers/gpu/drm/ingenic/ingenic-drm-d
Initialize hardware clock-gating registers on A640 and A650 GPUs.
At least for A650, this solves some performance issues.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx.xml.h | 8 ++
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 11 ++-
drivers/gpu/drm/msm/adreno/adren
This will allow supporting different hwcg tables for a6xx.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 129 ++---
drivers/gpu/drm/msm/adreno/adreno_device.c | 111 ++
drivers/gpu/drm/msm/adreno/adreno_gpu.h| 7 ++
3 files c
Initialize hardware clock-gating registers on A640 and A650 GPUs.
I put the hwcg tables in adreno_device.c, but maybe it makes more
sense to keep them in a6xx_gpu.c? (this would allow switching a5xx
to use the gpulist too.. it isn't possible to include both a6xx.xml.h
and a5xx.xml.h in adreno_devi
From: Dave Hansen
Global reclaim aims to reduce the amount of memory used on
a given node or set of nodes. Migrating pages to another
node serves this purpose.
memcg reclaim is different. Its goal is to reduce the
total memory consumption of the entire memcg, across all
nodes. Migration doe
On Mon, 29 Jun 2020, Peng Fan wrote:
> > > If that is the case, how is it possible that virtio breaks on ARM
> > > using the default dma_ops? The breakage is not Xen related (except
> > > that Xen turns dma_ops on). The original message from Peng was:
> > >
> > > vring_map_one_sg -> vring_use_dma
From: Dave Hansen
When memory fills up on a node, memory contents can be
automatically migrated to another node. The biggest problems are
knowing when to migrate and to where the migration should be
targeted.
The most straightforward way to generate the "to where" list
would be to follow the
From: Dave Hansen
Some method is obviously needed to enable reclaim-based migration.
Just like traditional autonuma, there will be some workloads that
will benefit like workloads with more "static" configurations where
hot pages stay hot and cold pages stay cold. If pages come and go
from the
From: Keith Busch
Age and reclaim anonymous pages if a migration path is available. The
node has other recourses for inactive anonymous pages beyond swap,
#Signed-off-by: Keith Busch
Cc: Keith Busch
[vishal: fixup the migration->demotion rename]
Signed-off-by: Vishal Verma
Signed-off-by: Da
From: Keith Busch
Migrating pages had been allocating the new page before it was actually
needed. Subsequent operations may still fail, which would have to handle
cleaning up the newly allocated page when it was never used.
Defer allocating the page until we are actually ready to make use of
i
From: Dave Hansen
Prepare for the kernel to auto-migrate pages to other memory nodes
with a user defined node migration table. This allows creating single
migration target for each NUMA node to enable the kernel to do NUMA
page migrations instead of simply reclaiming colder pages. A node
with n
claim
- Added stats patch from Yang Shi
The full series is also available here:
https://github.com/hansendc/linux/tree/automigrate-20200629
--
We're starting to see systems with more and more kinds of memory such
as Intel's implementation of persistent memory.
Let's say yo
From: Dave Hansen
If a memory node has a preferred migration path to demote cold pages,
attempt to move those inactive pages to that migration node before
reclaiming. This will better utilize available memory, provide a faster
tier than swapping or discarding, and allow such pages to be reused
From: Yang Shi
Account the number of demoted pages into reclaim_state->nr_demoted.
Add pgdemote_kswapd and pgdemote_direct VM counters showed in
/proc/vmstat.
[ daveh:
- __count_vm_events() a bit, and made them look at the THP
size directly rather than getting data from migrate_pages(
On Fri, Jun 26, 2020 at 04:40:23PM -0400, Mimi Zohar wrote:
> On Tue, 2020-06-23 at 17:26 -0300, Bruno Meneguele wrote:
>
>
> > diff --git a/security/integrity/ima/Kconfig b/security/integrity/ima/Kconfig
> > index edde88dbe576..62dc11a5af01 100644
> > --- a/security/integrity/ima/Kconfig
> > +++
On 2020/6/28 21:48, Liu Song via Linux-f2fs-devel wrote:
> From: Liu Song
>
> In current version, @state will only be FREE_NID. This parameter
> has no real effect so remove it to keep clean.
>
> Signed-off-by: Liu Song
Reviewed-by: Chao Yu
Thanks,
On Fri, 26 Jun 2020, Michael S. Tsirkin wrote:
> On Thu, Jun 25, 2020 at 10:31:27AM -0700, Stefano Stabellini wrote:
> > On Wed, 24 Jun 2020, Michael S. Tsirkin wrote:
> > > On Wed, Jun 24, 2020 at 02:53:54PM -0700, Stefano Stabellini wrote:
> > > > On Wed, 24 Jun 2020, Michael S. Tsirkin wrote:
>
On Mon, Jun 29, 2020 at 6:20 PM Wei Liu wrote:
>
> On Mon, Jun 29, 2020 at 05:51:05PM -0400, Andres Beltran wrote:
> > On Mon, Jun 29, 2020 at 4:46 PM Wei Liu wrote:
> > >
> > > On Mon, Jun 29, 2020 at 04:02:25PM -0400, Andres Beltran wrote:
> > > > Currently, VMbus drivers use pointers into gues
Hi,
On Mon, Jun 29, 2020 at 4:53 AM Mark Brown wrote:
>
> On Fri, Jun 26, 2020 at 03:19:50PM -0700, Douglas Anderson wrote:
> > Setting the chip select on the Qualcomm geni SPI controller isn't
> > exactly cheap. Let's cache the current setting and avoid setting the
> > chip select if it's alrea
On some SPI controllers (like spi-geni-qcom) setting the chip select
is a heavy operation. For instance on spi-geni-qcom, with the current
code, is was measured as taking upwards of 20 us. Even on SPI
controllers that aren't as heavy, setting the chip select is at least
something like a MMIO oper
On 26/06/2020 16.29, Gustavo A. R. Silva wrote:
> Hi Peter,
>
> Please, see my comments below...
>
> On Fri, Jun 26, 2020 at 10:30:37AM +0300, Peter Ujfalusi wrote:
>>
>>
>> On 24/06/2020 20.12, Gustavo A. R. Silva wrote:
>>> Hi Vinod,
>>>
>>> On 6/24/20 00:55, Vinod Koul wrote:
On 19-06-
Good Day,
Hope you are doing great Today.I have a proposed business deal that will
benefit both parties. This is legitimate,legal and your REPUTATION will not be
compromised.I am confident that both of us can work out this transaction
perfectly well to the benefit of both parties. Reach to me fo
On Sun, Jun 28, 2020 at 08:08:03PM -0700, Randy Dunlap wrote:
> From: Randy Dunlap
>
> Fix spelling of the 'langid' function argument in the kernel-doc
> notation to quieten a kernel-doc warning.
>
> ../drivers/usb/gadget/usbstring.c:77: warning: Function parameter or member
> 'langid' not desc
On 6/29/20 4:30 PM, Baoquan He wrote:
>> The only way I can plausibly think of "cleaning up" the RECLAIM_ZONE bit
>> would be to raise our confidence that it is truly unused. That takes
>> time, and probably a warning if we see it being set. If we don't run
>> into anybody setting it or depending
On Sun, Jun 28, 2020 at 10:23 AM Rafael J. Wysocki wrote:
>
> On Fri, Jun 26, 2020 at 8:43 PM Dan Williams wrote:
> >
> > On Fri, Jun 26, 2020 at 7:22 AM Rafael J. Wysocki wrote:
> > >
> > > On Fri, Jun 26, 2020 at 2:06 AM Dan Williams
> > > wrote:
> > > >
> > > > Quoting the documentation:
>
On 2020-06-29, Ard Biesheuvel wrote:
On Mon, 29 Jun 2020 at 19:37, Fangrui Song wrote:
On 2020-06-29, Arvind Sankar wrote:
>On Mon, Jun 29, 2020 at 09:20:31AM -0700, Kees Cook wrote:
>> On Mon, Jun 29, 2020 at 06:11:59PM +0200, Ard Biesheuvel wrote:
>> > On Mon, 29 Jun 2020 at 18:09, Kees Cook
months ago
config: arm-randconfig-c022-20200629 (attached as .config)
compiler: arm-linux-gnueabi-gcc (GCC) 9.3.0
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot
All errors (new ones prefixed by >>):
>> arm-linux-gnueabi-ld: secti
On 06/29/20 at 07:27am, Dave Hansen wrote:
> On 6/28/20 11:52 PM, Baoquan He wrote:
> > On 06/25/20 at 05:34pm, Dave Hansen wrote:
> >>
> >> From: Dave Hansen
> >>
> >> I went to go add a new RECLAIM_* mode for the zone_reclaim_mode
> >> sysctl. Like a good kernel developer, I also went to go upd
On Wed, Jun 24, 2020 at 12:13 PM Ethan Edwards
wrote:
> `sizeof buf` changed to `sizeof(buf)`
>
> Signed-off-by: Ethan Edwards
> ---
> security/selinux/ss/conditional.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Merged into selinux/next but I rewrote the subject line to "selinu
>> +static irqreturn_t nvidia_smmu_context_fault_bank(int irq,
>> + void __iomem *cb_base = nvidia_smmu_page(smmu, inst,
>> + smmu->numpage + idx);
[...]
>> + fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR);
[...]
>> + writel_relaxed(fsr, cb_base + ARM_SMMU_CB_FSR);
>It reads FSR
On Sat, Jun 27, 2020 at 11:25 PM Richard Guy Briggs wrote:
>
> Fixed an inconsistent use of GFP flags in nft_obj_notify() that used
> GFP_KERNEL when a GFP flag was passed in to that function. Given this
> allocated memory was then used in audit_log_nfcfg() it led to an audit
> of all other GFP a
On Sun, 28 Jun 2020 09:25:24 PDT (-0700), mhira...@kernel.org wrote:
On Sun, 28 Jun 2020 16:07:37 +
guo...@kernel.org wrote:
From: Guo Ren
Unfortunately, the current code couldn't be compiled:
CC arch/riscv/kernel/patch.o
In file included from ./include/linux/kernel.h:11,
Hi Masahiro,
On Mon, Jun 29, 2020 at 01:56:19AM +0900, Masahiro Yamada wrote:
> On Thu, Jun 25, 2020 at 5:32 AM 'Sami Tolvanen' via Clang Built Linux
> wrote:
> >
> > This patch series adds support for building x86_64 and arm64 kernels
> > with Clang's Link Time Optimization (LTO).
> >
> > In add
Neil Armstrong writes:
> On 09/06/2020 10:13, Christian Hewitt wrote:
>> Correct the SoC revision and package bits/mask values for S905D3/X3 to detect
>> a wider range of observed SoC IDs, and tweak sort order for A311D/S922X.
>>
>> S905X3 05 0101 (SEI610 initial devices)
>> S905X3 10 0001
On Wed, 17 Jun 2020 14:53:46 +0200, Jerome Brunet wrote:
> The peripheral clock of the RNG is missing for gxl while it is present
> for gxbb.
Applied, thanks!
[1/1] arm64: dts: meson: add missing gxl rng clock
commit: 95ca6f06dd4827ff63be5154120c7a8511cd9a41
Best regards,
--
Kevin Hilman
On Thu, 18 Jun 2020 15:27:37 +0200, Neil Armstrong wrote:
> When starting at 744MHz, the Mali 450 core crashes on S805X based boards:
> lima d00c.gpu: IRQ ppmmu3 not found
> lima d00c.gpu: IRQ ppmmu4 not found
> lima d00c.gpu: IRQ ppmmu5 not found
> lima d00c.gpu: IRQ ppmmu6 not
On Fri, 26 Jun 2020 10:06:26 +0200, Krzysztof Kozlowski wrote:
> Fix dtschema validator warnings like:
> l2-cache-controller@c420: $nodename:0:
> 'l2-cache-controller@c420' does not match
> '^(cache-controller|cpu)(@[0-9a-f,]+)*$'
Applied, thanks!
[1/1] ARM: dts: meson: Ali
On Mon, Jun 29, 2020 at 02:37:53PM -0600, Shuah Khan wrote:
Hi Sasha,
On 6/29/20 9:13 AM, Sasha Levin wrote:
This is the start of the stable review cycle for the 5.7.7 release.
There are 265 patches in this series, all will be posted as a response
to this one. If anyone has any issues with th
Quoting Rajendra Nayak (2020-06-15 05:02:39)
> diff --git a/drivers/tty/serial/qcom_geni_serial.c
> b/drivers/tty/serial/qcom_geni_serial.c
> index 457c0bf..a90f8ec 100644
> --- a/drivers/tty/serial/qcom_geni_serial.c
> +++ b/drivers/tty/serial/qcom_geni_serial.c
> @@ -9,6 +9,7 @@
> #include
>
On Tue, 30 Jun 2020, Stephen Rothwell wrote:
> Hi all,
>
> Commit
>
> 724f239c3401 ("arm/xen: remove the unused macro GRANT_TABLE_PHYSADDR")
>
> is missing a Signed-off-by from its committer.
Fixed. Thank you so much, I love linux-next :-)
Hi Tero,
This series adds SERDES PHY support and Type-C USB Super-Speed support
to the J721E EVM.
Please queue this for -next. Thanks.
cheers,
-roger
Changelog:
v4:
- Removed redundant patch
- used compaible string for yaml filename
- typo fix s/mdf/mfd in patch subject
- added simple-mfd, addr
On Thu, Jun 18, 2020 at 01:26:57AM +0300, Dmitry Osipenko wrote:
> In some case, like a DRM display code for example, it's useful to silently
> check whether port node exists at all in a device-tree before proceeding
> with parsing of the graph.
>
> This patch adds of_graph_presents() that returns
Hi Greg,
On Wed, 17 Jun 2020 07:58:43 +0200 Greg KH wrote:
>
> On Wed, Jun 17, 2020 at 09:27:47AM +1000, Stephen Rothwell wrote:
> > This is in preparation for removing the include of major.h where it is
> > not needed.
> >
> > These files were found using
> >
> > grep -E -L '[<"](uapi/)?li
On Mon, Jun 29, 2020 at 04:29:28PM -0500, Bjorn Helgaas wrote:
> On Sun, Jun 28, 2020 at 06:12:33PM +0200, Luc Van Oostenryck wrote:
> > The method struct pci_error_handlers::error_detected() is defined and
> > documented as taking an 'enum pci_channel_state' for the second
> > argument but most dr
Hello,
syzbot found the following crash on:
HEAD commit:4e99b321 Merge tag 'nfs-for-5.8-2' of git://git.linux-nfs...
git tree: upstream
console output: https://syzkaller.appspot.com/x/log.txt?x=1013cb2910
kernel config: https://syzkaller.appspot.com/x/.config?x=20c907630cbdbe5
dash
This kernel module exports configuration attributes for the
system SPI chip.
This initial version exports the BIOS Write Enable (bioswe),
BIOS Lock Enable (ble), and the SMM Bios Write Protect (SMM_BWP)
fields of the Bios Control register. The idea is to keep adding more
flags, not only from the BC
On Fri, 26 Jun 2020 16:19:23 -0600
Alex Williamson wrote:
> On Tue, 23 Jun 2020 10:03:53 -0700
> Jacob Pan wrote:
>
> > IOMMU UAPI is newly introduced to support communications between
> > guest virtual IOMMU and host IOMMU. There has been lots of
> > discussions on how it should work with VFIO
On Mon, Jun 29, 2020 at 03:13:25PM -0700, Dan Williams wrote:
>On Mon, Jun 29, 2020 at 1:34 AM Wei Yang
> wrote:
>>
>> On Thu, Jun 25, 2020 at 12:46:43PM -0700, Dan Williams wrote:
>> >On Wed, Jun 24, 2020 at 10:53 PM David Hildenbrand wrote:
>> >>
>> >>
>> >>
>> >> > Am 25.06.2020 um 01:47 schrie
On Mon, 22 Jun 2020 14:18:36 -0500, Ricardo Rivera-Matos wrote:
> The BQ2515X family of devices are highly integrated battery management
> ICs that integrate the most common functions for wearable devices
> namely a charger, an output voltage rail, ADC for battery and system
> monitoring, and a pus
On Mon, Jun 22, 2020 at 02:18:35PM -0500, Ricardo Rivera-Matos wrote:
> From: Dan Murphy
>
> Convert the battery.txt file to yaml and fix up the examples.
>
> Signed-off-by: Dan Murphy
> ---
> .../bindings/power/supply/battery.txt | 83 +--
> .../bindings/power/supply/battery.
>> + if (!nvidia_smmu->bases[0])
>> + nvidia_smmu->bases[0] = smmu->base;
>> +
>> + return nvidia_smmu->bases[inst] + (page << smmu->pgshift); }
>Not critical -- just a nit: why not put the bases[0] in init()?
smmu->base is not available during nvidia_smmu_impl_init() call. It
On Monday, June 29, 2020 5:49pm, "Sean Christopherson"
said:
> On Mon, Jun 29, 2020 at 02:22:45PM -0700, Andy Lutomirski wrote:
>>
>>
>> > On Jun 29, 2020, at 1:54 PM, David P. Reed wrote:
>> >
>> > Simple question for those on the To: and CC: list here. Should I
>> > abandon any hope of thi
On 6/29/20 4:36 PM, Stephen Rothwell wrote:
> Hi all,
>
> On Mon, 29 Jun 2020 10:25:01 -0600 Jens Axboe wrote:
>>
>> On 6/29/20 10:21 AM, Pavel Begunkov wrote:
>>> On 29/06/2020 01:05, Stephen Rothwell wrote:
Hi all,
In commit
8c9cb6cd9a46 ("io_uring: fix refs underfl
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