On 30. 10. 20 1:40, Nick Desaulniers wrote:
> + authors/reviewers of commit fee10bd22678 ("memory: pl353: Add driver
> for arm pl353 static memory controller")
>
> On Thu, Oct 29, 2020 at 12:34 PM Krzysztof Kozlowski wrote:
>>
>> The pl353-smc driver uses module_amba_driver so it has a build
>
Fix typo in bcm_iproc_i2c_slave_isr().
Signed-off-by: Rayagonda Kokatanur
---
drivers/i2c/busses/i2c-bcm-iproc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/i2c/busses/i2c-bcm-iproc.c
b/drivers/i2c/busses/i2c-bcm-iproc.c
index cd687696bf0b..7a235f9f5884 100644
--
Handle single or multi byte master read request with or without
repeated start.
Fixes: c245d94ed106 ("i2c: iproc: Add multi byte read-write support for slave
mode")
Signed-off-by: Rayagonda Kokatanur
---
drivers/i2c/busses/i2c-bcm-iproc.c | 215 +++--
1 file changed, 170
Add code to handle IS_S_RX_FIFO_FULL_SHIFT interrupt to support
master write request with >= 64 bytes.
Iproc has a slave rx fifo size of 64 bytes.
Rx fifo full interrupt (IS_S_RX_FIFO_FULL_SHIFT) will be generated
when RX fifo becomes full. This can happen if master issues write
request of more th
On Sun, Oct 25, 2020 at 10:31:13AM -0400, Arvind Sankar wrote:
> Patch 1/2 -- Use memzero_explicit() instead of structure assignment/plain
> memset() to clear sensitive state.
>
> Patch 3 -- Currently the temporary variables used in the generic sha256
> implementation are cleared, but the clearing
Handle Master aborted error by flushing tx and rx fifo
and reinitializing the hw.
Signed-off-by: Rayagonda Kokatanur
---
drivers/i2c/busses/i2c-bcm-iproc.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/i2c/busses/i2c-bcm-iproc.c
b/drivers/i2c/busses/i2c-bcm
Handle only slave interrupts which are enabled.
The IS_OFFSET register contains the interrupt status bits which will be
set regardless of the enabling of the corresponding interrupt condition.
One must therefore look at both IS_OFFSET and IE_OFFSET to determine
whether an interrupt condition is se
This series of patches adds the following,
- Handle master abort error
- Fix support for single/multi byte master read request with/without
repeated start.
- Handle rx fifo full interrupt
- Fix typo
Changes from V1:
--Address review comments from Ray Jui,
Remove fixes tag
Rayagonda Kokatanur (6
Update slave isr mask (ISR_MASK_SLAVE) to include remaining
two slave interrupts.
Fixes: c245d94ed106 ("i2c: iproc: Add multi byte read-write support for slave
mode")
Signed-off-by: Rayagonda Kokatanur
---
drivers/i2c/busses/i2c-bcm-iproc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-
On Wed, Sep 30, 2020 at 09:01:31PM +0200, Krzysztof Kozlowski wrote:
> Hi,
>
> Changes since v1:
> 1. Drop applied vendor-prefix patches.
> 2. Add Reviews from Rob.
> 3. Use ABB prefix for Aristainetos boards.
> 4. Add missed compatibles for i.MX51, i.MX53 and i.MX6DL.
> 5. Fix typo (VF600 -> VF61
On Thu, Oct 15, 2020 at 05:24:41PM +0800, Tianjia Zhang wrote:
> This is an algorithm optimization. The reset operation when
> setting the public key is repeated and redundant, so remove it.
> At the same time, `sm2_ecc_os2ec()` is optimized to make the
> function more simpler and more in line with
On Fri, Oct 09, 2020 at 09:19:38AM +0100, Shiju Jose wrote:
> Fix following warnings caused by mismatch between
> function parameters and function comments.
>
> drivers/crypto/hisilicon/sgl.c:256: warning: Excess function parameter
> 'hw_sgl_dma' description in 'hisi_acc_sg_buf_unmap'
> drivers/c
On Sat, Oct 10, 2020 at 05:47:36PM +0100, Colin King wrote:
> From: Colin Ian King
>
> An incorrect sizeof() is being used, sizeof(priv->ring[i].rdr_req) is
> not correct, it should be sizeof(*priv->ring[i].rdr_req). Note that
> since the size of ** is the same size as * this is not causing any
>
On Thu, Oct 08, 2020 at 09:34:56AM +, Christophe Leroy wrote:
> current_desc_hdr() returns a u32 but in fact this is a __be32,
> leading to a lot of sparse warnings.
>
> Change the return type to __be32 and ensure it is handled as
> sure by the caller.
>
> Fixes: 3e721aeb3df3 ("crypto: talito
On Thu, Oct 08, 2020 at 09:34:55AM +, Christophe Leroy wrote:
> current_desc_hdr() compares the value of the current descriptor
> with the next_desc member of the talitos_desc struct.
>
> While the current descriptor is obtained from in_be32() which
> return CPU ordered bytes, next_desc member
This DMI product family string of this board is "Google_Hatch" so the
DMI quirk will take place. However, this board is using rt1015 speaker
amp instead of max98357a specified in the quirk. Therefore, we need an
new DMI quirk for this board.
Signed-off-by: Brent Lu
---
sound/soc/intel/boards/sof
This patch adds the driver data and updates quirk info for cml with
rt1015 speaker amp and rt5682 headset codec. Due to different mclk
frequency on JSL and CML, we need to use 4 slot TDM 100fs to avoid
the SSP m/n counter.
Signed-off-by: Brent Lu
---
sound/soc/intel/boards/sof_rt5682.c
First patch adds tdm 4-slot 100fs DAI setting to avoid jitter of using
64fs on CML boards. Second patch is a DMI quirk for HP Dooly.
Brent Lu (2):
ASoC: intel: sof_rt5682: Add support for cml_rt1015_rt5682
ASoC: intel: sof_rt5682: Add quirk for Dooly
sound/soc/intel/boards/sof_rt5682.c
On 10/30/2020 3:33 AM, Jingoo Han wrote:
External email: Use caution opening links or attachments
On 10/29/20, 1:40 AM, Vidya Sagar wrote:
DesignWare core has a TLP digest (TD) override bit in one of the control
registers of ATU. This bit also needs to be programmed for proper ECRC
functio
On 29.10.20 22:29, Sudarshan Rajagopalan wrote:
Hello all,
Hi!
We have a usecase where a module driver adds certain memory blocks using
add_memory_driver_managed(), so that it can perform memory hotplug
operations on these blocks. In general, these memory blocks aren’t
something that gets ph
On 10/30/2020 12:06 PM, Jiaxun Yang wrote:
在 2020/10/29 16:02, Tiezhu Yang 写道:
Loongson 3A4000+ CPU has per-core Mail_Send register to send mail,
there is no need to maintain register address of each core and node,
just simply specify cpu number.
Signed-off-by: Lu Zeng
Signed-off-by: Jianmin
Hi Mark, Morimoto-san,
Summary of changes:
* Support multiple instances of a component. For example there can be
multiple I2S devices which can use the same component driver.
* Support open platforms with empty Codec endpoint. Customers can plug
their own HW and can populate codec e
Mauro Carvalho Chehab writes:
> There are some ABI documents that, while they don't generate
> any warnings, they have issues when parsed by get_abi.pl script
> on its output result.
>
> Address them, in order to provide a clean output.
>
> Signed-off-by: Mauro Carvalho Chehab
> diff --git a/D
We need support to various accessories on the device,
some requiring switch does not exist in switch list.
So added switch for the following purpose.
SW_EXT_PEN_ATTACHED is for the checking the external pen
attached or not on the device. We also added driver
that uses such event.
Signed-off-by: H
Similar to speculation store bypass, show information about the indirect
branch speculation mode of a task in /proc/$pid/status.
Signed-off-by: Anand K Mistry
---
Documentation/filesystems/proc.rst | 2 ++
fs/proc/array.c| 28
2 files changed, 3
On Thu, 2020-10-29 at 23:27 +0800, Chun-Kuang Hu wrote:
> mtk_mipi_dsi_phy is currently placed inside mediatek drm driver, but it's
> more suitable to place a phy driver into phy driver folder, so move
> mtk_mipi_dsi_phy driver into phy driver folder.
>
> Signed-off-by: Chun-Kuang Hu
> ---
> dri
On 10/30/2020 12:00 PM, Jiaxun Yang wrote:
在 2020/10/29 16:02, Tiezhu Yang 写道:
The field LPA of CP0_CONFIG3 register is read only for Loongson64, so
the
write operations are meaningless, remove them.
Signed-off-by: Tiezhu Yang
---
arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
Currently --raw_output means nothing gets shown.
Why?
Because `raw_output()` has a `yield` and therefore is a generator, which
means it only executes when you ask it for a value.
Given no one actually is using it as a generator (checked via the added
type annotation), drop the yield so we actually
> From: Lu Baolu
> Sent: Friday, October 30, 2020 12:58 PM
>
> With the IOMMU driver registering iommu_ops for the mdev_bus, the
> IOMMU
> operations on an mdev could be done in the same way as any normal device
> (for example, PCI/PCIe). There's no need to distinguish an mdev from
> others for i
Shuah Khan writes:
> On 10/27/20 7:37 PM, Michael Ellerman wrote:
>> Tommi Rantala writes:
>>> Hi, small fixes to issues I hit with selftests.
>>>
>>> Tommi Rantala (13):
>>>selftests: filter kselftest headers from command in lib.mk
>>>selftests: pidfd: fix compilation errors due to wait.
Hi
On Mon, Oct 26, 2020 at 06:05:14PM +0800, Biwen Li wrote:
> From: Biwen Li
>
> The patch supports slave mode for imx I2C driver
>
> Signed-off-by: Biwen Li
> ---
> Change in v8:
> - fix build issue
>
> Change in v7:
> - support auto switch mode between master and slave
>
> From: Lu Baolu
> Sent: Friday, October 30, 2020 12:58 PM
>
> The iommu_ops will only take effect when INTEL_IOMMU_SCALABLE_IOV
> kernel
> option is selected. It applies to any device passthrough framework which
> implements an underlying bus for the subdevices.
>
> - Subdevice probe:
> When
Daeho,
If there is no change, we are used to not resend the patch with updated
version.
Thanks,
On 2020/10/30 12:10, Daeho Jeong wrote:
From: Daeho Jeong
Added a new F2FS_IOC_SET_COMPRESS_OPTION ioctl to change file
compression option of a file.
struct f2fs_comp_option {
u8 algorithm;
Allow the qcom_scm driver to be loadable as a permenent module.
This still uses the "depends on QCOM_SCM || !QCOM_SCM" bit to
ensure that drivers that call into the qcom_scm driver are
also built as modules. While not ideal in some cases its the
only safe way I can find to avoid build errors witho
Tweaks to allow pinctrl-msm code to be loadable as a module.
This is needed in order to support having the qcom-scm driver,
which pinctrl-msm calls into, configured as a module.
This requires that we tweak Kconfigs selecting PINCTRL_MSM to
also depend on QCOM_SCM || QCOM_SCM=n so that we match th
On 2020/10/30 12:10, Daeho Jeong wrote:
From: Daeho Jeong
Added a new F2FS_IOC_GET_COMPRESS_OPTION ioctl to get file compression
option of a file.
struct f2fs_comp_option {
u8 algorithm; => compression algorithm
=> 0:lzo, 1:lz4, 2:zstd, 3:lzorle
u8
remove the get_sb_mode() from x86/kernel/ima_arch.c and create a common
helper ima_get_efi_secureboot() in IMA so that all EFI-based architectures
can refer to the same procedure.
Signed-off-by: Chester Lin
---
arch/x86/kernel/ima_arch.c | 69 +++-
include/linux
On Wed, Oct 28, 2020 at 6:51 AM Will Deacon wrote:
> On Tue, Oct 27, 2020 at 10:53:47PM -0700, John Stultz wrote:
> > Alternatively, I'm considering trying to switch the module dependency
> > annotation so that the CONFIG_QCOM_SCM modularity depends on ARM_SMMU
> > being a module. But that is sort
Add arm64 IMA arch support. The code and arch policy is mainly inherited
from x86.
Signed-off-by: Chester Lin
---
arch/arm64/Kconfig | 1 +
arch/arm64/kernel/Makefile | 2 ++
arch/arm64/kernel/ima_arch.c | 43
3 files changed, 46 insertions(+)
Add IMA arch dependent support for ARM64. Some IMA functions can check
arch-specific status before running. For example, the ima_load_data
function or the boot param "ima_appraise=" should not be executed when
UEFI secure boot is enabled. We want to fill the gap in order to complete
the IMA support
Generalize the efi_get_secureboot() function so not only efistub but also
other subsystems can use it.
Signed-off-by: Chester Lin
---
drivers/firmware/efi/libstub/Makefile | 2 +-
drivers/firmware/efi/libstub/efi-stub.c | 2 +-
drivers/firmware/efi/libstub/efistub.h| 22 ---
driv
Hi Dafna,
On 10/26/20 2:50 PM, Dafna Hirschfeld wrote:
> Hi,
>
>
> Am 19.10.20 um 18:04 schrieb Helen Koike:
>> Allow streaming from self picture path and main picture path at the same
>> time.
>>
>> Take care for s_stream() callbacks to not be called twice.
>> When starting a stream, s_stream(t
We need support to various accessories on the device,
some requiring switch does not exist in switch list.
So added switch for the following purpose.
SW_COVER_ATTACHED is for the checking the cover
attached or not on the device. We also added driver
that uses such event.
Signed-off-by: Hyungjae I
Realtek single-port 2.5Gbps Ethernet PHYs are list as below:
RTL8226-CG: the 1st generation 2.5Gbps single port PHY
RTL8226B-CG/RTL8221B-CG: the 2nd generation 2.5Gbps single port PHY
RTL8221B-VB-CG: the 3rd generation 2.5Gbps single port PHY
RTL8221B-VM-CG: the 2.5Gbps single port PHY with MACsec
> From: Lu Baolu
> Sent: Friday, October 30, 2020 12:58 PM
>
> The aux-domain apis were designed for macro driver where the subdevices
> are created and used inside a device driver. Use the device's bus iommu
> ops instead of that in iommu domain for various callbacks.
IIRC there are only two us
All the items in the TODO list were addressed, uapi was reviewed,
documentation written, checkpatch errors fixed, several bugs fixed.
There is no big reason to keep this driver in staging, so move it out.
Signed-off-by: Helen Koike
---
.../media/v4l/pixfmt-meta-rkisp1.rst | 2 +-
dri
Hello,
I think it is time to move this driver out of staging.
Thanks all who contributed, specially to Dafna, who put a lot of
effort addressing all the items in the TODO list, fixing bugs,
cleaning the code, addressing past comments and testing.
Please, review the driver, see if there is any ot
From: Shunqian Zheng
Add the Rockchip ISP1 specific processing parameter format
V4L2_META_FMT_RK_ISP1_PARAMS and metadata format
V4L2_META_FMT_RK_ISP1_STAT_3A for 3A.
Signed-off-by: Shunqian Zheng
Signed-off-by: Jacob Chen
Signed-off-by: Helen Koike
Reviewed-by: Laurent Pinchart
---
Hello,
On Thu, Oct 29, 2020 at 7:34 PM David Gow wrote:
>
> On Wed, Oct 21, 2020 at 7:32 AM Daniel Latypov wrote:
> >
> > For simplcity, strip all trailing whitespace from parsed output.
> > I imagine no one is printing out meaningful trailing whitespace via
> > KUNIT_FAIL() or similar, and that if they
On 10/29/20 7:45 PM, Hemant Kumar wrote:
> diff --git a/drivers/bus/mhi/Kconfig b/drivers/bus/mhi/Kconfig
> index e841c10..476cc55 100644
> --- a/drivers/bus/mhi/Kconfig
> +++ b/drivers/bus/mhi/Kconfig
> @@ -20,3 +20,16 @@ config MHI_BUS_DEBUG
> Enable debugfs support for use with the MHI t
When perf data is in a pipe, it reads each event separately using
read(2) syscall. This is a huge performance bottleneck when
processing large data like in perf inject. Also perf inject needs to
use write(2) syscall for the output.
So convert it to use buffer I/O functions in stdio library for p
I typically build cifs.ko for testing using the latest Ubuntu mainline
build - but building a module in the 5.10-rc1 kernel - while booted to
the 5.10-rc1 ubuntu mainlinekerel - e.g. "make C=1 -C
/usr/src/linux-headers-`uname -r` M=`pwd` modules
CF=-D__CHECK_ENDIAN__"
which has worked for years - n
The Corsair digital power supplies of the series RMi, HXi and AXi include
a small micro-controller with a lot of sensors attached. The sensors can
be accessed by an USB connector from the outside.
This micro-controller provides the data by a simple proprietary USB HID
protocol. The data consist of
Hi Jiri,
On Thu, Oct 29, 2020 at 8:57 PM Jiri Olsa wrote:
>
> On Wed, Oct 28, 2020 at 05:56:32PM +0900, Namhyung Kim wrote:
> > When perf data is in a pipe, it reads each event separately using
> > read(2) syscall. This is a huge performance bottleneck when
> > processing large data like in perf
From: Ramuthevar Vadivel Murugan
Add compatible for Intel LGM SoC.
Signed-off-by: Ramuthevar Vadivel Murugan
---
Documentation/devicetree/bindings/spi/cadence-quadspi.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/spi/cadence-quadspi.yaml
b/Documen
From: Ramuthevar Vadivel Murugan
Convert the cadence-quadspi.txt documentation to cadence-quadspi.yaml
remove the cadence-quadspi.txt from Documentation/devicetree/bindings/spi/
Signed-off-by: Ramuthevar Vadivel Murugan
---
.../devicetree/bindings/spi/cadence-quadspi.txt| 67 -
.
Add QSPI controller support for Intel LGM SoC.
Note from Vignesh(mtd subsystem maintainer):
This series is a subset of "[PATCH v12 0/4] spi: cadence-quadspi: Add
support for the Cadence QSPI controller" by Ramuthevar,Vadivel MuruganX
that intended to move
cadence-quadspi driver to spi-mem framewo
From: Ramuthevar Vadivel Murugan
Add QSPI controller support for Intel LGM SoC.
Signed-off-by: Ramuthevar Vadivel Murugan
---
drivers/spi/Kconfig | 2 +-
drivers/spi/spi-cadence-quadspi.c | 3 +++
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/Kconfig
From: Ramuthevar Vadivel Murugan
Add multiple chipselect support for Intel LGM SoCs,
currently QSPI-NOR and QSPI-NAND supported.
Signed-off-by: Ramuthevar Vadivel Murugan
---
drivers/spi/spi-cadence-quadspi.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/spi/sp
From: Ramuthevar Vadivel Murugan
On Intel Lightning Mountain(LGM) SoCs QSPI controller do not use
Direct Access Controller(DAC).
This patch adds a quirk to disable the Direct Access Controller
for data transfer instead it uses indirect data transfer.
Signed-off-by: Ramuthevar Vadivel Murugan
From: Ramuthevar Vadivel Murugan
Move the Documentation/devicetree/bindings/mtd/cadence-quadspi.txt to
Documentation/devicetree/bindings/spi/
Signed-off-by: Ramuthevar Vadivel Murugan
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/{mtd => spi}/cadence-quadspi.txt | 0
1 file cha
Hi,
Is the community not interested in these two patches?
The second one also appears in the LBR patch set and
will benefit other PMU features later, such as PEBS.
Thanks,
Like Xu
On 2020/10/20 22:57, Like Xu wrote:
On Intel platforms, software may uses IA32_MISC_ENABLE[7]
bit to detect whethe
Hello,
On Thu, Oct 8, 2020 at 6:38 PM Mark Wielaard wrote:
>
> Hi,
>
> On Thu, 2020-10-08 at 09:02 +0200, Peter Zijlstra wrote:
> > Some time ago, I had my intern pursue the other 2 approaches for
> > > symbolization. The one I see as most promising is by using the DWARF
> > > information (no BPF
On Thu, Oct 29, 2020 at 7:56 PM David Gow wrote:
>
> On Thu, Oct 22, 2020 at 6:08 AM Daniel Latypov wrote:
> >
> > The code uses annotations, but they aren't accurate.
> > Note that type checking in python is a separate process, running
> > `kunit.py run` will not check and complain about invalid
On 2020-10-28 17:16, Robert Marko wrote:
If the watchdog hardware is enabled/running during boot, e.g.
due to a boot loader configuring it, we must tell the
watchdog framework about this fact so that it can ping the
watchdog until userspace opens the device and takes over
control.
Do so using th
Andreas Schwab writes:
> On Okt 01 2020, Christophe Leroy wrote:
>
>> At the time being, an early hash table is set up when
>> CONFIG_KASAN is selected.
>>
>> There is nothing wrong with setting such an early hash table
>> all the time, even if it is not used. This is a statically
>> allocated 256
On 10/30/2020 2:18 AM, m...@chromium.org wrote:
On Thu, Oct 29, 2020 at 01:37:19PM +0530, Akhil P Oommen wrote:
Register GPU as a devfreq cooling device so that it can be passively
cooled by the thermal framework.
Signed-off-by: Akhil P Oommen
Reviewed-by: Matthias Kaehlcke
Wait, I did not
With the IOMMU driver registering iommu_ops for the mdev_bus, the IOMMU
operations on an mdev could be done in the same way as any normal device
(for example, PCI/PCIe). There's no need to distinguish an mdev from
others for iommu operations. Remove the unnecessary code.
Signed-off-by: Lu Baolu
-
Hi Joerg and Alex,
A description of purpose for this series could be found here.
https://lore.kernel.org/linux-iommu/20200901033422.22249-1-baolu...@linux.intel.com/
The previous version was posted here.
https://lore.kernel.org/linux-iommu/20200922061042.31633-1-baolu...@linux.intel.com/
This
The aux-domain apis were designed for macro driver where the subdevices
are created and used inside a device driver. Use the device's bus iommu
ops instead of that in iommu domain for various callbacks.
Signed-off-by: Lu Baolu
---
drivers/iommu/iommu.c | 16 ++--
1 file changed, 10 i
Move mdev bus registration earlier than IOMMU probe processing so that
the IOMMU drivers could be able to set iommu_ops for the mdev bus. This
only applies when vfio-mdev module is setected to be built-in.
Signed-off-by: Lu Baolu
---
drivers/vfio/mdev/mdev_core.c | 4
1 file changed, 4 inse
So that they could be used in other files as well. No functional changes.
Signed-off-by: Lu Baolu
---
drivers/iommu/intel/iommu.c | 74 +++--
include/linux/intel-iommu.h | 49
2 files changed, 62 insertions(+), 61 deletions(-)
diff --git
The iommu_ops will only take effect when INTEL_IOMMU_SCALABLE_IOV kernel
option is selected. It applies to any device passthrough framework which
implements an underlying bus for the subdevices.
- Subdevice probe:
When a subdevice is created and added to the bus, iommu_probe_device()
will be c
On Wed, Oct 28, 2020 at 10:41:02AM -0500, Tyler Hicks wrote:
> Mimic the pre-existing ACPI and Device Tree event log behavior by not
> creating the binary_bios_measurements file when the EFI TPM event log is
> empty.
>
> This fixes the following NULL pointer dereference that can occur when
> readi
On Fri, 30 Oct 2020 at 04:28, Andrew Jeffery wrote:
>
> Hi Billy,
>
> On Tue, 27 Oct 2020, at 19:14, Billy Tsai wrote:
> > Some gpio pin at aspeed soc is input only and the prefix name of these
> > pin is "GPI" only. This patch fine-tune the condition of GPIO check from
> > "GPIO" to "GPI".
> >
>
[AMD Official Use Only - Internal Distribution Only]
Other used APIs should be also dropped together.
navi10_i2c_func()
navi10_i2c_xfer()
navi10_i2c_write_data()
navi10_i2c_read_data()
Regards,
Evan
-Original Message-
From: amd-gfx On Behalf Of Zou Wei
Sent: Thursday, October 29, 2020 8:
The USB Power Delivery specification Section 6.2.1.1.5 outlines
revision backward compatibility requirements starting from Revision 3.0.
The Port, the Cable Plug, and the Port Partner may support either revision
2 or revision 3 individually, and communication between ports, partners,
and cables of
Hi all,
In commit
65d437b83b2b ("drm/amdgpu/pm: fix the fan speed in fan1_input in manual mode
for navi1x")
Fixes tag
Fixes: 3033e9f1c2de ("drm/amdgpu/swsmu: handle manual fan readback on SMU11")
has these problem(s):
- Target SHA1 does not exist
Mayne you meant
Fixes: f6eb433954bf (
Hello, This is Hyungjae Im from Samsung Electronics.
Let me answer your questions inline.
>On Thu, Oct 29, 2020 at 10:27:47PM +0900, HyungJae Im wrote:
>> From: "hj2.im"
>> Date: Thu, 29 Oct 2020 22:11:24 +0900
>> Subject: [PATCH v2] input: add 2 kind of switch
>
>Why is this in the body of that
Hi Billy,
On Tue, 27 Oct 2020, at 19:14, Billy Tsai wrote:
> Some gpio pin at aspeed soc is input only and the prefix name of these
> pin is "GPI" only. This patch fine-tune the condition of GPIO check from
> "GPIO" to "GPI".
>
> Signed-off-by: Billy Tsai
I'd like it if we were a bit more speci
Hi Kuogee,
FYI, the error/warning still remains.
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
master
head: 07e0887302450a62f51dba72df6afb5fabb23d1c
commit: 8ede2ecc3e5ee327923f6e3cfe52761ce73607d1 drm/msm/dp: Add DP compliance
tests on Snapdragon Chipsets
date:
I found a bug in the recursion protection that prevented function
tracing from running in NMI context. Applying this fix to 5.9 worked
fine (tested by running perf record and function tracing at the same
time). But when I applied the patch to 5.10-rc1, it blew up with a
stack overflow:
perf: inter
Pages in active areas shouldn’t be swapped out only those in inactive areas. So
it’s a bit like seminary rock.
Sent from my iPhone
On 29-10-20, 09:40, Viresh Kumar wrote:
> Thanks a lot. I was a bit worried about the crazy idea I had to solve
> this :)
Hmm, I thought this is the other patch where I had that crazy idea.
This one was quite straight forward :)
--
viresh
I have an issue on my laptop which is old but with 2.5gb of ram an ssd hdd and
using zram compression I believe.
When ever it hits swap the system completely locks up and I have to reboot.
This only started occurring in .51
I only have access to my phone at the moment though I’ve looked at the cod
Applied. Thanks!
Alex
On Thu, Oct 29, 2020 at 9:17 AM Bhaskar Chowdhury wrote:
>
> Correct spelling in one of the comment.
>
> s/defalut/default/p
>
> Signed-off-by: Bhaskar Chowdhury
> ---
> CCing Greg becasue it touched drivers file. Trivial though.
>
> drivers/gpu/drm/amd/display/amdgpu_d
Hi all,
Changes since 20201029:
The drm-misc tree gained a build failure so I used the version from
next-20201029.
The pinctrl tree gained a build failure so I reverted a commit.
Non-merge commits (relative to Linus' tree): 1997
2411 files changed, 324993 insertions(+), 49232 dele
Move MHI to a firmware download error state for a failure to find
the firmware files or to load SBL or EBL image using BHI/BHIe. This
helps detect an error state sooner and shortens the wait for a
synchronous power up timeout.
Signed-off-by: Bhaumik Bhatt
---
drivers/bus/mhi/core/boot.c | 35 +++
MHI client drivers can request a device wake even if the device
may be in an error state or undergoing a shutdown. To prevent
unnecessary device wake processing, check for the device state
and bail out early so that the clients are made aware of the
device state sooner.
Signed-off-by: Bhaumik Bhat
mhi_fw_load_sbl() function is currently used to transfer SBL or EDL
images over BHI (Boot Host Interface). Same goes with mhi_fw_load_amss()
which uses BHIe. However, the contents of these functions do not
indicate support for a specific set of images. Since these can be used
for any image download
Bug fixes and improvements for MHI powerup and shutdown handling.
Firmware load function names are updated to accurately reflect their purpose.
Closed certain design gaps where the host (MHI bus) would allow clients to
operate after a power down or error detection.
Move to an error state sooner bas
mhi_power_down() does not ensure that the PM state is moved to an
inaccessible state soon enough as the system can encounter
scheduling delays till mhi_pm_disable_transition() gets called.
Additionally, if an MHI controller decides that the device is now
inaccessible and issues a power down, the re
If an mhi_power_down() is initiated after the device has entered
RDDM and a status callback was provided for it, it is possible
that another BHI interrupt fires while waiting for the MHI
RESET to be cleared. If that happens, MHI host would have moved
a "disabled" execution environment and the check
If the host receives a mission mode event and by the time it can get
to processing it, the register accesses fail implying a connectivity
error, MHI should move to an error state. This helps avoid longer wait
times from a synchronous power up perspective and accurately reflects
the MHI execution en
Currently, there exist a set of if...else statements in the
mhi_pm_disable_transition() function which make handling system
error and disable transitions differently complex. To make that
cleaner and facilitate differences in behavior, separate these
two transitions for MHI host.
Signed-off-by: Bh
While powering down, the device may or may not acknowledge an MHI
RESET issued by host for a graceful shutdown scenario and end up
sending an incoming data packet after tasklets have been killed.
If a rogue device sends this interrupt for a data transfer event
ring update, it can result in a taskle
Correct the "error_read" label to say "error_ready_state" as that
is the appropriate usage of the label.
Signed-off-by: Bhaumik Bhatt
---
drivers/bus/mhi/core/boot.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/bus/mhi/core/boot.c b/drivers/bus/mhi/core/boot.
MHI work is currently scheduled on the global/system workqueue and can
encounter delays on a stressed system. To avoid those unforeseen
delays which can hamper bootup or shutdown times, use a dedicated high
priority workqueue instead of the global/system workqueue.
Signed-off-by: Bhaumik Bhatt
--
In some cases, the entry of device to RDDM execution environment
can occur after a significant amount of time has elapsed and a
SYS_ERROR state change event has already arrived. This can result
in scenarios where MHI controller and client drivers are unaware
of the error state of the device. Remove
Current design allows a controller to register with MHI successfully
without the need to have any IRQs available for use. If no IRQs are
available, power up requests to MHI can fail after a successful
registration with MHI. Improve the design by checking for the number
of IRQs available sooner with
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