-declaration]
>
> Signed-off-by: Josh Cartwright
Acked-by: Maxime Ripard
> ---
> Fixes multiplatform build error seen with today's linux-next-20121129.
>
> arch/arm/mach-sunxi/sunxi.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm/mach-sunx
possible to make the codes less error prone
> and gain some positive diff stat.
>
> Signed-off-by: Shawn Guo
Acked-by: Maxime Ripard
Maxime
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Hi Olof,
Le 18/12/2012 07:55, Olof Johansson a écrit :
> Maxime Ripard (1):
> ARM: sunxi: Change device tree naming scheme for sunxi
There's something odd about this one (commit 68136b10). The patch that
you seem to have applied differs from the one I sent. The DTs files
appe
Le 02/12/2012 15:40, Axel Lin a écrit :
> The of_device_id table is supposed to be zero-terminated.
Applied, thanks.
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Le 02/12/2012 16:08, Axel Lin a écrit :
> The of_device_id table is supposed to be zero-terminated.
Applied, thanks
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/?p=linux/kernel/git/arm/arm-soc.git;a=commit;h=5e51651de30677f9d36805de9c261bf80f415790
Thanks,
Maxime
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Commit 09f6ffde introduced a dependency on USB_EHCI_HCD for the chipidea
USB host driver, that in turns depends on USB_ARCH_HAS_EHCI.
If this symbol is not set for MXS, the MXS boards are not able to use the
chipidea driver anymore.
Signed-off-by: Maxime Ripard
---
drivers/usb/Kconfig |1
anymore.
Signed-off-by: Maxime Ripard
---
drivers/usb/Kconfig |1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
index 4c90b51..640ae6c 100644
--- a/drivers/usb/Kconfig
+++ b/drivers/usb/Kconfig
@@ -37,6 +37,7 @@ config USB_ARCH_HAS_EHCI
ge the dtsi update through arm-soc -- while you need
>> both, nothing is broken by having just one or the other, so taking the
>> separate merge paths are fine.
>>
>> Linus, Grant, sound ok to you?
>
> Sure. But I have requested a few changes to the patch set...
And we n
Hi Linus,
On 10/01/2013 12:06, Linus Walleij wrote:
> On Fri, Jan 4, 2013 at 5:45 PM, Maxime Ripard
> wrote:
>> +static int __devinit
>> +sunxi_pinctrl_register_gpio_ranges(struct sunxi_pinctrl *pctl)
>> +{
>> + int id = 0, base = 0, npins = 1, i, pr
i and
> drivers/clocksource by Stephen Warren.
I finally had some time to test your changes on sunxi, and you can add
for patches 1 and 3:
Acked-by: Maxime Ripard
Maxime
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Signed-off-by: Maxime Ripard
---
drivers/tty/serial/8250/8250_dw.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/tty/serial/8250/8250_dw.c
b/drivers/tty/serial/8250/8250_dw.c
index 1d0dba2..096d2ef 100644
--- a/drivers/tty/serial/8250/8250_dw.c
+++ b/drivers/tty
The UART controller used in the A10/A13 is the Synopsys DesignWare 8250.
The wrong use of a regular 8250 driver may lead to a oops during kernel
boot with "irq 17: nobody cared", because the apb UART as an extra
interrupt that gets raised when writing to the LCR when busy.
Signed-off-
Hi,
This patch adds support for the GPIOs for the Allwinner SoCs supported so
far.
It comes on top of my previous pinctrl patchset, and has been tested on a
A13-Olinuxino from Olimex.
Thanks,
Maxime
Maxime Ripard (2):
ARM: sunxi: gpio: Add Allwinner SoCs GPIO drivers
ARM: sunxi: Add the
need to probe a generic driver to handle
the banks available for each SoC.
This driver has been tested on a A13-Olinuxino.
Signed-off-by: Maxime Ripard
---
.../devicetree/bindings/gpio/gpio-sunxi.txt| 77 ++
drivers/gpio/Kconfig |6 +
drivers
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/sun5i-a13.dtsi | 51 ++
1 file changed, 51 insertions(+)
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index e112189..dc650a6 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
n IRC, it seems that the fix would be to replace
all the calls to fls(chip->gpio_chip.ngpio) by fls(chip->gpio_chip.ngpio
- 1).
Also, all the irq handling is not compiling anymore for trivial errors
(variables not defined, incompatible types, etc.). So obviously, I
couldn't test the changes you ma
ath_null+0x1c/0x24) from []
(irq_domain_legacy_revmap+0x2c/0x48)
[ 30.821187] [] (irq_domain_legacy_revmap+0x2c/0x48) from
[] (pca953x_irq_handler+0x16c/0x1ac)
[ 30.831656] [] (pca953x_irq_handler+0x16c/0x1ac) from []
(irq_thread+0xd0/0x124)
[ 30.841000] [] (irq_thread+0xd0/0x124) from []
(
Hi Gregory,
On 08/01/2013 09:58, Gregory CLEMENT wrote:
> On 01/08/2013 09:32 AM, Maxime Ripard wrote:
>> On 07/01/2013 23:51, Gregory CLEMENT wrote:
>>> static irqreturn_t pca953x_irq_handler(int irq, void *devid)
>>> {
>>> struct pca953x_chi
Some pin configurations IP allows to set the current output to the pin.
This patch adds such a parameter to the pinconf-generic mechanism.
This parameter takes as argument the drive strength in mA.
Signed-off-by: Maxime Ripard
---
include/linux/pinctrl/pinconf-generic.h |3 +++
1 file
gpio part will come
eventually.
Signed-off-by: Maxime Ripard
---
.../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 60 +++
arch/arm/mach-sunxi/Kconfig|1 +
drivers/pinctrl/Kconfig|5 +
drivers/pinctrl/Makefile
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/sun5i-a13.dtsi |9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 59a2d26..707bef5 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/sun5i-a13-olinuxino.dts |2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
index 498a091..4a1e45d 100644
--- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
Use pinctrl to configure the SoCs pins directly from the driver.
Signed-off-by: Maxime Ripard
---
drivers/tty/serial/of_serial.c |7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/tty/serial/of_serial.c b/drivers/tty/serial/of_serial.c
index e7cae1c..e9f3289 100644
--- a
Since the Allwinner SoCs variants don't have the same set of pins to
handle, we need to declare the pin ranges available.
Signed-off-by: Maxime Ripard
---
drivers/pinctrl/pinctrl-sunxi.c | 253 +++
1 file changed, 253 insertions(+)
diff --git a/dr
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/sun5i-a13.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 707bef5..e112189 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts
t;allwinner,sun7i-sid";
I'd prefer to have sun7i-a20-sid here. We usually mention the soc name
as well in the compatible when it's not the good ol' A10.
> + reg = <0x01c23800 0x200>;
> + };
> +
> +
Drop the extra line
Thanks,
Maxi
ize = sid_data->keysize; /* ugly */
Ugly? Why?
> + if (device_create_bin_file(&pdev->dev, &sid_bin_attr)) /* fixme */
And what is there to fix here?
For these two comments, either explain what you find so ugly/broken so
that someone reading your code can get what is wrong, or just remove
them, because keeping them like that is just confusing.
Maxime
> + return -ENODEV;
> +
> + entropy = kzalloc(sizeof(u8) * sid_data->keysize, GFP_KERNEL);
> + for (i = 0; i < sid_data->keysize; i++)
> + entropy[i] = sunxi_sid_read_byte(sid_data, i);
> + add_device_randomness(entropy, sid_data->keysize);
> + kfree(entropy);
> +
> + dev_dbg(&pdev->dev, "loaded\n");
> +
> + return 0;
> +}
> +
> +static struct platform_driver sunxi_sid_driver = {
> + .probe = sunxi_sid_probe,
> + .remove = sunxi_sid_remove,
> + .driver = {
> + .name = DRV_NAME,
> + .owner = THIS_MODULE,
> + .of_match_table = sunxi_sid_of_match,
> + /* .groups = sunxi_sid_groups, proper way */
> + },
> +};
> +module_platform_driver(sunxi_sid_driver);
> +
> +MODULE_AUTHOR("Oliver Schinagl ");
> +MODULE_DESCRIPTION("Allwinner sunxi security id driver");
> +MODULE_LICENSE("GPL");
> --
> 1.8.1.5
>
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Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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> of the of_iomap().
>
> Signed-off-by: Jisheng Zhang
It looks fine for me.
Acked-by: Maxime Ripard
Thanks!
Maxime
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Embedded Linux, Kernel and Android engineering
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erman Yin
> Cc: Maxime Ripard
> Signed-off-by: Linus Walleij
Acked-by: Maxime Ripard
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and the associated documentation for the A20.
Thanks,
Maxime
Maxime Ripard (2):
clk: sunxi: Add Allwinner A20 gates
ARM: sun7i: Enable the A20 clocks in the DTSI
Documentation/devicetree/bindings/clock/sunxi.txt | 3 +
.../bindings/clock/sunxi/sun7i-a20-gates.txt | 98
Now that the clock driver knows about the available clocks found on the
A20, we can build up the clock tree from the device tree.
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/sun7i-a20.dtsi | 126 +++
1 file changed, 116 insertions(+), 10 deletions
need to register different clock gates for the A20.
Signed-off-by: Maxime Ripard
---
Documentation/devicetree/bindings/clock/sunxi.txt | 3 +
.../bindings/clock/sunxi/sun7i-a20-gates.txt | 98 ++
drivers/clk/sunxi/clk-sunxi.c | 15
3 files ch
On Mon, Aug 12, 2013 at 10:19:16AM +0200, Maxime Ripard wrote:
> Hi Linus,
>
> On Sun, Aug 04, 2013 at 11:47:34AM +0200, Maxime Ripard wrote:
> > The Allwinner A31 SoC uses the same IP than the one found in the
> > A10/A13, with only different pins. Add the pins and the ass
On Mon, Aug 12, 2013 at 10:27:49AM +0200, Maxime Ripard wrote:
> Hi Linus,
>
> On Sun, Aug 04, 2013 at 11:58:46AM +0200, Maxime Ripard wrote:
> > Some pin functions in the array were not indented like the other
> > functions in this array. Fix this.
>
> Could you ple
On Mon, Aug 12, 2013 at 10:33:19AM +0200, Maxime Ripard wrote:
> Hi Linus,
>
> On Sun, Aug 04, 2013 at 11:58:45AM +0200, Maxime Ripard wrote:
> > The Allwinner A20 is pin-compatible with the older A10, so the two pin
> > set are quite similar. However, since the A20 has n
Hi Emilio,
On Mon, Aug 19, 2013 at 05:14:57PM -0300, Emilio López wrote:
> El 05/08/13 17:43, Maxime Ripard escribió:
> >The A31 has a mostly different clock set compared to the other older
> >SoCs currently supported in the Allwinner clock driver.
> >
> >Add support
quot;Allwinner Sunxi SOCs" if ARCH_MULTI_V7
I wonder if the sunxi (apart the weird letter case) is actually
needed. Maybe we can just put "Allwinner SoCs" (it would be great if
you could fix the SoCs case too).
Thanks!
Maxime
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Embedded Linu
Moving from void* to u8* removes the need for castslater on in the
function.
Signed-off-by: Maxime Ripard
---
drivers/video/backlight/hx8357.c |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/video/backlight/hx8357.c b/drivers/video/backlight/hx8357.c
index
In case of a failing allocation, a dump stack will be printed anyway, so
the dev_err is redundant.
Signed-off-by: Maxime Ripard
---
drivers/video/backlight/hx8357.c |4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/video/backlight/hx8357.c b/drivers/video
This allows a smaller and less error-prone code by using static arrays
and the ARRAY_SIZE macro.
Signed-off-by: Maxime Ripard
---
drivers/video/backlight/hx8357.c | 173 +-
1 file changed, 95 insertions(+), 78 deletions(-)
diff --git a/drivers/video
Signed-off-by: Maxime Ripard
---
drivers/video/backlight/hx8357.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/video/backlight/hx8357.c b/drivers/video/backlight/hx8357.c
index 7c82561..6da8ebe 100644
--- a/drivers/video/backlight/hx8357.c
+++ b/drivers/video
The element size and the number of elements was inverted in the kcalloc
call.
Signed-off-by: Maxime Ripard
---
drivers/video/backlight/hx8357.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/video/backlight/hx8357.c b/drivers/video/backlight/hx8357.c
index
up->dev, MSEC_PER_SEC);
> + pm_runtime_use_autosuspend(qup->dev);
> + pm_runtime_enable(qup->dev);
Since the device is already woken up, you probably need to call
pm_runtime_set_active here.
Maxime
--
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Embedded Linux, Kernel and Android engineering
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On Tue, Feb 18, 2014 at 04:10:38PM +0100, Hans de Goede wrote:
> Hi,
>
> On 02/18/2014 03:22 PM, Maxime Ripard wrote:
> >On Mon, Feb 17, 2014 at 11:02:41AM +0100, David Lanzendörfer wrote:
> >>Signed-off-by: David Lanzendörfer
> >>Signed-off-by: Hans de Goede
gt;>
> >> Nope, we only need this to get the data on sunxi_mmc_remove,
> >> everywhere else the data is found through the mmc-host struct.
> >
> > Still, if anyone makes a following patch using the platform_device
> > for some reason, we will have a race condition, without any way to
> > notice it.
> >
> > Plus, you're doing all the other bits of initialization of your
> > structures much earlier, why not be consistent and having all of
> > them at the same place?
>
> Most platform drivers I've worked on do platform_set_drvdata as late
> as possible, so that the drvdata does not get set and never cleared
> in error paths.
You don't actually have to clear it, and some frameworks actually
require you to call dev_set_drvdata before registration, so that
statement looks quite odd to me.
Thanks!
Maxime
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her.
> I can throw in a line for refering to the mmc slot gpio lib docs.
Yes, that would be great :)
> > Isn't the cd-gpios property requested too?
> I can refer to the docs there as well if you like... :-)
That would be great too :)
Thanks!
Maxime
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The A13 has 3 SPI controllers compatible with the one found in the A10. Add
them in the DT.
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/sun5i-a13.dtsi | 33 +
1 file changed, 33 insertions(+)
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot
controllers in a single
driver would be unreasonable, hence the addition of a new driver.
Like its more recent counterpart, it supports DMA, but the driver only does PIO
until we have a dmaengine driver for this platform.
Signed-off-by: Maxime Ripard
---
.../devicetree/bindings/spi/spi-sun4i.txt
The A10s has 3 SPI controllers compatible with the one found in the A10. Add
them in the DT.
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/sun5i-a10s.dtsi | 33 +
1 file changed, 33 insertions(+)
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi
b/arch/arm
The A10 has 4 SPI controllers that are now supported. Add them in the DT.
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/sun4i-a10.dtsi | 44
1 file changed, 44 insertions(+)
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i
doesn't support transfer larger than the FIFO size (64 bytes) for
now, It's one of the things that will be fixed whenever we will have
DMA support.
Thanks!
Maxime
Maxime Ripard (7):
spi: sunxi: Add Allwinner A10 SPI controller driver
ARM: dt: sun7i: Add A20 SPI controller nodes
The A20 has 4 SPI controllers compatible with the one found in the A10. Add
them in the DT.
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/sun7i-a20.dtsi | 44
1 file changed, 44 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm
The A20-Olinuxino-micro has two SPI bus exposed on its UEXT connectors, enable
them.
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
b/arch
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/sun7i-a20.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 0f0ee58..6161fd8 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts
Hi,
On Sun, Feb 23, 2014 at 11:15:30AM +0900, Mark Brown wrote:
> On Sat, Feb 22, 2014 at 10:35:53PM +0100, Maxime Ripard wrote:
> > The older Allwinner SoCs (A10, A13, A10s and A20) all have the
> > same SPI controller.
>
> Applied, thanks. Please differentiate between
On Sat, Feb 22, 2014 at 10:35:52PM +0100, Maxime Ripard wrote:
> Hi,
>
> This patchset brings support for the SPI controller found in the
> Allwinner A10 and derived SoCs.
>
> Even though the controller supports DMA, the driver only supports PIO
> mode for now. This driver
troller is able to memory-to-memory or memory-to-device transfers on
the 16 channels in parallel.
Signed-off-by: Maxime Ripard
---
.../devicetree/bindings/dma/sun6i-dma.txt | 45 +
drivers/dma/Kconfig| 8 +
drivers/dma/Makefile
Prevent the SDRAM controller from being gated by force-enabling it in the clock
driver.
Signed-off-by: Maxime Ripard
---
drivers/clk/sunxi/clk-sunxi.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 6cfcd23..d9b4a41
Now that we have a DMA driver, we can add the DMA bindings in the DTSI for the
controller and the devices supported that can use DMA.
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/sun6i-a31.dtsi | 29 +
1 file changed, 29 insertions(+)
diff --git a/arch/arm
Hi,
This patchset adds support for the DMA controller found in the
Allwinner A31 and A23 SoCs.
This has been tested using the newly introduced SPI driver on an A31
EVK. Support for DMA-driven SPI transfers will be the subject of
another patch serie.
Thanks,
Maxime
Maxime Ripard (5):
clk
In order for the DMA controller to work for SDRAM to devices transfers, the AHB
clock should be reparented on the PLL6.
Force that parenting in the clock driver.
Signed-off-by: Maxime Ripard
---
drivers/clk/sunxi/clk-sunxi.c | 18 +-
1 file changed, 17 insertions(+), 1 deletion
Right now, AHB is an indirect child clock of the CPU clock. If that happens to
change, since the CPU clock has no other consumers declared in Linux, it would
be shut down, which is not really a good idea.
Prevent this by forcing it enabled.
Signed-off-by: Maxime Ripard
---
drivers/clk/sunxi
off-by: Maxime Ripard
Cc: sta...@vger.kernel.org
---
drivers/spi/spi.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index 23756b0..39f12be 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -756,8 +756,6 @@ static void spi_pump_messages(
Hi Geert,
On Mon, Feb 17, 2014 at 07:02:09PM +0100, Geert Uytterhoeven wrote:
> On Mon, Feb 17, 2014 at 6:20 PM, Maxime Ripard
> wrote:
> > When the generic implementation of the transfer_one_message callback was
> > called
> > by the spi_pump_messages function, if t
ed it, you can add my Acked-by
Maxime
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On Mon, Feb 17, 2014 at 11:02:28AM +0100, David Lanzendörfer wrote:
> From: Hans de Goede
>
> Signed-off-by: Hans de Goede
Again, your SoB is missing, and that can be squashed with the previous
patch.
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ht
ework road, some documentation on what are the
arguments it takes and what it's supposed to return would be great.
Thanks!
Maxime
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pio: pinctrl@01c20800 {
> compatible = "allwinner,sun7i-a20-pinctrl";
> reg = <0x01c20800 0x400>;
> @@ -432,6 +472,27 @@
> allwinner,drive = <0>;
> allwinner,pull = <0>;
efine SDXC_END_BIT_ERROR BIT(15)
> +#define SDXC_SDIO_INTERRUPT BIT(16)
> +#define SDXC_CARD_INSERT BIT(30)
> +#define SDXC_CARD_REMOVE BIT(31)
> +#define SDXC_INTERRUPT_ERROR_BIT (SDXC_RESP_ERROR |
> SDXC_RESP_CRC_ERROR | \
;&mmc0_clk>;
> + clock-names = "ahb", "mod";
You never talked about the clock-names property, and which clocks were
supposed to be provided.
> + interrupts = <0 32 4>;
> + bus-width = <4>;
And you never talked about bus-width either.
> + status = "disabled";
> +};
>
Isn't the cd-gpios property requested too?
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Hi Hans,
On Tue, Feb 18, 2014 at 09:49:21PM +0100, Hans de Goede wrote:
> Hi,
>
> On 02/18/2014 04:37 PM, Maxime Ripard wrote:
>
>
>
> >>+
> >>+ for (i = 0; i < data->sg_len; i++) {
> >>+ pdes[i
t-address should go, and the names made unique through other means.
What do you suggest to make the name unique then?
The ePAPR is pretty clear that the above is the way to go, so I'm
unclear on what you have in mind here.
Plus, I haven't seen anywhere that reg was actually mandatory.
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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stem to hang.
>
> Cc: sta...@vger.kernel.org
> Signed-off-by: Chen-Yu Tsai
Acked-by: Maxime Ripard
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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The A31 has 4 SPI controllers. Add them in the DTSI.
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/sun6i-a31.dtsi | 40
1 file changed, 40 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index ae058eb
doesn't support transfer larger than the FIFO size (128 bytes) for
now, so this is kind of a blocker against inclusion, but I expect it
to be fixed by v2.
Thanks!
Maxime
Maxime Ripard (4):
clk: sunxi: Add support for PLL6 on the A31
ARM: sun6i: dt: Add PLL6 and SPI module clocks
spi: sunxi
The A31 has a slightly different PLL6 clock. Add support for this new clock in
our driver.
Signed-off-by: Maxime Ripard
---
Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
drivers/clk/sunxi/clk-sunxi.c | 45 +++
2 files changed, 46 insertions
The module clocks in the A31 are still compatible with the A10 one. Add the SPI
module clocks and the PLL6 in the device tree to allow their use by the SPI
controllers.
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/sun6i-a31.dtsi | 48 +++-
1 file
The Allwinner A31 has a new SPI controller IP compared to the older Allwinner
SoCs.
It supports DMA, but the driver only does PIO for now, and DMA will be
supported eventually.
Signed-off-by: Maxime Ripard
---
.../devicetree/bindings/spi/spi-sun6i.txt | 23 +
drivers/spi/Makefile
Hi Mark,
On Thu, Jan 16, 2014 at 07:40:03PM +, Mark Brown wrote:
> On Thu, Jan 16, 2014 at 06:11:24PM +0100, Maxime Ripard wrote:
>
> Looks pretty clean, a few fairly small things below.
>
> > +- clocks: phandle to the clocks feeding the SPI controller. Two are
>
Hi Arnd,
On Wed, Jan 15, 2014 at 10:40:56AM +0100, Arnd Bergmann wrote:
> On Wednesday 15 January 2014 10:10:06 Maxime Ripard wrote:
> > On Thu, Jan 09, 2014 at 04:34:04PM +0100, Gerardo Di Iorio wrote:
> > > Change the AllWinner A1X SOCs to Allwinner Sunxi SOCs
> >
Hi Josh,
On Thu, Jan 16, 2014 at 12:15:28PM -0600, Josh Cartwright wrote:
> On Thu, Jan 16, 2014 at 06:11:23PM +0100, Maxime Ripard wrote:
> > The module clocks in the A31 are still compatible with the A10 one. Add the
> > SPI
> > module clocks and the PLL6 in the device tr
The module clocks in the A31 are still compatible with the A10 one. Add the SPI
module clocks and the PLL6 in the device tree to allow their use by the SPI
controllers.
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/sun6i-a31.dtsi | 46
1 file
The A31 has a slightly different PLL6 clock. Add support for this new clock in
our driver.
Signed-off-by: Maxime Ripard
---
Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
drivers/clk/sunxi/clk-sunxi.c | 45 +++
2 files changed, 46 insertions
The Allwinner A31 has a new SPI controller IP compared to the older Allwinner
SoCs.
It supports DMA, but the driver only does PIO for now, and DMA will be
supported eventually.
Signed-off-by: Maxime Ripard
---
.../devicetree/bindings/spi/spi-sun6i.txt | 24 ++
drivers/spi/Kconfig
n the FIFO
size, instead of silently timeouting.
- Added a Kconfig symbol
- Move the clock ratio change at transfer time
- Fixed the PLL6 cell size in the DTSI
- A few fixes here and there: typos, etc.
Maxime Ripard (5):
clk: sunxi: Add support for PLL6 on the A31
ARM: sun6i: dt: Add
Signed-off-by: Maxime Ripard
---
arch/arm/configs/sunxi_defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/configs/sunxi_defconfig
index 3e2259b..b5df4a5 100644
--- a/arch/arm/configs/sunxi_defconfig
+++ b/arch/arm/configs/sunxi_defconfig
The A31 has 4 SPI controllers. Add them in the DTSI.
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/sun6i-a31.dtsi | 40
1 file changed, 40 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 0eea325
On Wed, Jan 29, 2014 at 12:25:20PM +, Mark Brown wrote:
> On Wed, Jan 29, 2014 at 12:10:48PM +0100, Maxime Ripard wrote:
>
> > +config SPI_SUN6I
> > + tristate "Allwinner A31 SPI controller"
> > + depends on ARCH_SUNXI || COMPILE_TEST
> > + selec
Hi Kevin,
On Thu, Jan 30, 2014 at 03:52:16PM -0800, Kevin Hilman wrote:
> On Wed, Jan 29, 2014 at 5:32 AM, Maxime Ripard
> wrote:
> > On Wed, Jan 29, 2014 at 12:25:20PM +, Mark Brown wrote:
> >> On Wed, Jan 29, 2014 at 12:10:48PM +0100, Maxime Ripard wrote:
> >
devm_spi_alloc_master, and converted the users of
devm_spi_register_master to use it.
Maxime Ripard (3):
spi: core: Add devm_spi_alloc_master
spi: core: Update the devm_spi_register_master documentation
spi: switch to devm_spi_alloc_master
drivers/spi/spi-atmel.c | 8 +++-
drivers/spi
Make the existing users of devm_spi_register_master use the
devm_spi_alloc_master function to avoid leaking memory.
Signed-off-by: Maxime Ripard
---
drivers/spi/spi-atmel.c | 8 +++-
drivers/spi/spi-bcm2835.c| 15 +--
drivers/spi/spi-bcm63xx-hsspi.c | 8
devm_spi_alloc_master to provide the intended behaviour.
Signed-off-by: Maxime Ripard
---
drivers/spi/spi.c | 36
include/linux/spi/spi.h | 2 ++
2 files changed, 38 insertions(+)
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index 63613a9..eb728ec 100644
--- a
want to use the devm_spi_alloc_master function in such case.
Signed-off-by: Maxime Ripard
---
drivers/spi/spi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index eb728ec..dc577b7 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
Signed-off-by: Maxime Ripard
---
arch/arm/configs/sunxi_defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/configs/sunxi_defconfig
index 3e2259b..b5df4a5 100644
--- a/arch/arm/configs/sunxi_defconfig
+++ b/arch/arm/configs/sunxi_defconfig
The A31 has 4 SPI controllers. Add them in the DTSI.
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/sun6i-a31.dtsi | 40
1 file changed, 40 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 0eea325
The module clocks in the A31 are still compatible with the A10 one. Add the SPI
module clocks and the PLL6 in the device tree to allow their use by the SPI
controllers.
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/sun6i-a31.dtsi | 46
1 file
The Allwinner A31 has a new SPI controller IP compared to the older Allwinner
SoCs.
It supports DMA, but the driver only does PIO for now, and DMA will be
supported eventually.
Signed-off-by: Maxime Ripard
---
.../devicetree/bindings/spi/spi-sun6i.txt | 24 ++
drivers/spi/Kconfig
ded a Kconfig symbol
- Move the clock ratio change at transfer time
- Fixed the PLL6 cell size in the DTSI
- A few fixes here and there: typos, etc.
Maxime Ripard (5):
clk: sunxi: Add support for PLL6 on the A31
ARM: sun6i: dt: Add PLL6 and SPI module clocks
spi: sunxi: Add Allwinner A3
The A31 has a slightly different PLL6 clock. Add support for this new clock in
our driver.
Signed-off-by: Maxime Ripard
---
Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
drivers/clk/sunxi/clk-sunxi.c | 45 +++
2 files changed, 46 insertions
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