[PATCH V6 8/9] clk: imx: implement new clk_hw based APIs

Clock providers are recommended to use the new struct clk_hw based API, so implement IMX clk_hw based provider helpers functions to the new approach. Signed-off-by: Dong Aisheng --- ChangeLog: v2->v4: * no changes v1->v2: new patches --- drivers/clk/imx/clk.c | 22 ++

[PATCH V6 8/9] clk: imx: implement new clk_hw based APIs

Clock providers are recommended to use the new struct clk_hw based API, so implement IMX clk_hw based provider helpers functions to the new approach. Signed-off-by: Dong Aisheng --- ChangeLog: v2->v4: * no changes v1->v2: new patches --- drivers/clk/imx/clk.c | 22 ++

[PATCH V6 9/9] clk: imx: add imx7ulp clk driver

i.MX7ULP Clock functions are under joint control of the System Clock Generation (SCG) modules, Peripheral Clock Control (PCC) modules, and Core Mode Controller (CMC)1 blocks The clocking scheme provides clear separation between M4 domain and A7 domain. Except for a few clock sources shared

[PATCH V6 6/9] dt-bindings: clock: add imx7ulp clock binding doc

i.MX7ULP Clock functions are under joint control of the System Clock Generation (SCG) modules, Peripheral Clock Control (PCC) modules, and Core Mode Controller (CMC)1 blocks Note IMX7ULP has two clock domains: M4 and A7. This binding doc is only for A7 clock domain. Cc: Rob Herring Cc: Mark

[PATCH V6 9/9] clk: imx: add imx7ulp clk driver

i.MX7ULP Clock functions are under joint control of the System Clock Generation (SCG) modules, Peripheral Clock Control (PCC) modules, and Core Mode Controller (CMC)1 blocks The clocking scheme provides clear separation between M4 domain and A7 domain. Except for a few clock sources shared

[PATCH V6 6/9] dt-bindings: clock: add imx7ulp clock binding doc

i.MX7ULP Clock functions are under joint control of the System Clock Generation (SCG) modules, Peripheral Clock Control (PCC) modules, and Core Mode Controller (CMC)1 blocks Note IMX7ULP has two clock domains: M4 and A7. This binding doc is only for A7 clock domain. Cc: Rob Herring Cc: Mark

[PATCH V6 3/9] clk: imx: add pllv4 support

pllv4 is designed for System Clock Generation (SCG) module observed in IMX ULP SoC series. e.g. i.MX7ULP. The SCG modules generates clock used to derive processor, system, peripheral bus and external memory interface clocks while this patch intends to support the PLL part. Cc: Stephen Boyd Cc:

[PATCH V6 4/9] clk: imx: add pfdv2 support

The pfdv2 is designed for PLL Fractional Divide (PFD) observed in System Clock Generation (SCG) module in IMX ULP SoC series. e.g. i.MX7ULP. NOTE pfdv2 can only be operated when clk is gated. Cc: Stephen Boyd Cc: Michael Turquette Cc: Shawn Guo Cc: Anson Huang Cc: Bai Ping Signed-off-by:

[PATCH V6 5/9] clk: imx: add imx7ulp composite clk support

The imx composite clk is designed for Peripheral Clock Control (PCC) module observed in IMX ULP SoC series. NOTE pcc can only be operated when clk is gated. Cc: Stephen Boyd Cc: Michael Turquette Cc: Shawn Guo Cc: Anson Huang Cc: Bai Ping Signed-off-by: Dong Aisheng --- ChangeLog: v4->v5:

[PATCH V6 3/9] clk: imx: add pllv4 support

pllv4 is designed for System Clock Generation (SCG) module observed in IMX ULP SoC series. e.g. i.MX7ULP. The SCG modules generates clock used to derive processor, system, peripheral bus and external memory interface clocks while this patch intends to support the PLL part. Cc: Stephen Boyd Cc:

[PATCH V6 4/9] clk: imx: add pfdv2 support

The pfdv2 is designed for PLL Fractional Divide (PFD) observed in System Clock Generation (SCG) module in IMX ULP SoC series. e.g. i.MX7ULP. NOTE pfdv2 can only be operated when clk is gated. Cc: Stephen Boyd Cc: Michael Turquette Cc: Shawn Guo Cc: Anson Huang Cc: Bai Ping Signed-off-by:

[PATCH V6 5/9] clk: imx: add imx7ulp composite clk support

The imx composite clk is designed for Peripheral Clock Control (PCC) module observed in IMX ULP SoC series. NOTE pcc can only be operated when clk is gated. Cc: Stephen Boyd Cc: Michael Turquette Cc: Shawn Guo Cc: Anson Huang Cc: Bai Ping Signed-off-by: Dong Aisheng --- ChangeLog: v4->v5:

[PATCH V6 0/9] clk: add imx7ulp clk support

This patch series intends to add imx7ulp clk support. i.MX7ULP Clock functions are under joint control of the System Clock Generation (SCG) modules, Peripheral Clock Control (PCC) modules, and Core Mode Controller (CMC)1 blocks The clocking scheme provides clear separation between M4 domain and

[PATCH V6 1/9] clk: imx: add gatable clock divider support

For dividers with zero indicating clock is disabled, instead of giving a warning each time like "clkx: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set" in exist code, we'd like to introduce enable/disable function for it. e.g. 000b - Clock disabled 001b - Divide by 1 010b - Divide by 2 ... Set

[PATCH V6 7/9] clk: imx: make mux parent strings const

As the commit 2893c379461a ("clk: make strings in parent name arrays const"), let's make the parent strings const, otherwise we may meet the following warning when compiling: drivers/clk/imx/clk-imx7ulp.c: In function 'imx7ulp_clocks_init': drivers/clk/imx/clk-imx7ulp.c:73:35: warning: passing

[PATCH V6 2/9] clk: fractional-divider: add CLK_FRAC_DIVIDER_ZERO_BASED flag support

Adding CLK_FRAC_DIVIDER_ZERO_BASED flag to indicate the numerator and denominator value in register are start from 0. This can be used to support frac dividers like below: Divider output clock = Divider input clock x [(frac +1) / (div +1)] where frac/div in register is: 000b - Divide by 1. 001b -

[PATCH V6 0/9] clk: add imx7ulp clk support

This patch series intends to add imx7ulp clk support. i.MX7ULP Clock functions are under joint control of the System Clock Generation (SCG) modules, Peripheral Clock Control (PCC) modules, and Core Mode Controller (CMC)1 blocks The clocking scheme provides clear separation between M4 domain and

[PATCH V6 1/9] clk: imx: add gatable clock divider support

For dividers with zero indicating clock is disabled, instead of giving a warning each time like "clkx: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set" in exist code, we'd like to introduce enable/disable function for it. e.g. 000b - Clock disabled 001b - Divide by 1 010b - Divide by 2 ... Set

[PATCH V6 7/9] clk: imx: make mux parent strings const

As the commit 2893c379461a ("clk: make strings in parent name arrays const"), let's make the parent strings const, otherwise we may meet the following warning when compiling: drivers/clk/imx/clk-imx7ulp.c: In function 'imx7ulp_clocks_init': drivers/clk/imx/clk-imx7ulp.c:73:35: warning: passing

[PATCH V6 2/9] clk: fractional-divider: add CLK_FRAC_DIVIDER_ZERO_BASED flag support

Adding CLK_FRAC_DIVIDER_ZERO_BASED flag to indicate the numerator and denominator value in register are start from 0. This can be used to support frac dividers like below: Divider output clock = Divider input clock x [(frac +1) / (div +1)] where frac/div in register is: 000b - Divide by 1. 001b -

RE: [PATCH RESEND V4 1/9] clk: clk-divider: add CLK_DIVIDER_ZERO_GATE clk support

Hi Michael, > -Original Message- > From: Michael Turquette [mailto:mturque...@baylibre.com] [...] > Hi Dong, > > Quoting A.s. Dong (2018-10-21 06:10:48) > > For dividers with zero indicating clock is disabled, instead of giving > > a warning each ti

RE: [PATCH RESEND V4 1/9] clk: clk-divider: add CLK_DIVIDER_ZERO_GATE clk support

Hi Michael, > -Original Message- > From: Michael Turquette [mailto:mturque...@baylibre.com] [...] > Hi Dong, > > Quoting A.s. Dong (2018-10-21 06:10:48) > > For dividers with zero indicating clock is disabled, instead of giving > > a warning each ti

RE: [PATCH] pinctrl: imx: make sure that maps are fully initialized

scu or by mmio using a non-default pad > config. Increment the counter only if a new map was created. > > Fixes: b96eea718bf6 ("pinctrl: fsl: add scu based pinctrl support") > Cc: A.s. Dong > Signed-off-by: Martin Kaiser Thanks for reporting this issue. The original co

RE: [PATCH] pinctrl: imx: make sure that maps are fully initialized

scu or by mmio using a non-default pad > config. Increment the counter only if a new map was created. > > Fixes: b96eea718bf6 ("pinctrl: fsl: add scu based pinctrl support") > Cc: A.s. Dong > Signed-off-by: Martin Kaiser Thanks for reporting this issue. The original co

RE: [PATCH v9 3/5] clk: imx: add SCCG PLL type

Hi Stephen, [...] > > I already sent the 12th version of this current patch series and I > > would really like to get this in ASAP so that the booting up of imx8mq will > not be delayed. > > > > Ok. Well we're in rc1 right now, and so we're not merging new drivers into > mainline. I can merge

RE: [PATCH v9 3/5] clk: imx: add SCCG PLL type

Hi Stephen, [...] > > I already sent the 12th version of this current patch series and I > > would really like to get this in ASAP so that the booting up of imx8mq will > not be delayed. > > > > Ok. Well we're in rc1 right now, and so we're not merging new drivers into > mainline. I can merge

[PATCH V5 3/9] clk: imx: add pllv4 support

pllv4 is designed for System Clock Generation (SCG) module observed in IMX ULP SoC series. e.g. i.MX7ULP. The SCG modules generates clock used to derive processor, system, peripheral bus and external memory interface clocks while this patch intends to support the PLL part. Cc: Stephen Boyd Cc:

[PATCH V5 8/9] clk: imx: implement new clk_hw based APIs

Clock providers are recommended to use the new struct clk_hw based API, so implement IMX clk_hw based provider helpers functions to the new approach. Signed-off-by: Dong Aisheng --- ChangeLog: v2->v4: * no changes v1->v2: new patches --- drivers/clk/imx/clk.c | 22 ++

[PATCH V5 2/9] clk: fractional-divider: add CLK_FRAC_DIVIDER_ZERO_BASED flag support

Adding CLK_FRAC_DIVIDER_ZERO_BASED flag to indicate the numerator and denominator value in register are start from 0. This can be used to support frac dividers like below: Divider output clock = Divider input clock x [(frac +1) / (div +1)] where frac/div in register is: 000b - Divide by 1. 001b -

[PATCH V5 4/9] clk: imx: add pfdv2 support

The pfdv2 is designed for PLL Fractional Divide (PFD) observed in System Clock Generation (SCG) module in IMX ULP SoC series. e.g. i.MX7ULP. NOTE pfdv2 can only be operated when clk is gated. Cc: Stephen Boyd Cc: Michael Turquette Cc: Shawn Guo Cc: Anson Huang Cc: Bai Ping Signed-off-by:

[PATCH V5 3/9] clk: imx: add pllv4 support

pllv4 is designed for System Clock Generation (SCG) module observed in IMX ULP SoC series. e.g. i.MX7ULP. The SCG modules generates clock used to derive processor, system, peripheral bus and external memory interface clocks while this patch intends to support the PLL part. Cc: Stephen Boyd Cc:

[PATCH V5 8/9] clk: imx: implement new clk_hw based APIs

Clock providers are recommended to use the new struct clk_hw based API, so implement IMX clk_hw based provider helpers functions to the new approach. Signed-off-by: Dong Aisheng --- ChangeLog: v2->v4: * no changes v1->v2: new patches --- drivers/clk/imx/clk.c | 22 ++

[PATCH V5 2/9] clk: fractional-divider: add CLK_FRAC_DIVIDER_ZERO_BASED flag support

Adding CLK_FRAC_DIVIDER_ZERO_BASED flag to indicate the numerator and denominator value in register are start from 0. This can be used to support frac dividers like below: Divider output clock = Divider input clock x [(frac +1) / (div +1)] where frac/div in register is: 000b - Divide by 1. 001b -

[PATCH V5 4/9] clk: imx: add pfdv2 support

The pfdv2 is designed for PLL Fractional Divide (PFD) observed in System Clock Generation (SCG) module in IMX ULP SoC series. e.g. i.MX7ULP. NOTE pfdv2 can only be operated when clk is gated. Cc: Stephen Boyd Cc: Michael Turquette Cc: Shawn Guo Cc: Anson Huang Cc: Bai Ping Signed-off-by:

[PATCH V5 7/9] clk: imx: make mux parent strings const

As the commit 2893c379461a ("clk: make strings in parent name arrays const"), let's make the parent strings const, otherwise we may meet the following warning when compiling: drivers/clk/imx/clk-imx7ulp.c: In function 'imx7ulp_clocks_init': drivers/clk/imx/clk-imx7ulp.c:73:35: warning: passing

[PATCH V5 6/9] dt-bindings: clock: add imx7ulp clock binding doc

i.MX7ULP Clock functions are under joint control of the System Clock Generation (SCG) modules, Peripheral Clock Control (PCC) modules, and Core Mode Controller (CMC)1 blocks Note IMX7ULP has two clock domains: M4 and A7. This binding doc is only for A7 clock domain. Cc: Rob Herring Cc: Mark

[PATCH V5 9/9] clk: imx: add imx7ulp clk driver

i.MX7ULP Clock functions are under joint control of the System Clock Generation (SCG) modules, Peripheral Clock Control (PCC) modules, and Core Mode Controller (CMC)1 blocks The clocking scheme provides clear separation between M4 domain and A7 domain. Except for a few clock sources shared

[PATCH V5 5/9] clk: imx: add imx7ulp composite clk support

The imx composite clk is designed for Peripheral Clock Control (PCC) module observed in IMX ULP SoC series. NOTE pcc can only be operated when clk is gated. Cc: Stephen Boyd Cc: Michael Turquette Cc: Shawn Guo Cc: Anson Huang Cc: Bai Ping Signed-off-by: Dong Aisheng --- ChangeLog: v4->v5:

[PATCH V5 9/9] clk: imx: add imx7ulp clk driver

i.MX7ULP Clock functions are under joint control of the System Clock Generation (SCG) modules, Peripheral Clock Control (PCC) modules, and Core Mode Controller (CMC)1 blocks The clocking scheme provides clear separation between M4 domain and A7 domain. Except for a few clock sources shared

[PATCH V5 5/9] clk: imx: add imx7ulp composite clk support

The imx composite clk is designed for Peripheral Clock Control (PCC) module observed in IMX ULP SoC series. NOTE pcc can only be operated when clk is gated. Cc: Stephen Boyd Cc: Michael Turquette Cc: Shawn Guo Cc: Anson Huang Cc: Bai Ping Signed-off-by: Dong Aisheng --- ChangeLog: v4->v5:

[PATCH V5 7/9] clk: imx: make mux parent strings const

As the commit 2893c379461a ("clk: make strings in parent name arrays const"), let's make the parent strings const, otherwise we may meet the following warning when compiling: drivers/clk/imx/clk-imx7ulp.c: In function 'imx7ulp_clocks_init': drivers/clk/imx/clk-imx7ulp.c:73:35: warning: passing

[PATCH V5 6/9] dt-bindings: clock: add imx7ulp clock binding doc

i.MX7ULP Clock functions are under joint control of the System Clock Generation (SCG) modules, Peripheral Clock Control (PCC) modules, and Core Mode Controller (CMC)1 blocks Note IMX7ULP has two clock domains: M4 and A7. This binding doc is only for A7 clock domain. Cc: Rob Herring Cc: Mark

[PATCH V5 1/9] clk: clk-divider: add CLK_DIVIDER_ZERO_GATE clk support

For dividers with zero indicating clock is disabled, instead of giving a warning each time like "clkx: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set" in exist code, we'd like to introduce enable/disable function for it. e.g. 000b - Clock disabled 001b - Divide by 1 010b - Divide by 2 ... Set

[PATCH V5 0/9] clk: add imx7ulp clk support

This patch series intends to add imx7ulp clk support. i.MX7ULP Clock functions are under joint control of the System Clock Generation (SCG) modules, Peripheral Clock Control (PCC) modules, and Core Mode Controller (CMC)1 blocks The clocking scheme provides clear separation between M4 domain and

[PATCH V5 1/9] clk: clk-divider: add CLK_DIVIDER_ZERO_GATE clk support

For dividers with zero indicating clock is disabled, instead of giving a warning each time like "clkx: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set" in exist code, we'd like to introduce enable/disable function for it. e.g. 000b - Clock disabled 001b - Divide by 1 010b - Divide by 2 ... Set

[PATCH V5 0/9] clk: add imx7ulp clk support

This patch series intends to add imx7ulp clk support. i.MX7ULP Clock functions are under joint control of the System Clock Generation (SCG) modules, Peripheral Clock Control (PCC) modules, and Core Mode Controller (CMC)1 blocks The clocking scheme provides clear separation between M4 domain and

RE: [PATCH RESEND V4 0/9] clk: add imx7ulp clk support

> -Original Message- > From: Leonard Crestez > Sent: Tuesday, November 6, 2018 11:34 PM [...] > > On Tue, 2018-11-06 at 15:30 +, A.s. Dong wrote: > > Gently Ping... > > > drivers/clk/imx/clk-composite.c| 85 + > > Du

RE: [PATCH RESEND V4 0/9] clk: add imx7ulp clk support

> -Original Message- > From: Leonard Crestez > Sent: Tuesday, November 6, 2018 11:34 PM [...] > > On Tue, 2018-11-06 at 15:30 +, A.s. Dong wrote: > > Gently Ping... > > > drivers/clk/imx/clk-composite.c| 85 + > > Du

RE: [PATCH RESEND V4 0/9] clk: add imx7ulp clk support

Gently Ping... > -Original Message- > From: A.s. Dong > Sent: Sunday, October 21, 2018 9:15 PM > To: sb...@kernel.org > Cc: linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > mturque...@baylibre.com; shawn...@kernel.org; Anson Huang > ; Jac

RE: [PATCH RESEND V4 0/9] clk: add imx7ulp clk support

Gently Ping... > -Original Message- > From: A.s. Dong > Sent: Sunday, October 21, 2018 9:15 PM > To: sb...@kernel.org > Cc: linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > mturque...@baylibre.com; shawn...@kernel.org; Anson Huang > ; Jac

RE: [PATCH RESEND V4 6/9] dt-bindings: clock: add imx7ulp clock binding doc

> -Original Message- > From: Rob Herring [mailto:r...@kernel.org] > Sent: Tuesday, October 23, 2018 6:17 AM [...] > > On Sun, Oct 21, 2018 at 01:11:09PM +, A.s. Dong wrote: > > i.MX7ULP Clock functions are under joint control of the System Clock > &g

RE: [PATCH RESEND V4 6/9] dt-bindings: clock: add imx7ulp clock binding doc

> -Original Message- > From: Rob Herring [mailto:r...@kernel.org] > Sent: Tuesday, October 23, 2018 6:17 AM [...] > > On Sun, Oct 21, 2018 at 01:11:09PM +, A.s. Dong wrote: > > i.MX7ULP Clock functions are under joint control of the System Clock > &g

RE: [PATCH RESEND V4 0/9] clk: add imx7ulp clk support

> -Original Message- > From: A.s. Dong > Sent: Sunday, October 21, 2018 9:11 PM > To: linux-...@vger.kernel.org > Cc: linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > sb...@kernel.org; mturque...@baylibre.com; shawn...@kernel.org; Anson > Huang ; Jac

RE: [PATCH RESEND V4 0/9] clk: add imx7ulp clk support

> -Original Message- > From: A.s. Dong > Sent: Sunday, October 21, 2018 9:11 PM > To: linux-...@vger.kernel.org > Cc: linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > sb...@kernel.org; mturque...@baylibre.com; shawn...@kernel.org; Anson > Huang ; Jac

[PATCH RESEND V4 6/9] dt-bindings: clock: add imx7ulp clock binding doc

i.MX7ULP Clock functions are under joint control of the System Clock Generation (SCG) modules, Peripheral Clock Control (PCC) modules, and Core Mode Controller (CMC)1 blocks Note IMX7ULP has two clock domains: M4 and A7. This binding doc is only for A7 clock domain. Cc: Rob Herring Cc: Mark

[PATCH RESEND V4 3/9] clk: imx: add pllv4 support

pllv4 is designed for System Clock Generation (SCG) module observed in IMX ULP SoC series. e.g. i.MX7ULP. The SCG modules generates clock used to derive processor, system, peripheral bus and external memory interface clocks while this patch intends to support the PLL part. Cc: Stephen Boyd Cc:

[PATCH RESEND V4 2/9] clk: fractional-divider: add CLK_FRAC_DIVIDER_ZERO_BASED flag support

Adding CLK_FRAC_DIVIDER_ZERO_BASED flag to indicate the numerator and denominator value in register are start from 0. This can be used to support frac dividers like below: Divider output clock = Divider input clock x [(frac +1) / (div +1)] where frac/div in register is: 000b - Divide by 1. 001b -

[PATCH RESEND V4 3/9] clk: imx: add pllv4 support

pllv4 is designed for System Clock Generation (SCG) module observed in IMX ULP SoC series. e.g. i.MX7ULP. The SCG modules generates clock used to derive processor, system, peripheral bus and external memory interface clocks while this patch intends to support the PLL part. Cc: Stephen Boyd Cc:

[PATCH RESEND V4 2/9] clk: fractional-divider: add CLK_FRAC_DIVIDER_ZERO_BASED flag support

Adding CLK_FRAC_DIVIDER_ZERO_BASED flag to indicate the numerator and denominator value in register are start from 0. This can be used to support frac dividers like below: Divider output clock = Divider input clock x [(frac +1) / (div +1)] where frac/div in register is: 000b - Divide by 1. 001b -

[PATCH RESEND V4 6/9] dt-bindings: clock: add imx7ulp clock binding doc

i.MX7ULP Clock functions are under joint control of the System Clock Generation (SCG) modules, Peripheral Clock Control (PCC) modules, and Core Mode Controller (CMC)1 blocks Note IMX7ULP has two clock domains: M4 and A7. This binding doc is only for A7 clock domain. Cc: Rob Herring Cc: Mark

[PATCH RESEND V4 5/9] clk: imx: add composite clk support

The imx composite clk is designed for Peripheral Clock Control (PCC) module observed in IMX ULP SoC series. e.g. i.MX7ULP. NOTE pcc can only be operated when clk is gated. Cc: Stephen Boyd Cc: Michael Turquette Cc: Shawn Guo Cc: Anson Huang Cc: Bai Ping Signed-off-by: Dong Aisheng ---

[PATCH RESEND V4 4/9] clk: imx: add pfdv2 support

The pfdv2 is designed for PLL Fractional Divide (PFD) observed in System Clock Generation (SCG) module in IMX ULP SoC series. e.g. i.MX7ULP. NOTE pfdv2 can only be operated when clk is gated. Cc: Stephen Boyd Cc: Michael Turquette Cc: Shawn Guo Cc: Anson Huang Cc: Bai Ping Signed-off-by:

[PATCH RESEND V4 7/9] clk: imx: make mux parent strings const

As the commit 2893c379461a ("clk: make strings in parent name arrays const"), let's make the parent strings const, otherwise we may meet the following warning when compiling: drivers/clk/imx/clk-imx7ulp.c: In function 'imx7ulp_clocks_init': drivers/clk/imx/clk-imx7ulp.c:73:35: warning: passing

[PATCH RESEND V4 4/9] clk: imx: add pfdv2 support

The pfdv2 is designed for PLL Fractional Divide (PFD) observed in System Clock Generation (SCG) module in IMX ULP SoC series. e.g. i.MX7ULP. NOTE pfdv2 can only be operated when clk is gated. Cc: Stephen Boyd Cc: Michael Turquette Cc: Shawn Guo Cc: Anson Huang Cc: Bai Ping Signed-off-by:

[PATCH RESEND V4 7/9] clk: imx: make mux parent strings const

As the commit 2893c379461a ("clk: make strings in parent name arrays const"), let's make the parent strings const, otherwise we may meet the following warning when compiling: drivers/clk/imx/clk-imx7ulp.c: In function 'imx7ulp_clocks_init': drivers/clk/imx/clk-imx7ulp.c:73:35: warning: passing

[PATCH RESEND V4 5/9] clk: imx: add composite clk support

The imx composite clk is designed for Peripheral Clock Control (PCC) module observed in IMX ULP SoC series. e.g. i.MX7ULP. NOTE pcc can only be operated when clk is gated. Cc: Stephen Boyd Cc: Michael Turquette Cc: Shawn Guo Cc: Anson Huang Cc: Bai Ping Signed-off-by: Dong Aisheng ---

[PATCH RESEND V4 0/9] clk: add imx7ulp clk support

This is a rebased version of below patch series against latest clk tree. [PATCH RESEND V3 0/9] clk: add imx7ulp clk support https://lkml.org/lkml/2018/3/16/310 It only updates the license to SPDX format as well as a minor fix of pllv4. This patch series intends to add imx7ulp clk support.

[PATCH RESEND V4 1/9] clk: clk-divider: add CLK_DIVIDER_ZERO_GATE clk support

For dividers with zero indicating clock is disabled, instead of giving a warning each time like "clkx: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set" in exist code, we'd like to introduce enable/disable function for it. e.g. 000b - Clock disabled 001b - Divide by 1 010b - Divide by 2 ... Set

[PATCH RESEND V4 9/9] clk: imx: add imx7ulp clk driver

i.MX7ULP Clock functions are under joint control of the System Clock Generation (SCG) modules, Peripheral Clock Control (PCC) modules, and Core Mode Controller (CMC)1 blocks The clocking scheme provides clear separation between M4 domain and A7 domain. Except for a few clock sources shared

[PATCH RESEND V4 8/9] clk: imx: implement new clk_hw based APIs

Clock providers are recommended to use the new struct clk_hw based API, so implement IMX clk_hw based provider helpers functions to the new approach. Signed-off-by: Dong Aisheng --- ChangeLog: v2->v4: * no changes v1->v2: new patches --- drivers/clk/imx/clk.c | 22 ++

[PATCH RESEND V4 0/9] clk: add imx7ulp clk support

This is a rebased version of below patch series against latest clk tree. [PATCH RESEND V3 0/9] clk: add imx7ulp clk support https://lkml.org/lkml/2018/3/16/310 It only updates the license to SPDX format as well as a minor fix of pllv4. This patch series intends to add imx7ulp clk support.

[PATCH RESEND V4 1/9] clk: clk-divider: add CLK_DIVIDER_ZERO_GATE clk support

For dividers with zero indicating clock is disabled, instead of giving a warning each time like "clkx: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set" in exist code, we'd like to introduce enable/disable function for it. e.g. 000b - Clock disabled 001b - Divide by 1 010b - Divide by 2 ... Set

[PATCH RESEND V4 9/9] clk: imx: add imx7ulp clk driver

i.MX7ULP Clock functions are under joint control of the System Clock Generation (SCG) modules, Peripheral Clock Control (PCC) modules, and Core Mode Controller (CMC)1 blocks The clocking scheme provides clear separation between M4 domain and A7 domain. Except for a few clock sources shared

[PATCH RESEND V4 8/9] clk: imx: implement new clk_hw based APIs

Clock providers are recommended to use the new struct clk_hw based API, so implement IMX clk_hw based provider helpers functions to the new approach. Signed-off-by: Dong Aisheng --- ChangeLog: v2->v4: * no changes v1->v2: new patches --- drivers/clk/imx/clk.c | 22 ++

RE: [PATCH v2 0/4] Port mxs-dcp to imx6ull and imx6sll

Hi Leonard, > -Original Message- > From: Leonard Crestez > Sent: Monday, October 15, 2018 9:28 PM [...] > Subject: [PATCH v2 0/4] Port mxs-dcp to imx6ull and imx6sll > > The DCP block is present on 6sll and 6ull but not enabled. The hardware is > mostly compatible with 6sl, the only

RE: [PATCH v2 0/4] Port mxs-dcp to imx6ull and imx6sll

Hi Leonard, > -Original Message- > From: Leonard Crestez > Sent: Monday, October 15, 2018 9:28 PM [...] > Subject: [PATCH v2 0/4] Port mxs-dcp to imx6ull and imx6sll > > The DCP block is present on 6sll and 6ull but not enabled. The hardware is > mostly compatible with 6sl, the only

RE: [PATCH V6 0/4] clk: new APIs to handle all available clocks

Ping > -Original Message- > From: A.s. Dong > Sent: Monday, October 8, 2018 6:43 PM > To: thor.tha...@linux.intel.com; linux-...@vger.kernel.org; sb...@kernel.org > Cc: linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > mturque...@baylibre.com; shawn

RE: [PATCH V6 0/4] clk: new APIs to handle all available clocks

Ping > -Original Message- > From: A.s. Dong > Sent: Monday, October 8, 2018 6:43 PM > To: thor.tha...@linux.intel.com; linux-...@vger.kernel.org; sb...@kernel.org > Cc: linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > mturque...@baylibre.com; shawn

RE: [PATCH V4 0/9] clk: add imx7ulp clk support

Ping > -Original Message- > From: A.s. Dong > Sent: Tuesday, September 25, 2018 5:11 PM > To: sb...@kernel.org; shawn...@kernel.org > Cc: linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > mturque...@baylibre.com; Anson Huang ; Jacky Bai > ; d

RE: [PATCH V4 0/9] clk: add imx7ulp clk support

Ping > -Original Message- > From: A.s. Dong > Sent: Tuesday, September 25, 2018 5:11 PM > To: sb...@kernel.org; shawn...@kernel.org > Cc: linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > mturque...@baylibre.com; Anson Huang ; Jacky Bai > ; d

RE: [PATCH V6 0/4] clk: new APIs to handle all available clocks

Hi Stephen, Gently ping again.. > > > > > Just checking on the status of this patch. The clock routines (patches > > 1-3) are useful for one of my drivers but if they aren't accepted or > > will take a long time to be accepted, I'll need to refactor my driver. > > > > Thanks for this

RE: [PATCH V6 0/4] clk: new APIs to handle all available clocks

Hi Stephen, Gently ping again.. > > > > > Just checking on the status of this patch. The clock routines (patches > > 1-3) are useful for one of my drivers but if they aren't accepted or > > will take a long time to be accepted, I'll need to refactor my driver. > > > > Thanks for this

RE: [PATCH 1/1] MAINTAINERS: imx: include drivers/firmware/imx path

> > diff --git a/MAINTAINERS b/MAINTAINERS index 9ad052a..d1fb824 100644 > > --- a/MAINTAINERS > > +++ b/MAINTAINERS > > @@ -1462,6 +1462,7 @@ F:arch/arm/mach-mxs/ > > F: arch/arm/boot/dts/imx* > > F: arch/arm/configs/imx*_defconfig > > F: drivers/clk/imx/ > > +F: drivers/firmware/imx/ > >

RE: [PATCH 1/1] MAINTAINERS: imx: include drivers/firmware/imx path

> > diff --git a/MAINTAINERS b/MAINTAINERS index 9ad052a..d1fb824 100644 > > --- a/MAINTAINERS > > +++ b/MAINTAINERS > > @@ -1462,6 +1462,7 @@ F:arch/arm/mach-mxs/ > > F: arch/arm/boot/dts/imx* > > F: arch/arm/configs/imx*_defconfig > > F: drivers/clk/imx/ > > +F: drivers/firmware/imx/ > >

RE: [PATCH V4 0/9] clk: add imx7ulp clk support

It's been a few months without comments. Shawn & Stephen, Would you provide some suggestions on how to handle this? Regards Dong Aisheng > -Original Message- > From: A.s. Dong > Sent: Thursday, September 6, 2018 11:25 AM > To: linux-...@vger.kernel.org; sb...@k

RE: [PATCH V4 0/9] clk: add imx7ulp clk support

It's been a few months without comments. Shawn & Stephen, Would you provide some suggestions on how to handle this? Regards Dong Aisheng > -Original Message- > From: A.s. Dong > Sent: Thursday, September 6, 2018 11:25 AM > To: linux-...@vger.kernel.org; sb...@k

RE: [PATCH V6 0/4] clk: new APIs to handle all available clocks

> -Original Message- > From: Thor Thayer [mailto:thor.tha...@linux.intel.com] > Sent: Wednesday, September 19, 2018 10:47 PM > To: A.s. Dong ; linux-...@vger.kernel.org > Cc: linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > sb...@kernel.org; mturq

RE: [PATCH V6 0/4] clk: new APIs to handle all available clocks

> -Original Message- > From: Thor Thayer [mailto:thor.tha...@linux.intel.com] > Sent: Wednesday, September 19, 2018 10:47 PM > To: A.s. Dong ; linux-...@vger.kernel.org > Cc: linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > sb...@kernel.org; mturq

RE: [PATCH V6 0/4] clk: new APIs to handle all available clocks

Ping again > -Original Message- > From: A.s. Dong > Sent: Thursday, September 6, 2018 11:23 AM > To: linux-...@vger.kernel.org > Cc: linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > sb...@kernel.org; mturque...@baylibre.com; shawn...@kern

RE: [PATCH V6 0/4] clk: new APIs to handle all available clocks

Ping again > -Original Message- > From: A.s. Dong > Sent: Thursday, September 6, 2018 11:23 AM > To: linux-...@vger.kernel.org > Cc: linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > sb...@kernel.org; mturque...@baylibre.com; shawn...@kern

RE: [PATCH V4 0/9] clk: add imx7ulp clk support

Hi Stephen, Would you shine some lights on how to proceed? Regards Dong Aisheng > -Original Message- > From: A.s. Dong > Sent: Monday, August 27, 2018 11:46 AM > To: linux-...@vger.kernel.org; sb...@kernel.org; shawn...@kernel.org > Cc: linux-kernel@vger.kernel.org

RE: [PATCH V4 0/9] clk: add imx7ulp clk support

Hi Stephen, Would you shine some lights on how to proceed? Regards Dong Aisheng > -Original Message- > From: A.s. Dong > Sent: Monday, August 27, 2018 11:46 AM > To: linux-...@vger.kernel.org; sb...@kernel.org; shawn...@kernel.org > Cc: linux-kernel@vger.kernel.org

RE: [PATCH V6 0/4] clk: new APIs to handle all available clocks

Gently ping... > -Original Message- > From: A.s. Dong > Sent: Friday, August 31, 2018 12:46 PM > To: linux-...@vger.kernel.org > Cc: linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > sb...@kernel.org; mturque...@baylibre.com; shawn...@kern

RE: [PATCH V6 0/4] clk: new APIs to handle all available clocks

Gently ping... > -Original Message- > From: A.s. Dong > Sent: Friday, August 31, 2018 12:46 PM > To: linux-...@vger.kernel.org > Cc: linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > sb...@kernel.org; mturque...@baylibre.com; shawn...@kern

RE: [PATCH V4 4/4] video: simplefb: switch to use clk_bulk API to simplify clock operations

> -Original Message- > From: Hans de Goede [mailto:hdego...@redhat.com] > Sent: Wednesday, August 29, 2018 9:01 PM [...] > > @@ -252,39 +228,21 @@ static int simplefb_clocks_get(struct simplefb_par > *par, > > static void simplefb_clocks_enable(struct simplefb_par *par, > >

RE: [PATCH V4 4/4] video: simplefb: switch to use clk_bulk API to simplify clock operations

> -Original Message- > From: Hans de Goede [mailto:hdego...@redhat.com] > Sent: Wednesday, August 29, 2018 9:01 PM [...] > > @@ -252,39 +228,21 @@ static int simplefb_clocks_get(struct simplefb_par > *par, > > static void simplefb_clocks_enable(struct simplefb_par *par, > >

RE: [PATCH V3 0/4] clk: new APIs to handle all available clocks

> -Original Message- > From: Stephen Boyd [mailto:sb...@kernel.org] > Sent: Wednesday, August 29, 2018 11:09 AM > To: A.s. Dong > Cc: linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > mturque...@baylibre.com; shawn...@kernel.org; dl-linu

RE: [PATCH V3 0/4] clk: new APIs to handle all available clocks

> -Original Message- > From: Stephen Boyd [mailto:sb...@kernel.org] > Sent: Wednesday, August 29, 2018 11:09 AM > To: A.s. Dong > Cc: linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > mturque...@baylibre.com; shawn...@kernel.org; dl-linu

RE: [PATCH] pinctrl: Convert to using %pOFn instead of device_node.name

> -Original Message- > From: Rob Herring [mailto:r...@kernel.org] > Sent: Tuesday, August 28, 2018 9:53 AM > To: linux-kernel@vger.kernel.org > Cc: Linus Walleij ; A.s. Dong > ; Fabio Estevam ; Shawn > Guo ; Stefan Agner ; Pengutronix > Kernel Team ; Sean W

RE: [PATCH] pinctrl: Convert to using %pOFn instead of device_node.name

> -Original Message- > From: Rob Herring [mailto:r...@kernel.org] > Sent: Tuesday, August 28, 2018 9:53 AM > To: linux-kernel@vger.kernel.org > Cc: Linus Walleij ; A.s. Dong > ; Fabio Estevam ; Shawn > Guo ; Stefan Agner ; Pengutronix > Kernel Team ; Sean W

  1   2   3   >