RE: [PATCH] usb: dwc3: gadget: Correct the logic for finding last SG entry

Hi Felipe, >-Original Message- >From: Felipe Balbi [mailto:ba...@kernel.org] >Sent: Wednesday, June 5, 2019 1:34 PM >To: Anurag Kumar Vulisha ; Greg Kroah-Hartman > >Cc: linux-...@vger.kernel.org; linux-kernel@vger.kernel.org; >v.anuragku...@gmail.com; Anurag Kumar

[PATCH] usb: dwc3: gadget: Correct the logic for finding last SG entry

t;num_mapped_sgs, then this sg is the last sg. In the above example, the dwc3 driver has already queued 3 sgs (upto sg3), so the num_queued_sgs = 3. On preparing the next sg (i.e sg4), check for last sg (num_queued_sgs + 1) == num_mapped_sgs becomes true. So, the driver sets IOC bit for sg4. This p

RE: [PATCH] usb: gadget: configfs: Add lpm_Ux_disable

Hi Claus & Thinh, >-Original Message- >From: Claus H. Stovgaard [mailto:c...@phaseone.com] >Sent: Wednesday, May 08, 2019 2:59 AM >To: Thinh Nguyen ; linux-...@vger.kernel.org >Cc: Felipe Balbi ; Greg Kroah-Hartman >; linux-kernel@vger.kernel.org; Anurag Kumar &

RE: [PATCH v5 2/2] phy: zynqmp: Add phy driver for xilinx zynqmp phy core

Hi Kishon, >-Original Message- >From: Kishon Vijay Abraham I [mailto:kis...@ti.com] >Sent: Monday, January 21, 2019 11:16 AM >To: Anurag Kumar Vulisha ; robh...@kernel.org; Mark >Rutland ; vivek.gau...@codeaurora.org >Cc: Michal Simek ; v.anuragku...@gmail.com; sundeep

RE: [PATCH v5 2/2] phy: zynqmp: Add phy driver for xilinx zynqmp phy core

Hi Kishon, >-Original Message- >From: Kishon Vijay Abraham I [mailto:kis...@ti.com] >Sent: Wednesday, January 16, 2019 1:38 PM >To: Anurag Kumar Vulisha ; robh...@kernel.org; Mark >Rutland ; vivek.gau...@codeaurora.org >Cc: Michal Simek ; v.anuragku...@gmail.com; sundeep

RE: [PATCH v7 01/10] usb: gadget: udc: Add timer support for usb requests

Hi Felipe, Resending... Since I am waiting on your suggestion, thought of giving remainder. Thanks, Anurag Kumar Vulisha >-Original Message- >From: Anurag Kumar Vulisha >Sent: Wednesday, December 12, 2018 8:41 PM >To: 'Alan Stern' ; Felipe Balbi >Cc: Greg K

[PATCH v5 0/2] phy: zynqmp: Add phy driver for xilinx zynqmp phy core

as suggested by "Vivek Gautam" Changes in v2: 1. Fixed the compilation error when compiled phy-zynqmp.c as a module 2. Added CONFIG_PM macro in phy-zynqmp.c driver Anurag Kumar Vulisha (2): phy: zynqmp: Add dt bindings for ZynqMP phy phy: zynqmp: Add phy driver for xilinx z

[PATCH v5 1/2] phy: zynqmp: Add dt bindings for ZynqMP phy

This patch adds the document describing dt bindings for ZynqMP phy. ZynqMP SOC has a High Speed Processing System Gigabit Transceiver which provides PHY capabilties to USB, SATA, PCIE, Display Port and Ehernet SGMII controllers. Reviewed-by: Rob Herring Signed-off-by: Anurag Kumar Vulisha

[PATCH v5 2/2] phy: zynqmp: Add phy driver for xilinx zynqmp phy core

ZynqMP SoC has a Gigabit Transceiver with four lanes. All the high speed peripherals such as USB, SATA, PCIE, Display Port and Ethernet SGMII can rely on any of the four GT lanes for PHY layer. This patch adds driver for that ZynqMP GT core. Signed-off-by: Anurag Kumar Vulisha --- Changes in v5

RE: [PATCH v7 01/10] usb: gadget: udc: Add timer support for usb requests

Hi Felipe, >-Original Message- >From: Alan Stern [mailto:st...@rowland.harvard.edu] >Sent: Friday, December 07, 2018 10:40 PM >To: Felipe Balbi >Cc: Anurag Kumar Vulisha ; Greg Kroah-Hartman >; Shuah Khan ; Johan Hovold >; Jaejoong Kim ; Benjamin >Herrenschmid

RE: [PATCH v7 09/10] usb: dwc3: Check for IOC/LST bit in both event->status and TRB->ctrl fields

Hi Felipe, >-Original Message- >From: Felipe Balbi [mailto:ba...@kernel.org] >Sent: Monday, December 10, 2018 12:24 PM >To: Anurag Kumar Vulisha ; Greg Kroah-Hartman >; Shuah Khan ; Alan Stern >; Johan Hovold ; Jaejoong Kim >; Benjamin Herrenschmidt ; >Rog

RE: [PATCH v7 09/10] usb: dwc3: Check for IOC/LST bit in both event->status and TRB->ctrl fields

HI Felipe, >-Original Message- >From: Felipe Balbi [mailto:ba...@kernel.org] >Sent: Friday, December 07, 2018 11:42 AM >To: Anurag Kumar Vulisha ; Greg Kroah-Hartman >; Shuah Khan ; Alan Stern >; Johan Hovold ; Jaejoong Kim >; Benjamin Herrenschmidt ; >Rog

RE: [PATCH V6 01/10] usb: gadget: udc: Add timer for stream capable endpoints

Hi Felipe, >-Original Message- >From: Felipe Balbi [mailto:ba...@kernel.org] >Sent: Thursday, November 29, 2018 6:22 PM >To: Anurag Kumar Vulisha ; Greg Kroah-Hartman >; Alan Stern ; Johan >Hovold ; Jaejoong Kim ; Benjamin >Herrenschmidt ; Roger Quadros >Cc: l

RE: [PATCH v3 1/2] phy: zynqmp: Add phy driver for xilinx zynqmp phy core

Hi Sundeep, >-Original Message- >From: sundeep subbaraya [mailto:sundeep.l...@gmail.com] >Sent: Thursday, November 01, 2018 10:31 PM >To: Anurag Kumar Vulisha >Cc: kis...@ti.com; Michal Simek ; robh...@kernel.org; Mark >Rutland ; vivek.gau...@codeaurora.org; >v.

RE: [PATCH v4 2/2] phy: zynqmp: Add phy driver for xilinx zynqmp phy core

Hi Kishon, >-Original Message- >From: Kishon Vijay Abraham I [mailto:kis...@ti.com] >Sent: Tuesday, October 09, 2018 1:18 PM >To: Anurag Kumar Vulisha ; robh...@kernel.org; >mark.rutl...@arm.com; Michal Simek ; >vivek.gau...@codeaurora.org >Cc: v.anuragku...@gmail.c

RE: [PATCH v5 0/8] usb: dwc3: Fix broken BULK stream support to dwc3 gadget driver

Hi Felipe, Please let us know if you have any suggestions / comments on this patch series. If you feel this patch series are okay, can we proceed with them? Thanks, Anurag Kumar Vulisha >-Original Message- >From: Anurag Kumar Vulisha [mailto:anurag.kumar.vuli...@xilinx.com]

RE: [PATCH 1/2] phy: zynqmp: Add phy driver for xilinx zynqmp phy core

HI Vivek, >-Original Message- >From: Vivek Gautam [mailto:vivek.gau...@codeaurora.org] >Sent: Tuesday, September 25, 2018 3:44 PM >To: Anurag Kumar Vulisha ; Kishon Vijay Abraham I >; Michal Simek ; robh...@kernel.org; >mark.rutl...@arm.com >Cc: v.anuragku...@gm

RE: [PATCH 1/2] phy: zynqmp: Add phy driver for xilinx zynqmp phy core

HI Kishon, Thanks a lot for spending your time in reviewing this patch. Please find my comments inline >-Original Message- >From: Kishon Vijay Abraham I [mailto:kis...@ti.com] >Sent: Tuesday, September 25, 2018 10:59 AM >To: Anurag Kumar Vulisha ; Michal Simek >; rob

[PATCH v4 2/2] phy: zynqmp: Add phy driver for xilinx zynqmp phy core

ZynqMP SoC has a Gigabit Transceiver with four lanes. All the high speed peripherals such as USB, SATA, PCIE, Display Port and Ethernet SGMII can rely on any of the four GT lanes for PHY layer. This patch adds driver for that ZynqMP GT core. Signed-off-by: Anurag Kumar Vulisha --- Changes in v4

[PATCH v4 1/2] phy: zynqmp: Add dt bindings for ZynqMP phy

This patch adds the document describing dt bindings for ZynqMP phy. ZynqMP SOC has a High Speed Processing System Gigabit Transceiver which provides PHY capabilties to USB, SATA, PCIE, Display Port and Ehernet SGMII controllers. Signed-off-by: Anurag Kumar Vulisha --- Changes in v4: 1

[PATCH v4 0/2] phy: zynqmp: Add phy driver for xilinx zynqmp phy core

d to 1st Changes in v3: 1. Corrected the Documentation as suggested by "Vivek Gautam" Changes in v2: 1. Fixed the compilation error when compiled phy-zynqmp.c as a module 2. Added CONFIG_PM macro in phy-zynqmp.c driver Anurag Kumar Vulisha (2): phy: zynqmp:

RE: [PATCH v3 2/2] phy: zynqmp: Add dt bindings for ZynqMP phy

requencies. For example USB3.0 protocol can operate with 26, 52 & 100 MHZ. Providing any other frequency would make the phy fail to lock the PLL and error would be generated by the driver. As you suggested, I will add more details regarding the frequencies supported by different protocols in the next series of the patch. >> + >> +Example: >> + >> +#include >> + >> +usb@fe20 { >> +... >> +phys = <&lane2 PHY_TYPE_USB3 0 2 260>; >> +... >> +}; >> + >> +ahci@fd0c { >> +... >> +phys = <&lane3 PHY_TYPE_SATA 1 1 12500>; >> +... >> +}; > >What if you are doing multiple lanes for 1 device? That would be more useful >2nd >example if that's supported. > Will add the multi lane example in the next series of the patch. Thanks, Anurag Kumar Vulisha >> -- >> 2.1.1 >>

RE: [PATCH v3 1/2] phy: zynqmp: Add phy driver for xilinx zynqmp phy core

Hi Rob, Thanks a lot for spending your time in reviewing this patch series, >> Signed-off-by: Anurag Kumar Vulisha >> --- >> Changes in v3: >> 1. Corrected the Documentation as suggested by Vivek Gautam >> >> Changes in v2: >> 1. Fix

[PATCH v3 1/2] phy: zynqmp: Add phy driver for xilinx zynqmp phy core

ZynqMP SoC has a Gigabit Transceiver with four lanes. All the high speed peripherals such as USB, SATA, PCIE, Display Port and Ethernet SGMII can rely on any of the four GT lanes for PHY layer. This patch adds driver for that ZynqMP GT core. Signed-off-by: Anurag Kumar Vulisha --- Changes in v3

[PATCH v3 0/2] phy: zynqmp: Add phy driver for xilinx zynqmp phy core

mpiled phy-zynqmp.c as a module 2. Added CONFIG_PM macro in phy-zynqmp.c driver Anurag Kumar Vulisha (2): phy: zynqmp: Add phy driver for xilinx zynqmp phy core phy: zynqmp: Add dt bindings for ZynqMP phy .../devicetree/bindings/phy/phy-zynqmp.txt | 104 ++ drivers/p

[PATCH v3 2/2] phy: zynqmp: Add dt bindings for ZynqMP phy

This patch adds the document describing dt bindings for ZynqMP phy. ZynqMP SOC has a High Speed Processing System Gigabit Transceiver which provides PHY capabilties to USB, SATA, PCIE, Display Port and Ehernet SGMII controllers. Signed-off-by: Anurag Kumar Vulisha --- Changes in v3: 1

RE: [PATCH v2 2/2] phy: zynqmp: Add dt bindings for ZynqMP phy

>> +lane1: >> +- #phy-cells: Should be 4 >> + >> +lane2: >> +- #phy-cells: Should be 4 >> + >> +lane3: >> +- #phy-cells: Should be 4 >> + >> +Example: >> +serdes: zynqmp_phy@fd400000 { > >phy is not just the serdes. Also s/zynqmp_phy/phy > >This could be: >     zynqmp_phy: phy@fd40 > Thanks for correcting, will fix this in next series of this patch Best Regards, Anurag Kumar Vulisha

[PATCH v2 1/2] phy: zynqmp: Add phy driver for xilinx zynqmp phy core

ZynqMP SoC has a Gigabit Transceiver with four lanes. All the high speed peripherals such as USB, SATA, PCIE, Display Port and Ethernet SGMII can rely on any of the four GT lanes for PHY layer. This patch adds driver for that ZynqMP GT core. Signed-off-by: Anurag Kumar Vulisha --- Changes in v2

[PATCH v2 0/2] phy: zynqmp: Add phy driver for xilinx zynqmp phy core

er Anurag Kumar Vulisha (2): phy: zynqmp: Add phy driver for xilinx zynqmp phy core phy: zynqmp: Add dt bindings for ZynqMP phy .../devicetree/bindings/phy/phy-zynqmp.txt | 104 ++ drivers/phy/Kconfig|8 + drivers/ph

[PATCH v2 2/2] phy: zynqmp: Add dt bindings for ZynqMP phy

This patch adds the document describing dt bindings for ZynqMP phy. ZynqMP SOC has a High Speed Processing System Gigabit Transceiver which provides PHY capabilties to USB, SATA, PCIE, Display Port and Ehernet SGMII controllers. Signed-off-by: Anurag Kumar Vulisha --- changes in v2: 1

[PATCH 1/2] phy: zynqmp: Add phy driver for xilinx zynqmp phy core

ZynqMP SoC has a Gigabit Transceiver with four lanes. All the high speed peripherals such as USB, SATA, PCIE, Display Port and Ethernet SGMII can rely on any of the four GT lanes for PHY layer. This patch adds driver for that ZynqMP GT core. Signed-off-by: Anurag Kumar Vulisha --- drivers/phy

[PATCH 0/2] phy: zynqmp: Add phy driver for xilinx zynqmp phy core

Clock Sharing". This driver supports clock sharing aswell. These set of patches add support SIOU support by adding zynqmp-phy driver to linux. Anurag Kumar Vulisha (2): phy: zynqmp: Add phy driver for xilinx zynqmp phy core phy: zynqmp: Add dt bindings for ZynqMP phy .../devicetree/bi

[PATCH 2/2] phy: zynqmp: Add dt bindings for ZynqMP phy

This patch adds the document describing dt bindings for ZynqMP phy. ZynqMP SOC has a High Speed Processing System Gigabit Transceiver which provides PHY capabilties to USB, SATA, PCIE, Display Port and Ehernet SGMII controllers. Signed-off-by: Anurag Kumar Vulisha --- .../devicetree/bindings

[PATCH v3] usb: host: xhci-plat: Iterate over parent nodes for finding quirks

ted. Signed-off-by: Anurag Kumar Vulisha --- Changes in v3: 1. As Mathias suggested, moved the position of reading devicetree property "imod-interval-ns" into for loop Changes in v2: 1. As suggested by Mathias, restoring immod_interval changes to default

RE: [PATCH 4/8] usb: dwc3: implement stream transfer timeout

>-Original Message- >From: Andy Shevchenko [mailto:andy.shevche...@gmail.com] >Sent: Wednesday, July 25, 2018 8:55 PM >To: Anurag Kumar Vulisha >Cc: Felipe Balbi ; Greg Kroah-Hartman >; v.anuragku...@gmail.com; USB u...@vger.kernel.org>; Linux Kernel Mailing List &

RE: [PATCH 4/8] usb: dwc3: implement stream transfer timeout

Hi Andy, Thanks for your review comments, please find my comments inline >-Original Message- >From: Andy Shevchenko [mailto:andy.shevche...@gmail.com] >Sent: Wednesday, July 25, 2018 8:36 PM >To: Anurag Kumar Vulisha >Cc: Felipe Balbi ; Greg Kroah-Hartman >; v.anu

[PATCH 7/8] usb: dwc3: Check for IOC/LST bit in both event->status and TRB->ctrl fields

t;status is checked for IOC/LST bit and returns on the first TRB. This makes the remaining TRBs left unhandled. To aviod this, changed the code to check for IOC/LST bits in both event->status & TRB->ctrl. This patch does the same. Signed-off-by: Anurag Kumar Vulisha --- drivers/usb/dwc3/ga

[PATCH 8/8] usb: dwc3: Check MISSED ISOC bit only for ISOC endpoints

When streaming is enabled on BULK endpoints and LST bit is set observed MISSED ISOC bit set in event->status for BULK ep. Since this bit is only valid for isocronous endpoints, changed the code to check for isocrnous endpoints when MISSED ISOC bit is set. Signed-off-by: Anurag Kumar Vuli

[PATCH 5/8] usb: dwc3: don't issue no-op trb for stream capable endpoints

The stream capable endpoints require stream id to be given when issuing START TRANSFER. While issuing no-op trb the stream id is not yet known, so don't issue no-op trb's on stream capable endpoints. Signed-off-by: Anurag Kumar Vulisha --- drivers/usb/dwc3/gadget.c | 2 +- 1 file

[PATCH 6/8] usb: dwc3: check for requests in started list for stream capable endpoints

__dwc3_gadget_kick_transfer() if any. Signed-off-by: Anurag Kumar Vulisha --- drivers/usb/dwc3/gadget.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c index af8d470..fe1ea245 100644 --- a/drivers/usb/dwc3/gadget.c +++ b/drivers/usb/dwc3

[PATCH 4/8] usb: dwc3: implement stream transfer timeout

, device will first stop transfer and restart the transfer again. This patch does the same. Signed-off-by: Anurag Kumar Vulisha --- drivers/usb/dwc3/core.h | 7 +++ drivers/usb/dwc3/gadget.c | 39 +++ 2 files changed, 46 insertions(+) diff --git a/drivers/usb

[PATCH 1/8] usb: dwc3: Correct the logic for checking TRB full in __dwc3_prepare_one_trb()

() wrongly calculates the present working TRB as free TRB (since HWO bit is not yet set). This patch corrects this issue by setting HWO bit before calling dwc3_calc_trbs_left(). Signed-off-by: Anurag Kumar Vulisha --- drivers/usb/dwc3/gadget.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletion

[PATCH 3/8] usb: dwc3: make controller clear transfer resources after complete

the ctrl field of the last TRB. Signed-off-by: Anurag Kumar Vulisha --- drivers/usb/dwc3/gadget.c | 19 --- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c index efc6e13..b3e9e7f 100644 --- a/drivers/usb/dwc3

[PATCH 0/8] fix broken BULK stream support to dwc3 gadget driver

These patch series fixes the broken BULK streaming support in dwc3 gadget driver. Anurag Kumar Vulisha (8): usb: dwc3: Correct the logic for checking TRB full in __dwc3_prepare_one_trb() usb: dwc3: update stream id in depcmd usb: dwc3: make controller clear transfer resources after

[PATCH 2/8] usb: dwc3: update stream id in depcmd

For stream capable endpoints, stream id related information needs to be updated into DEPCMD while issuing START TRANSFER. This patch does the same. Signed-off-by: Anurag Kumar Vulisha --- drivers/usb/dwc3/gadget.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/usb/dwc3/gadget.c

RE: [PATCH v2 1/2] usb: dwc3: gadget: Correct handling of scattergather lists

Hi All, Please let me know if the changes in this patch are okay . If the changes looks fine , can we proceed with this patch. Thanks, Anurag Kumar Vulisha >-Original Message- >From: v.anuragku...@gmail.com [mailto:v.anuragku...@gmail.com] >Sent: Tuesday, March 27, 2018 4:

RE: [PATCH] usb: dwc3: gadget: Correct the logic for queuing sgs

Hi Felipe, Thanks for providing your inputs on this patch. Will send v2 with all your suggestions added. Thanks, Anurag Kumar Vulisha >-Original Message- >From: Felipe Balbi [mailto:ba...@kernel.org] >Sent: Friday, March 23, 2018 4:59 PM >To: Anurag Kumar Vulisha ; Greg K

RE: [PATCH] usb: dwc3: gadget: Correct the logic for queuing sgs

Hi Felipe, Thanks for reviewing the patch , please find my comments inline >-Original Message- >From: Felipe Balbi [mailto:ba...@kernel.org] >Sent: Monday, March 19, 2018 2:21 PM >To: Anurag Kumar Vulisha ; Greg Kroah-Hartman > >Cc: v.anuragku...@gmail.com; Ajay Y

[PATCH] usb: dwc3: gadget: Correct the logic for queuing sgs

e correctly fetches the req's which were not queued from the started_list but fails to start from the sg where it previously stopped queuing because of the unavailable TRB's. This patch correct's the code to start queuing from the correct sg in sglist. Signed-off-by: Anurag Kumar Vuli

RE: [LINUX PATCH] usb: xhci: Add toggle cycle bit for the last seg trb when cached ring is used

HI Mathias, >-Original Message- >From: Mathias Nyman [mailto:mathias.ny...@linux.intel.com] >Sent: Thursday, June 01, 2017 6:51 PM >To: Anurag Kumar Vulisha ; mathias.ny...@intel.com; >gre...@linuxfoundation.org >Cc: linux-...@vger.kernel.org; linux-kernel@vger.ke

[LINUX PATCH] usb: xhci: Add toggle cycle bit for the last seg trb when cached ring is used

cached ring last segment. When the controller fetches the last link trb with no toggle bit set, abnormal behaviour is generated. This patch solves that problem by adding the TOGGLE bit for the last trb of the last segment of the cached ring. Signed-off-by: Anurag Kumar Vulisha --- drivers/usb/host

[RFC PATCH] drivers: ata: Add [save|restore]_initial_config override functions

functions for saving and restoring controller values from the driver instead of doing it in AHCI stack Signed-off-by: Anurag Kumar Vulisha --- drivers/ata/ahci.c | 5 - drivers/ata/ahci.h | 9 + drivers/ata/libahci.c | 5 - drivers/ata

[RFC PATCH] xhci: Use Cached ring during endpoint ring allocation

urs due to insufficient memory during ring expansion. Signed-off-by: Anurag Kumar Vulisha --- drivers/usb/host/xhci-mem.c | 13 - 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c index 8414ed2..587b6c6 100644 --- a/driver

RE: [PATCH] media: uvcvideo: Add support for changing UVC_URBS/UVC_MAX_PACKETS from sysfs

Ping ! >-Original Message- >From: Anurag Kumar Vulisha [mailto:anurag.kumar.vuli...@xilinx.com] >Sent: Friday, February 03, 2017 10:10 PM >To: Laurent Pinchart ; Mauro Carvalho >Chehab >Cc: Punnaiah Choudary Kalluri ; Anirudha Sarangi >; linux-me...@vger.ke

[PATCH] media: uvcvideo: Add support for changing UVC_URBS/UVC_MAX_PACKETS from sysfs

UVC_MAX_PACKETS also at runtime instead of #define it. This patch adds the solution to change UVC_URBS and UVC_MAX_PACKETS at runtime using sysfs layer before starting the video application. Signed-off-by: Anurag Kumar Vulisha --- drivers/media/usb/uvc/uvc_driver.c | 89

[PATCH] usb: dwc3: of-simple: Fix warning during unbind

(). Signed-off-by: Anurag Kumar Vulisha --- drivers/usb/dwc3/dwc3-of-simple.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/dwc3/dwc3-of-simple.c b/drivers/usb/dwc3/dwc3-of-simple.c index e56d59b..99d8016 100644 --- a/drivers/usb/dwc3/dwc3-of-simple.c +++ b/drivers

[PATCH V4] rtc: zynqmp: Update seconds time programming logic

from CURRENT_TIME. This patch updates the above said. Signed-off-by: Anurag Kumar Vulisha --- Changes in v4: 1. Corrected the read time logic Changes in v2: 1. Updated the Time programming logic as suggested by Alexandre Belloni 2. Changed the commit message --- drivers/rtc/rtc

RE: [PATCH V3] rtc: zynqmp: Update seconds time programming logic

Hi all, Made a small typo mistake , Please ignore this patch. Sorry for the inconvenience caused. Thanks, Anurag Kumar V > -Original Message- > From: Anurag Kumar Vulisha [mailto:anurag.kumar.vuli...@xilinx.com] > Sent: Wednesday, April 20, 2016 8:29 PM > To: Ales

[PATCH V3] rtc: zynqmp: Update seconds time programming logic

from CURRENT_TIME. This patch updates the above said. Signed-off-by: Anurag Kumar Vulisha --- Changes in v3: 1. Corrected the read time logic Changes in v2: 1. Updated the Time programming logic as suggested by Alexandre Belloni 2. Changed the commit message --- drivers/rtc

RE: [PATCH V2] rtc: zynqmp: Update seconds time programming logic

Hi Alexandre, > -Original Message- > From: Alexandre Belloni [mailto:alexandre.bell...@free-electrons.com] > Sent: Wednesday, April 20, 2016 7:33 PM > To: Anurag Kumar Vulisha > Cc: Alessandro Zummo ; Soren Brinkmann > ; Michal Simek ; rtc- > li...@googlegrou

RE: [PATCH 3/3] RTC: Update seconds time programming logic

Hi Alexandre, Thanks for reviewing the patch, I will sent v2 with the changes updated. Thanks, Anurag Kumar V > -Original Message- > From: Alexandre Belloni [mailto:alexandre.bell...@free-electrons.com] > Sent: Wednesday, April 20, 2016 5:32 PM > To: Anurag Kumar V

[PATCH V2] rtc: zynqmp: Update seconds time programming logic

from CURRENT_TIME. This patch updates the above said. Signed-off-by: Anurag Kumar Vulisha --- Changes in v2: 1. Updated the Time programming logic as suggested by Alexandre Belloni 2. Changed the commit message --- drivers/rtc/rtc-zynqmp.c | 41

RE: [PATCH 3/3] RTC: Update seconds time programming logic

Hi Alexandre, > -Original Message- > From: Alexandre Belloni [mailto:alexandre.bell...@free-electrons.com] > Sent: Wednesday, April 20, 2016 1:28 PM > To: Anurag Kumar Vulisha > Cc: Alessandro Zummo ; Soren Brinkmann > ; Michal Simek ; rtc- > li...@googlegrou

RE: [PATCH 3/3] RTC: Update seconds time programming logic

Hi Alexandre, > -Original Message- > From: Alexandre Belloni [mailto:alexandre.bell...@free-electrons.com] > Sent: Wednesday, April 20, 2016 4:01 AM > To: Anurag Kumar Vulisha > Cc: Alessandro Zummo ; Soren Brinkmann > ; Michal Simek ; rtc- > li...@googlegrou

[PATCH 1/3] RTC: Enable RTC switching to battery power when VCC_PSAUX is N/A

logic within the battery-powered domain from functioning incorrectly. This patch enables that feature. Signed-off-by: Anurag Kumar Vulisha --- drivers/rtc/rtc-zynqmp.c | 8 1 file changed, 8 insertions(+) diff --git a/drivers/rtc/rtc-zynqmp.c b/drivers/rtc/rtc-zynqmp.c index 8b28762

[PATCH 3/3] RTC: Update seconds time programming logic

from CURRENT_TIME. This patch updates the above said. Signed-off-by: Anurag Kumar Vulisha --- drivers/rtc/rtc-zynqmp.c | 40 ++-- 1 file changed, 38 insertions(+), 2 deletions(-) diff --git a/drivers/rtc/rtc-zynqmp.c b/drivers/rtc/rtc-zynqmp.c index f87f971

[PATCH 2/3] RTC: Write Calibration value before set time

It is suggested to programe CALIB_WRITE register with the calibration value before updating the SET_TIME_WRITE register, doing so will clear the Tick Counter and force the next second to be signaled exactly in 1 second. This patch updates the same. Signed-off-by: Anurag Kumar Vulisha

RE: [RFC PATCH] drivers: ata: Read Rx water mark value from device-tree

+ Michal > -Original Message- > From: Anurag Kumar Vulisha > Sent: Friday, February 26, 2016 7:18 PM > To: 'Rob Herring' > Cc: Arnd Bergmann; pawel.m...@arm.com; mark.rutl...@arm.com; > ijc+devicet...@hellion.org.uk; ga...@codeaurora.org; t...@kernel.org;

RE: [RFC PATCH] drivers: ata: Read Rx water mark value from device-tree

Hi Rob, > -Original Message- > From: Rob Herring [mailto:r...@kernel.org] > Sent: Wednesday, February 24, 2016 1:00 AM > To: Anurag Kumar Vulisha > Cc: Arnd Bergmann; pawel.m...@arm.com; mark.rutl...@arm.com; > ijc+devicet...@hellion.org.uk; ga...@codeaurora.or

RE: [RFC PATCH] drivers: ata: Read Rx water mark value from device-tree

Hi Arnd, > -Original Message- > From: Arnd Bergmann [mailto:a...@arndb.de] > Sent: Tuesday, February 23, 2016 3:51 PM > To: Anurag Kumar Vulisha > Cc: robh...@kernel.org; pawel.m...@arm.com; mark.rutl...@arm.com; > ijc+devicet...@hellion.org.uk; ga...@codeaurora.or

RE: [RFC PATCH] drivers: ata: Read Rx water mark value from device-tree

Hi Arnd, > -Original Message- > From: Arnd Bergmann [mailto:a...@arndb.de] > Sent: Monday, February 22, 2016 8:50 PM > To: Anurag Kumar Vulisha > Cc: robh...@kernel.org; pawel.m...@arm.com; mark.rutl...@arm.com; > ijc+devicet...@hellion.org.uk; ga...@codeaurora.or

RE: [RFC PATCH] drivers: ata: Read Rx water mark value from device-tree

Hi Arnd, > -Original Message- > From: Arnd Bergmann [mailto:a...@arndb.de] > Sent: Sunday, February 21, 2016 4:05 AM > To: Anurag Kumar Vulisha > Cc: robh...@kernel.org; pawel.m...@arm.com; mark.rutl...@arm.com; > ijc+devicet...@hellion.org.uk; ga...@codeaurora.or

[RFC PATCH] drivers: ata: Read Rx water mark value from device-tree

controller will transmit HOLDS to the device asking it to wait. Signed-off-by: Anurag Kumar Vulisha --- .../devicetree/bindings/ata/ahci-ceva.txt |2 ++ drivers/ata/ahci_ceva.c| 10 +- 2 files changed, 11 insertions(+), 1 deletions(-) diff --git

RE: [PATCH] drivers: ata: Move vendor specific sata port phy oob settings to device-tree

Hi Rob, Do you have any further comments on this or shall we proceed with this patch . Thanks, Anurag Kumar V > -Original Message- > From: Anurag Kumar Vulisha > Sent: Tuesday, November 17, 2015 7:54 PM > To: 'Rob Herring' > Cc: pawel.m...@arm.com; ma

RE: [PATCH] drivers: ata: Move vendor specific sata port phy oob settings to device-tree

Hi Rob, Thanks for reviewing the patch > -Original Message- > From: Rob Herring [mailto:r...@kernel.org] > Sent: Friday, November 13, 2015 8:02 PM > To: Anurag Kumar Vulisha > Cc: pawel.m...@arm.com; mark.rutl...@arm.com; > ijc+devicet...@hellion.org.uk; ga...

[PATCH] mtd: spi-nor: Add Global Block-Protection Unlock support for SST flash parts

This patch adds Global block protection unlock support for SST flash parts Signed-off-by: Anurag Kumar Vulisha --- drivers/mtd/spi-nor/spi-nor.c | 8 include/linux/mtd/spi-nor.h | 1 + 2 files changed, 9 insertions(+) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor

[PATCH] drivers: ata: Move vendor specific sata port phy oob settings to device-tree

and zc1751 has different clock frequencies). Since to make ahci_ceva driver generic, it would be better to move these settings to the device-tree node and read them from driver. This patch does the same. Signed-off-by: Anurag Kumar Vulisha --- .../devicetree/bindings/ata/ahci-ceva.txt

RE: [PATCH v2] dmaengine: vdma: Add 64 bit addressing support to the driver

Hi Vinod, Thanks for reviewing the patch > -Original Message- > From: Vinod Koul [mailto:vinod.k...@intel.com] > Sent: Monday, September 21, 2015 9:27 PM > To: Anurag Kumar Vulisha > Cc: Rob Herring; Pawel Moll; Mark Rutland; Ian Campbell; Kumar Gala; Michal > Simek; So

[PATCH v2] dmaengine: vdma: Add 64 bit addressing support to the driver

address.So we need to program two registers at a time. This patch adds the 64 bit addressing support to the vdma driver. Signed-off-by: Anurag Kumar Vulisha --- Changes in v2: 1. Added dma-ranges property in device tree as suggested by Arnd Bergmann. 2. Added device tree property(xlnx

RE: [PATCH] dmaengine: vdma: Add 64 bit addressing support to the driver

Hi Laurent, > -Original Message- > From: Anurag Kumar Vulisha > Sent: Thursday, August 20, 2015 2:41 PM > To: Anurag Kumar Vulisha > Subject: RE:[PATCH] dmaengine: vdma: Add 64 bit addressing support to the > driver > > > Hi Anurag, > > Thank you fo

RE: [PATCH] dmaengine: vdma: Add 64 bit addressing support to the driver

Ping? > -Original Message- > From: Anurag Kumar Vulisha [mailto:anurag.kumar.vuli...@xilinx.com] > Sent: Wednesday, August 05, 2015 5:18 PM > To: dan.j.willi...@intel.com; vinod.k...@intel.com; Michal Simek; Soren > Brinkmann; srikanth.thok...@xilinx.com; max

[PATCH] dmaengine: vdma: Add 64 bit addressing support to the driver

This patch adds the 64 bit addressing support to the vdma driver. Signed-off-by: Anurag Kumar Vulisha --- drivers/dma/Kconfig |2 +- drivers/dma/xilinx/xilinx_vdma.c | 36 ++-- 2 files changed, 31 insertions(+), 7 deletions(-) diff --git a

[PATCH v2] i2c: removed work arounds in i2c driver for Zynq Ultrascale+ MPSoC

Cadence 1.0 version has bugs which have been fixed in the cadence 1.4 version. This patch removes the quirks present in the driver for cadence 1.4 version. Signed-off-by: Anurag Kumar Vulisha --- Changes in v2: 1.Changed the commit message. 2.Changed the compatible string

RE: [PATCH] i2c: removed work arounds in i2c driver for Zynq Ultrascale+ MPSoC

Hi, Thanks for reviewing the code. I will make the changes as said and send the patch as v2. Thanks, Anurag Kumar V > -Original Message- > From: Wolfram Sang [mailto:w...@the-dreams.de] > Sent: Friday, July 10, 2015 1:39 AM > To: Anurag Kumar Vulisha > Cc: rob

[PATCH] i2c: removed work arounds in i2c driver for Zynq Ultrascale+ MPSoC

Removed the workarounds present in the cadence i2c driver for Zynq Ultrascale+ MPSoC Signed-off-by: Anurag Kumar Vulisha --- .../devicetree/bindings/i2c/i2c-cadence.txt|2 +- drivers/i2c/busses/i2c-cadence.c | 67 --- 2 files changed, 57

[RFC PATCH] mtd: spi-nor: Added flag check for quad io protocol for micron flash parts

cked before enabling the quad io protocol. Signed-off-by: Anurag Kumar Vulisha --- drivers/mtd/spi-nor/spi-nor.c |3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 14a5d23..a6fa8dc 100644 --- a/drivers/mtd/spi

[PATCH v2] gpio: Added GPIO support to Zynq Ultrascale+ MPSoC

Added support to Zynq Ultrascale+ MPSoC on the existing zynq gpio driver. Signed-off-by: Anurag Kumar Vulisha --- Chnages in v2: 1.Added device tree bingings for Zynq Ultrascale+ MPSoC 2.Changed the commit message and subject from ZynqMP to Zynq Ultrascale+ MPSoC

RE: [patch] gpio: Added GPIO support to ZynqMP SoC

Hi Linus, > -Original Message- > From: Linus Walleij [mailto:linus.wall...@linaro.org] > Sent: Thursday, June 04, 2015 1:38 PM > To: Anurag Kumar Vulisha > Cc: Alexandre Courbot; Michal Simek; Soren Brinkmann; linux- > g...@vger.kernel.org; linux-kernel@vger.kernel.org

[patch] gpio: Added GPIO support to ZynqMP SoC

Added support to ZynqMP SoC on the existing zynq gpio driver. Signed-off-by: Anurag Kumar Vulisha --- drivers/gpio/Kconfig |2 +- drivers/gpio/gpio-zynq.c | 191 ++ 2 files changed, 126 insertions(+), 67 deletions(-) diff --git a/drivers