On 07/19/2017 05:18 PM, Abhishek Sahu wrote:
The BAM transaction is the core data structure which will be used
for all the data transfers in QPIC NAND. Since the base layer is
serializing all the NAND requests so allocating BAM transaction
before every transfer will be overhead. The memory for
On 07/19/2017 05:18 PM, Abhishek Sahu wrote:
The BAM transaction is the core data structure which will be used
for all the data transfers in QPIC NAND. Since the base layer is
serializing all the NAND requests so allocating BAM transaction
before every transfer will be overhead. The memory for
Hi,
On 07/19/2017 05:18 PM, Abhishek Sahu wrote:
The EBI2 NAND directly remaps register read buffer with
dma_map_sg. The QPIC NAND will give register read buffer in its
command descriptor and the command descriptor will be mapped with
dma_map_sg instead of register read buffer. This command
Hi,
On 07/19/2017 05:18 PM, Abhishek Sahu wrote:
The EBI2 NAND directly remaps register read buffer with
dma_map_sg. The QPIC NAND will give register read buffer in its
command descriptor and the command descriptor will be mapped with
dma_map_sg instead of register read buffer. This command
ed int data_crci;
+ };
+ };
Could you put comments here explaining one is for EBI2/ADM
and other is for QPIC/BAM? It'll improve the readability a
bit. Otherwise:
Reviewed-by: Archit Taneja <arch...@codeaurora.org>
Thanks,
Archit
+
struct list_head desc_li
;
+ };
+ };
Could you put comments here explaining one is for EBI2/ADM
and other is for QPIC/BAM? It'll improve the readability a
bit. Otherwise:
Reviewed-by: Archit Taneja
Thanks,
Archit
+
struct list_head desc_list;
u8 *data_buffer;
@@ -1985,10 +1995,31 @@ static int
support QPIC NAND also by adding the
BAM DMA support. This patch adds the QPIC NAND support in current
NAND driver with compatible string "qcom,qpic-nandc-v1.4.0" and
maps it with different configuration parameter in driver data.
Reviewed-by: Archit Taneja <arch...@codeaurora.org&
support QPIC NAND also by adding the
BAM DMA support. This patch adds the QPIC NAND support in current
NAND driver with compatible string "qcom,qpic-nandc-v1.4.0" and
maps it with different configuration parameter in driver data.
Reviewed-by: Archit Taneja
Signed-off-by: Abh
properties specific to NAND controller.
Reviewed-by: Archit Taneja <arch...@codeaurora.org>
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
drivers/mtd/nand/qcom_nandc.c | 23 +--
1 file changed, 17 insertions(+), 6 deletions(-)
diff --git a/driv
properties specific to NAND controller.
Reviewed-by: Archit Taneja
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/qcom_nandc.c | 23 +--
1 file changed, 17 insertions(+), 6 deletions(-)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index
On 07/19/2017 05:17 PM, Abhishek Sahu wrote:
This is reorganization of exiting code and will not change any
functionality. The NAND controller supports multiple NAND device
with different page size. The subsequent patch allocate memory
which depends upon the maximum number of codewords so this
On 07/19/2017 05:17 PM, Abhishek Sahu wrote:
This is reorganization of exiting code and will not change any
functionality. The NAND controller supports multiple NAND device
with different page size. The subsequent patch allocate memory
which depends upon the maximum number of codewords so this
On 07/19/2017 05:17 PM, Abhishek Sahu wrote:
The memset in clear_read_regs is overhead. All the register data
will be filled by DMA during NAND operation so making these
register variables zero is not required.
Yeah, that's a good point.
Reviewed-by: Archit Taneja <arch...@codeaurora.
On 07/19/2017 05:17 PM, Abhishek Sahu wrote:
The memset in clear_read_regs is overhead. All the register data
will be filled by DMA during NAND operation so making these
register variables zero is not required.
Yeah, that's a good point.
Reviewed-by: Archit Taneja
Signed-off
functions to
configure page specific register once and per codeword specific
registers for each NAND ECC step.
Thanks for fixing this. I'm assuming this has been tested on IPQ806x
too.
Reviewed-by: Archit Taneja <arch...@codeaurora.org>
Signed-off-by: Abhishek Sahu <abs...@codea
functions to
configure page specific register once and per codeword specific
registers for each NAND ECC step.
Thanks for fixing this. I'm assuming this has been tested on IPQ806x
too.
Reviewed-by: Archit Taneja
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/qcom_nandc.c | 32
to
configure page specific register once and per codeword specific
registers for each NAND ECC step.
Looks good to me.
Reviewed-by: Archit Taneja <arch...@codeaurora.org>
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
drivers/mtd/nand/qcom_
to
configure page specific register once and per codeword specific
registers for each NAND ECC step.
Looks good to me.
Reviewed-by: Archit Taneja
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/qcom_nandc.c | 37 +++--
1 file changed, 27 insertions(+), 10
so this
patch removes the use of “qcom,nandcs” for specifying NAND device
sub nodes.
Since there is no user for this driver currently in so
changing compatible string is safe.
Reviewed-by: Archit Taneja <arch...@codeaurora.org>
Signed-off-by: Abhishek Sahu <abs...@codea
so this
patch removes the use of “qcom,nandcs” for specifying NAND device
sub nodes.
Since there is no user for this driver currently in so
changing compatible string is safe.
Reviewed-by: Archit Taneja
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/qcom_nandc.c | 26
On 07/19/2017 05:17 PM, Abhishek Sahu wrote:
The current driver is failing without complete bootchain since
NAND_DEV_CMD_VLD value is not valid.
Reviewed-by: Archit Taneja <arch...@codeaurora.org>
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
drivers/mtd/nand/qcom
On 07/19/2017 05:17 PM, Abhishek Sahu wrote:
The current driver is failing without complete bootchain since
NAND_DEV_CMD_VLD value is not valid.
Reviewed-by: Archit Taneja
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/qcom_nandc.c | 4
1 file changed, 4 insertions(+)
diff
ing assined to BCH_DISABLED.
s/assined/assigned
Thanks for fixing this up.
Reviewed-by: Archit Taneja <arch...@codeaurora.org>
Fixes: c76b78d8ec05a ("mtd: nand: Qualcomm NAND controller driver")
Cc: sta...@vger.kernel.org
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org&g
ing assined to BCH_DISABLED.
s/assined/assigned
Thanks for fixing this up.
Reviewed-by: Archit Taneja
Fixes: c76b78d8ec05a ("mtd: nand: Qualcomm NAND controller driver")
Cc: sta...@vger.kernel.org
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/qcom_nandc.c | 4 ++--
1 fi
On 07/19/2017 01:43 AM, Eric Anholt wrote:
Archit Taneja <arch...@codeaurora.org> writes:
On 07/15/2017 04:28 AM, Eric Anholt wrote:
Archit Taneja <arch...@codeaurora.org> writes:
On 06/28/2017 01:28 AM, Eric Anholt wrote:
When a mipi_dsi_host is registered, the DT is walked
On 07/19/2017 01:43 AM, Eric Anholt wrote:
Archit Taneja writes:
On 07/15/2017 04:28 AM, Eric Anholt wrote:
Archit Taneja writes:
On 06/28/2017 01:28 AM, Eric Anholt wrote:
When a mipi_dsi_host is registered, the DT is walked to find any child
nodes with compatible strings. Those get
On 07/15/2017 04:31 AM, Eric Anholt wrote:
Archit Taneja <arch...@codeaurora.org> writes:
On 06/29/2017 04:09 PM, Andrzej Hajda wrote:
On 29.06.2017 07:03, Archit Taneja wrote:
On 06/28/2017 01:28 AM, Eric Anholt wrote:
When a mipi_dsi_host is registered, the DT is walked to fi
On 07/15/2017 04:31 AM, Eric Anholt wrote:
Archit Taneja writes:
On 06/29/2017 04:09 PM, Andrzej Hajda wrote:
On 29.06.2017 07:03, Archit Taneja wrote:
On 06/28/2017 01:28 AM, Eric Anholt wrote:
When a mipi_dsi_host is registered, the DT is walked to find any child
nodes with compatible
On 07/15/2017 04:28 AM, Eric Anholt wrote:
Archit Taneja <arch...@codeaurora.org> writes:
On 06/28/2017 01:28 AM, Eric Anholt wrote:
When a mipi_dsi_host is registered, the DT is walked to find any child
nodes with compatible strings. Those get registered as DSI devices,
and most DSI
On 07/15/2017 04:28 AM, Eric Anholt wrote:
Archit Taneja writes:
On 06/28/2017 01:28 AM, Eric Anholt wrote:
When a mipi_dsi_host is registered, the DT is walked to find any child
nodes with compatible strings. Those get registered as DSI devices,
and most DSI panel drivers
is and that some clocks are just branches of
it, we can do better and return that rate instead of a bogus one.
+Hans.
Thanks for the fix.
Reviewed-by: Archit Taneja <arch...@codeaurora.org>
Reported-by: Archit Taneja <arch...@codeaurora.org>
Signed-off-by: Georgi Djakov <georgi.dj
is and that some clocks are just branches of
it, we can do better and return that rate instead of a bogus one.
+Hans.
Thanks for the fix.
Reviewed-by: Archit Taneja
Reported-by: Archit Taneja
Signed-off-by: Georgi Djakov
---
drivers/clk/qcom/clk-smd-rpm.c | 4 ++--
1 file changed, 2
On 06/29/2017 12:46 PM, Abhishek Sahu wrote:
The current QCOM NAND driver only supports version 1.4.0
QCOM QPIC NAND controller. This patch adds the support for
version 1.5.0 which contains some of the registers at
different offsets. The driver data contains the register offset
field which is
On 06/29/2017 12:46 PM, Abhishek Sahu wrote:
The current QCOM NAND driver only supports version 1.4.0
QCOM QPIC NAND controller. This patch adds the support for
version 1.5.0 which contains some of the registers at
different offsets. The driver data contains the register offset
field which is
On 06/29/2017 12:46 PM, Abhishek Sahu wrote:
The current driver defines the register offset with preprocessor
macro which is defined crossponding to NAND controller version
1.4.0. This patch changes these macro with enumeration. It also
adds mapping array which contains controller register
On 06/29/2017 12:46 PM, Abhishek Sahu wrote:
The current driver defines the register offset with preprocessor
macro which is defined crossponding to NAND controller version
1.4.0. This patch changes these macro with enumeration. It also
adds mapping array which contains controller register
On 06/29/2017 12:46 PM, Abhishek Sahu wrote:
1. Add the function for command descriptor preparation which
will be used only by BAM DMA and it will form the DMA descriptors
containing command elements.
2. Add the data descriptor preparation function which will be used
only by BAM
On 06/29/2017 12:46 PM, Abhishek Sahu wrote:
1. Add the function for command descriptor preparation which
will be used only by BAM DMA and it will form the DMA descriptors
containing command elements.
2. Add the data descriptor preparation function which will be used
only by BAM
On 06/29/2017 12:46 PM, Abhishek Sahu wrote:
1. The BAM mode requires few registers configuration before each
NAND page read and codeword read which is different from ADM
so add the helper functions which will be called in BAM mode
only.
2. The NAND page read handling of BAM is
On 06/29/2017 12:46 PM, Abhishek Sahu wrote:
1. The BAM mode requires few registers configuration before each
NAND page read and codeword read which is different from ADM
so add the helper functions which will be called in BAM mode
only.
2. The NAND page read handling of BAM is
On 06/29/2017 12:46 PM, Abhishek Sahu wrote:
1. NAND_READ_LOCATION: provides the offset in page for
reading in BAM DMA mode
2. NAND_ERASED_CW_DETECT_CFG: contains the status for erased
code words
3. NAND_BUFFER_STATUS: contains the status for ECC
Signed-off-by: Abhishek Sahu
On 06/29/2017 12:46 PM, Abhishek Sahu wrote:
1. NAND_READ_LOCATION: provides the offset in page for
reading in BAM DMA mode
2. NAND_ERASED_CW_DETECT_CFG: contains the status for erased
code words
3. NAND_BUFFER_STATUS: contains the status for ECC
Signed-off-by: Abhishek Sahu
---
On 06/29/2017 12:45 PM, Abhishek Sahu wrote:
The BAM has multiple flags to control the transfer. This patch
adds flags parameter in register and data transfer functions and
modifies all these function call with appropriate flags.
Signed-off-by: Abhishek Sahu
---
On 06/29/2017 12:45 PM, Abhishek Sahu wrote:
The BAM has multiple flags to control the transfer. This patch
adds flags parameter in register and data transfer functions and
modifies all these function call with appropriate flags.
Signed-off-by: Abhishek Sahu
---
On 06/29/2017 12:45 PM, Abhishek Sahu wrote:
1. prepare_bam_async_desc is the function which will call
all the DMA API’s. It will fetch the outstanding scatter gather
list for passed channel and will do the DMA descriptor formation.
The DMA flag is dependent upon the type of
On 06/29/2017 12:45 PM, Abhishek Sahu wrote:
1. prepare_bam_async_desc is the function which will call
all the DMA API’s. It will fetch the outstanding scatter gather
list for passed channel and will do the DMA descriptor formation.
The DMA flag is dependent upon the type of
On 06/29/2017 04:09 PM, Andrzej Hajda wrote:
On 29.06.2017 07:03, Archit Taneja wrote:
On 06/28/2017 01:28 AM, Eric Anholt wrote:
When a mipi_dsi_host is registered, the DT is walked to find any child
nodes with compatible strings. Those get registered as DSI devices,
and most DSI panel
On 06/29/2017 04:09 PM, Andrzej Hajda wrote:
On 29.06.2017 07:03, Archit Taneja wrote:
On 06/28/2017 01:28 AM, Eric Anholt wrote:
When a mipi_dsi_host is registered, the DT is walked to find any child
nodes with compatible strings. Those get registered as DSI devices,
and most DSI panel
On 06/29/2017 12:45 PM, Abhishek Sahu wrote:
1. The QPIC NAND uses 3 BAM channels: command, data tx and
data rx while EBI2 NAND uses only single ADM channel.
2. The EBI2 NAND uses normal register read buffer since this
buffer will be remapped with dma_map_sg. The QPIC NAND will give
On 06/29/2017 12:45 PM, Abhishek Sahu wrote:
1. The QPIC NAND uses 3 BAM channels: command, data tx and
data rx while EBI2 NAND uses only single ADM channel.
2. The EBI2 NAND uses normal register read buffer since this
buffer will be remapped with dma_map_sg. The QPIC NAND will give
On 06/29/2017 12:45 PM, Abhishek Sahu wrote:
The current driver only support EBI2 NAND which uses ADM DMA. The
latest QCOM controller supports QPIC NAND which uses BAM DMA. NAND
registers and programming sequence are same for EBI2 and QPIC
NAND so the same driver can support QPIC NAND also by
On 06/29/2017 12:45 PM, Abhishek Sahu wrote:
The current driver only support EBI2 NAND which uses ADM DMA. The
latest QCOM controller supports QPIC NAND which uses BAM DMA. NAND
registers and programming sequence are same for EBI2 and QPIC
NAND so the same driver can support QPIC NAND also by
On 06/28/2017 01:28 AM, Eric Anholt wrote:
When a mipi_dsi_host is registered, the DT is walked to find any child
nodes with compatible strings. Those get registered as DSI devices,
and most DSI panel drivers are mipi_dsi_drivers that attach to those nodes.
There is one special case
On 06/28/2017 01:28 AM, Eric Anholt wrote:
When a mipi_dsi_host is registered, the DT is walked to find any child
nodes with compatible strings. Those get registered as DSI devices,
and most DSI panel drivers are mipi_dsi_drivers that attach to those nodes.
There is one special case
On 06/24/2017 03:20 AM, Eric Anholt wrote:
Boris Brezillon <boris.brezil...@free-electrons.com> writes:
On Thu, 22 Jun 2017 13:47:43 +0530
Archit Taneja <arch...@codeaurora.org> wrote:
On 06/22/2017 01:20 PM, Benjamin Gaignard wrote:
2017-06-20 19:31 GMT+02:00 Eric Anholt <
On 06/24/2017 03:20 AM, Eric Anholt wrote:
Boris Brezillon writes:
On Thu, 22 Jun 2017 13:47:43 +0530
Archit Taneja wrote:
On 06/22/2017 01:20 PM, Benjamin Gaignard wrote:
2017-06-20 19:31 GMT+02:00 Eric Anholt :
Archit Taneja writes:
On 06/16/2017 08:13 PM, Eric Anholt wrote
zillon wrote:
On Thu, 22 Jun 2017 13:47:43 +0530
Archit Taneja <arch...@codeaurora.org> wrote:
On 06/22/2017 01:20 PM, Benjamin Gaignard wrote:
2017-06-20 19:31 GMT+02:00 Eric Anholt <e...@anholt.net>:
Archit Taneja <arch...@codeaurora.org> writes:
On 06/16/20
Archit Taneja wrote:
On 06/22/2017 01:20 PM, Benjamin Gaignard wrote:
2017-06-20 19:31 GMT+02:00 Eric Anholt :
Archit Taneja writes:
On 06/16/2017 08:13 PM, Eric Anholt wrote:
Archit Taneja writes:
On 06/16/2017 02:11 AM, Eric Anholt wrote:
If the panel-bridge is being set
On 06/22/2017 01:20 PM, Benjamin Gaignard wrote:
2017-06-20 19:31 GMT+02:00 Eric Anholt <e...@anholt.net>:
Archit Taneja <arch...@codeaurora.org> writes:
On 06/16/2017 08:13 PM, Eric Anholt wrote:
Archit Taneja <arch...@codeaurora.org> writes:
On 06/16/2017 02:11 AM,
On 06/22/2017 01:20 PM, Benjamin Gaignard wrote:
2017-06-20 19:31 GMT+02:00 Eric Anholt :
Archit Taneja writes:
On 06/16/2017 08:13 PM, Eric Anholt wrote:
Archit Taneja writes:
On 06/16/2017 02:11 AM, Eric Anholt wrote:
If the panel-bridge is being set up after
On 06/16/2017 08:13 PM, Eric Anholt wrote:
Archit Taneja <arch...@codeaurora.org> writes:
On 06/16/2017 02:11 AM, Eric Anholt wrote:
If the panel-bridge is being set up after the drm_mode_config_reset(),
then the connector's state would never get initialized, and we'd
dereference th
On 06/16/2017 08:13 PM, Eric Anholt wrote:
Archit Taneja writes:
On 06/16/2017 02:11 AM, Eric Anholt wrote:
If the panel-bridge is being set up after the drm_mode_config_reset(),
then the connector's state would never get initialized, and we'd
dereference the NULL in the hotplug path. We
On 06/15/2017 11:24 PM, Eric Anholt wrote:
ERR_PTR() needs a negative errno argument.
Thanks, I'll queue it to drm-misc-next-fixes once it's opened.
Archit
Signed-off-by: Eric Anholt
---
drivers/gpu/drm/bridge/panel.c | 2 +-
1 file changed, 1 insertion(+), 1
On 06/15/2017 11:24 PM, Eric Anholt wrote:
ERR_PTR() needs a negative errno argument.
Thanks, I'll queue it to drm-misc-next-fixes once it's opened.
Archit
Signed-off-by: Eric Anholt
---
drivers/gpu/drm/bridge/panel.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
On 06/16/2017 02:11 AM, Eric Anholt wrote:
If the panel-bridge is being set up after the drm_mode_config_reset(),
then the connector's state would never get initialized, and we'd
dereference the NULL in the hotplug path. We also need to register
the connector, so that userspace can get at it.
On 06/16/2017 02:11 AM, Eric Anholt wrote:
If the panel-bridge is being set up after the drm_mode_config_reset(),
then the connector's state would never get initialized, and we'd
dereference the NULL in the hotplug path. We also need to register
the connector, so that userspace can get at it.
On 06/06/2017 11:22 PM, Eric Anholt wrote:
Maarten Lankhorst writes:
This fixes the following depmod error when building drm as a module:
depmod: ERROR: Found 6 modules in dependency cycles!
depmod: ERROR: Cycle detected: drm -> drm_kms_helper -> drm
On 06/06/2017 11:22 PM, Eric Anholt wrote:
Maarten Lankhorst writes:
This fixes the following depmod error when building drm as a module:
depmod: ERROR: Found 6 modules in dependency cycles!
depmod: ERROR: Cycle detected: drm -> drm_kms_helper -> drm
Fixes: 13dfc0540a57 ("drm/bridge:
On 06/06/2017 02:27 PM, Boris Brezillon wrote:
Hi Archit,
On Mon, 5 Jun 2017 21:06:20 +0530
Archit Taneja <arch...@codeaurora.org> wrote:
Hi,
When pushing to drm-misc-next, I got a minor merge conflict when dim tried
to rebuild drm-tip.
The reason for the conflict was b
On 06/06/2017 02:27 PM, Boris Brezillon wrote:
Hi Archit,
On Mon, 5 Jun 2017 21:06:20 +0530
Archit Taneja wrote:
Hi,
When pushing to drm-misc-next, I got a minor merge conflict when dim tried
to rebuild drm-tip.
The reason for the conflict was because the following commit was present
Hi,
When pushing to drm-misc-next, I got a minor merge conflict when dim tried
to rebuild drm-tip.
The reason for the conflict was because the following commit was present
in drm-tip but not in drm-misc:
Hi,
When pushing to drm-misc-next, I got a minor merge conflict when dim tried
to rebuild drm-tip.
The reason for the conflict was because the following commit was present
in drm-tip but not in drm-misc:
Anholt <e...@anholt.net>
Acked-by: Daniel Vetter <daniel.vet...@ffwll.ch> (v1)
Reviewed-by: Boris Brezillon <boris.brezil...@free-electrons.com> (v2)
Acked-by: Archit Taneja <arch...@codeaurora.org> (v2)
---
New version of the first patch with build fixes. I've re-pushed t
olt
Acked-by: Daniel Vetter (v1)
Reviewed-by: Boris Brezillon (v2)
Acked-by: Archit Taneja (v2)
---
New version of the first patch with build fixes. I've re-pushed to
get another round of kbuild test, but if it comes back clean, I'd like
to merge this one, the vc4 patches (unchanged), and atmel-hl
On 05/30/2017 03:59 PM, Philipp Zabel wrote:
Hi Archit,
On Tue, 2017-05-30 at 15:54 +0530, Archit Taneja wrote:
Hi,
On 05/25/2017 07:49 PM, Jose Abreu wrote:
Now that we have a callback to check if bridge supports a given mode
we can use it in Synopsys Designware HDMI bridge so that we
On 05/30/2017 03:59 PM, Philipp Zabel wrote:
Hi Archit,
On Tue, 2017-05-30 at 15:54 +0530, Archit Taneja wrote:
Hi,
On 05/25/2017 07:49 PM, Jose Abreu wrote:
Now that we have a callback to check if bridge supports a given mode
we can use it in Synopsys Designware HDMI bridge so that we
On 05/31/2017 01:37 PM, Boris Brezillon wrote:
Hi Archit,
Le Wed, 31 May 2017 13:31:16 +0530,
Archit Taneja <arch...@codeaurora.org> a écrit :
Hi Boris,
On 05/31/2017 11:56 AM, Boris Brezillon wrote:
Hi Philippe,
Le Tue, 30 May 2017 16:55:42 +,
Philippe CORNU <philippe.co.
On 05/31/2017 01:37 PM, Boris Brezillon wrote:
Hi Archit,
Le Wed, 31 May 2017 13:31:16 +0530,
Archit Taneja a écrit :
Hi Boris,
On 05/31/2017 11:56 AM, Boris Brezillon wrote:
Hi Philippe,
Le Tue, 30 May 2017 16:55:42 +,
Philippe CORNU a écrit :
Hi Eric,
I took your patch
Hi Boris,
On 05/31/2017 11:56 AM, Boris Brezillon wrote:
Hi Philippe,
Le Tue, 30 May 2017 16:55:42 +,
Philippe CORNU a écrit :
Hi Eric,
I took your patch for the panel-bridge and it works perfectly in both
DPI mode (panel RGB //) and DSI mode (bridge dw mipi
Hi Boris,
On 05/31/2017 11:56 AM, Boris Brezillon wrote:
Hi Philippe,
Le Tue, 30 May 2017 16:55:42 +,
Philippe CORNU a écrit :
Hi Eric,
I took your patch for the panel-bridge and it works perfectly in both
DPI mode (panel RGB //) and DSI mode (bridge dw mipi dsi), bravo :-)
I still
, there is no need to use mode_fixup() callback as mode_valid()
will handle the mode validation.
NOTE: Only compile tested.
Signed-off-by: Jose Abreu <joab...@synopsys.com>
Cc: Carlos Palminha <palmi...@synopsys.com>
Cc: Daniel Vetter <daniel.vet...@ffwll.ch>
Cc: Archit Taneja <arch.
, there is no need to use mode_fixup() callback as mode_valid()
will handle the mode validation.
NOTE: Only compile tested.
Signed-off-by: Jose Abreu
Cc: Carlos Palminha
Cc: Daniel Vetter
Cc: Archit Taneja
Cc: Andrzej Hajda
Cc: Laurent Pinchart
Cc: David Airlie
---
drivers/gpu/drm/bridge/analogix
los Palminha <palmi...@synopsys.com>
Cc: Daniel Vetter <daniel.vet...@ffwll.ch>
Cc: Archit Taneja <arch...@codeaurora.org>
Cc: Andrzej Hajda <a.ha...@samsung.com>
Cc: Laurent Pinchart <laurent.pinch...@ideasonboard.com>
Cc: David Airlie <airl...@linux.ie>
Cc: Philipp
been tested on Meson by Neil.
Since this also touches rockchip/imx drm driver files, can I get an
OK from the maintainers to pull the changes via drm-misc?
Thanks,
Archit
Signed-off-by: Jose Abreu
Acked-by: Neil Armstrong
Cc: Carlos Palminha
Cc: Daniel Vetter
Cc: Archit Taneja
Cc: Andrzej
as mode_valid()
will handle the mode validation.
Reviewed-by: Archit Taneja <arch...@codeaurora.org>
NOTE: Only compile tested.
Signed-off-by: Jose Abreu <joab...@synopsys.com>
Cc: Carlos Palminha <palmi...@synopsys.com>
Cc: Daniel Vetter <daniel.vet...@ffwll.ch>
Cc: Archit Taneja
as mode_valid()
will handle the mode validation.
Reviewed-by: Archit Taneja
NOTE: Only compile tested.
Signed-off-by: Jose Abreu
Cc: Carlos Palminha
Cc: Daniel Vetter
Cc: Archit Taneja
Cc: Andrzej Hajda
Cc: Laurent Pinchart
Cc: David Airlie
---
drivers/gpu/drm/bridge/analogix-anx78xx.c | 13
On 05/25/2017 07:49 PM, Jose Abreu wrote:
Introduce a new helper function which calls mode_valid() callback
for all bridges in an encoder chain.
Reviewed-by: Archit Taneja <arch...@codeaurora.org>
Signed-off-by: Jose Abreu <joab...@synopsys.com>
Reviewed-by: Daniel Vetter
On 05/25/2017 07:49 PM, Jose Abreu wrote:
Introduce a new helper function which calls mode_valid() callback
for all bridges in an encoder chain.
Reviewed-by: Archit Taneja
Signed-off-by: Jose Abreu
Reviewed-by: Daniel Vetter
Cc: Carlos Palminha
Cc: Ville Syrjälä
Cc: Dave Airlie
Cc
On 05/26/2017 09:46 AM, Archit Taneja wrote:
Hi,
On 05/25/2017 05:04 AM, Kuninori Morimoto wrote:
Hi Mark
Cc: DRM maintainer
ALSA SoC needs to know connected DAI ID for probing.
It is not a big problem if device/driver was only for sound,
but getting DAI ID will be difficult if device
On 05/26/2017 09:46 AM, Archit Taneja wrote:
Hi,
On 05/25/2017 05:04 AM, Kuninori Morimoto wrote:
Hi Mark
Cc: DRM maintainer
ALSA SoC needs to know connected DAI ID for probing.
It is not a big problem if device/driver was only for sound,
but getting DAI ID will be difficult if device
Hi,
On 05/25/2017 05:04 AM, Kuninori Morimoto wrote:
Hi Mark
Cc: DRM maintainer
ALSA SoC needs to know connected DAI ID for probing.
It is not a big problem if device/driver was only for sound,
but getting DAI ID will be difficult if device includes both
Video/Sound, like HDMI.
As far as I
Hi,
On 05/25/2017 05:04 AM, Kuninori Morimoto wrote:
Hi Mark
Cc: DRM maintainer
ALSA SoC needs to know connected DAI ID for probing.
It is not a big problem if device/driver was only for sound,
but getting DAI ID will be difficult if device includes both
Video/Sound, like HDMI.
As far as I
On 05/18/2017 08:25 PM, Laurent Pinchart wrote:
Hi Archit,
On Thursday 18 May 2017 13:56:19 Archit Taneja wrote:
On 05/17/2017 12:16 AM, Eric Anholt wrote:
[snip]
In terms of physical connections:
[15-pin "DSI" connector on 2835]
| I2C | DSI
/ \
On 05/18/2017 08:25 PM, Laurent Pinchart wrote:
Hi Archit,
On Thursday 18 May 2017 13:56:19 Archit Taneja wrote:
On 05/17/2017 12:16 AM, Eric Anholt wrote:
[snip]
In terms of physical connections:
[15-pin "DSI" connector on 2835]
| I2C | DSI
/ \
Hi,
On 05/17/2017 12:16 AM, Eric Anholt wrote:
Laurent Pinchart writes:
Hi Eric,
On Tuesday 16 May 2017 09:47:49 Eric Anholt wrote:
Rob Herring writes:
On Mon, May 15, 2017 at 7:03 PM, Eric Anholt wrote:
Laurent
Hi,
On 05/17/2017 12:16 AM, Eric Anholt wrote:
Laurent Pinchart writes:
Hi Eric,
On Tuesday 16 May 2017 09:47:49 Eric Anholt wrote:
Rob Herring writes:
On Mon, May 15, 2017 at 7:03 PM, Eric Anholt wrote:
Laurent Pinchart writes:
Hi Eric,
Thank you for the patch.
On Thursday 11 May
On 05/18/2017 09:59 AM, Masahiro Yamada wrote:
With the include directives under include/drm/ fixed, this flag is
no longer needed.
Acked-by: Archit Taneja <arch...@codeaurora.org>
Signed-off-by: Masahiro Yamada <yamada.masah...@socionext.com>
---
Changes in v3: None
dri
On 05/18/2017 09:59 AM, Masahiro Yamada wrote:
With the include directives under include/drm/ fixed, this flag is
no longer needed.
Acked-by: Archit Taneja
Signed-off-by: Masahiro Yamada
---
Changes in v3: None
drivers/gpu/drm/i2c/Makefile | 2 --
1 file changed, 2 deletions(-)
diff
A few members in ion_buffer struct are unused after features
like page faulting, ion_handle and ion_client were removed.
Remove these members and the leftover references to them.
Signed-off-by: Archit Taneja <arch...@codeaurora.org>
---
drivers/staging/android/ion/ion.c | 2 --
drivers/s
twice.
Don't call free_duped_table() in ion_map_dma_buf() to avoid this.
Signed-off-by: Archit Taneja <arch...@codeaurora.org>
---
drivers/staging/android/ion/ion.c | 12 +++-
1 file changed, 3 insertions(+), 9 deletions(-)
diff --git a/drivers/staging/android/ion/ion.c
b/drivers/s
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