division.
Signed-off-by: Archit Taneja
---
drivers/clk/qcom/clk-rcg2.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index 08b8b37..4fe9c01 100644
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk/qcom/clk-rcg2.c
On 03/04/2015 09:14 PM, Stéphane Viau wrote:
Hi,
Hi Archit,
On 03/04/2015 12:06 AM, Stephane Viau wrote:
Up until now, we assume that eDP is tight to intf_0 and HDMI to
intf_3. This information shall actually come from the mdp5_cfg
module since it can change from one chip to another.
division.
Signed-off-by: Archit Taneja arch...@codeaurora.org
---
drivers/clk/qcom/clk-rcg2.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index 08b8b37..4fe9c01 100644
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk
v1:
* Addressed comments from Stephen Boyd and Archit Taneja
* Fixed some incorrect offsets, parents etc.
* Driver is tested on MSM8916-MTP device.
For MDSS clocks:
Tested-by: Archit Taneja arch...@codeaurora.org
Thanks,
Archit
--
Qualcomm Innovation Center, Inc. is a member of Code
Hi,
On 03/04/2015 12:06 AM, Stephane Viau wrote:
DSI and WB interfaces need a more complex pipeline configuration
than the current mdp5_ctl_set_intf().
For example, memory output connections need to be selected for
WB. Interface mode (Video vs. Command modes) also need to be
configured for
Hi,
On 03/04/2015 12:06 AM, Stephane Viau wrote:
Up until now, we assume that eDP is tight to intf_0 and HDMI to
intf_3. This information shall actually come from the mdp5_cfg
module since it can change from one chip to another.
Signed-off-by: Stephane Viau
---
Hi,
On 03/04/2015 12:06 AM, Stephane Viau wrote:
Up until now, we assume that eDP is tight to intf_0 and HDMI to
intf_3. This information shall actually come from the mdp5_cfg
module since it can change from one chip to another.
Signed-off-by: Stephane Viau sv...@codeaurora.org
---
Hi,
On 03/04/2015 12:06 AM, Stephane Viau wrote:
DSI and WB interfaces need a more complex pipeline configuration
than the current mdp5_ctl_set_intf().
For example, memory output connections need to be selected for
WB. Interface mode (Video vs. Command modes) also need to be
configured for
Hi Georgi,
On 02/24/2015 09:19 PM, Georgi Djakov wrote:
On 02/24/2015 06:49 AM, Archit Taneja wrote:
Hi,
[..]
+
+static struct freq_tbl ftbl_gcc_mdss_pclk[] = {
+{ .src = P_DSI0_PHYPLL_DSI },
+{ }
+};
+
+static struct clk_rcg2 pclk0_clk_src = {
+.cmd_rcgr = 0x4d084,
This should
Hi Georgi,
On 02/24/2015 09:19 PM, Georgi Djakov wrote:
On 02/24/2015 06:49 AM, Archit Taneja wrote:
Hi,
[..]
+
+static struct freq_tbl ftbl_gcc_mdss_pclk[] = {
+{ .src = P_DSI0_PHYPLL_DSI },
+{ }
+};
+
+static struct clk_rcg2 pclk0_clk_src = {
+.cmd_rcgr = 0x4d084,
This should
Hi,
On 02/07/2015 12:28 AM, Georgi Djakov wrote:
This is preliminary and not fully tested patch which adds
support for the global clock controller found on the MSM8916
based devices. It allows the various device drivers to probe
and control their clocks and resets.
Signed-off-by: Georgi Djakov
The DRM_KMS_FB_HELPER config is selected only when DRM_MSM_FBDEV config is
selected. The driver accesses drm_fb_helper_* functions even when legacy fbdev
support is disabled in msm. Wrap around these functions with #ifdef checks to
prevent build break.
Signed-off-by: Archit Taneja
---
drivers
The DRM_KMS_FB_HELPER config is selected only when DRM_MSM_FBDEV config is
selected. The driver accesses drm_fb_helper_* functions even when legacy fbdev
support is disabled in msm. Wrap around these functions with #ifdef checks to
prevent build break.
Signed-off-by: Archit Taneja arch
Hi,
On 02/07/2015 12:28 AM, Georgi Djakov wrote:
This is preliminary and not fully tested patch which adds
support for the global clock controller found on the MSM8916
based devices. It allows the various device drivers to probe
and control their clocks and resets.
Signed-off-by: Georgi Djakov
Add register offset table entry for the newer (v1.7.0) version of the BAM IP
found on MSM8916. Update the DT bindings documentation.
Signed-off-by: Archit Taneja
---
Change in v2: Fix wrong execution environment multiplier for BAM_IRQ_SRCS_EE and
BAM_IRQ_SRCS_MSK_EE
Add register offset table entry for the newer (v1.7.0) version of the BAM IP
found on MSM8916. Update the DT bindings documentation.
Signed-off-by: Archit Taneja arch...@codeaurora.org
---
Change in v2: Fix wrong execution environment multiplier for BAM_IRQ_SRCS_EE
},
[BAM_P_DATA_FIFO_ADDR] = { 0x1824, 0x00, 0x1000, 0x00 },
[BAM_P_DESC_FIFO_ADDR] = { 0x181C, 0x00, 0x1000, 0x00 },
[BAM_P_EVNT_GEN_TRSHLD] = { 0x1828, 0x00, 0x1000, 0x00 },
Didn't know how this crept in. Apologies for the inconvenience!
Reviewed-by: Archit Taneja
--
Qualcomm
, 0x00 },
[BAM_P_DATA_FIFO_ADDR] = { 0x1824, 0x00, 0x1000, 0x00 },
[BAM_P_DESC_FIFO_ADDR] = { 0x181C, 0x00, 0x1000, 0x00 },
[BAM_P_EVNT_GEN_TRSHLD] = { 0x1828, 0x00, 0x1000, 0x00 },
Didn't know how this crept in. Apologies for the inconvenience!
Reviewed-by: Archit Taneja
Hi,
On 01/16/2015 08:18 PM, Archit Taneja wrote:
Add support for the NAND controller driver for SoC's that contain EBI2. For now,
the only SoC upstream that has EBI2 is IPQ806x.
The patchset requires the ADM dmaengine patches posted by Andy:
http://thread.gmane.org/gmane.linux.ports.arm.msm
Hi,
On 01/16/2015 08:18 PM, Archit Taneja wrote:
Add support for the NAND controller driver for SoC's that contain EBI2. For now,
the only SoC upstream that has EBI2 is IPQ806x.
The patchset requires the ADM dmaengine patches posted by Andy:
http://thread.gmane.org/gmane.linux.ports.arm.msm
On 01/27/2015 02:35 AM, Kevin Cernekee wrote:
On Wed, Jan 21, 2015 at 10:36 PM, Archit Taneja wrote:
On 01/21/2015 06:24 AM, Daniel Ehrenberg wrote:
On Fri, Jan 16, 2015 at 6:48 AM, Archit Taneja
wrote:
+/*
+ * the bad block marker is readable only when we read the page with ECC
On 01/27/2015 02:35 AM, Kevin Cernekee wrote:
On Wed, Jan 21, 2015 at 10:36 PM, Archit Taneja arch...@codeaurora.org wrote:
On 01/21/2015 06:24 AM, Daniel Ehrenberg wrote:
On Fri, Jan 16, 2015 at 6:48 AM, Archit Taneja arch...@codeaurora.org
wrote:
+/*
+ * the bad block marker is readable
Add register offset table entry for the newer (v1.7.0) version of the BAM IP
found on MSM8916. Update the DT bindings documentation.
Signed-off-by: Archit Taneja
---
.../devicetree/bindings/dma/qcom_bam_dma.txt | 1 +
drivers/dma/qcom_bam_dma.c | 30
Hi,
On 01/21/2015 06:24 AM, Daniel Ehrenberg wrote:
On Fri, Jan 16, 2015 at 6:48 AM, Archit Taneja wrote:
+/*
+ * the bad block marker is readable only when we read the page with ECC
+ * disabled. all the read/write commands like NAND_CMD_READOOB, NAND_CMD_READ0
+ * and NAND_CMD_PAGEPROG
Hi,
On 01/21/2015 06:24 AM, Daniel Ehrenberg wrote:
On Fri, Jan 16, 2015 at 6:48 AM, Archit Taneja arch...@codeaurora.org wrote:
+/*
+ * the bad block marker is readable only when we read the page with ECC
+ * disabled. all the read/write commands like NAND_CMD_READOOB, NAND_CMD_READ0
Add register offset table entry for the newer (v1.7.0) version of the BAM IP
found on MSM8916. Update the DT bindings documentation.
Signed-off-by: Archit Taneja arch...@codeaurora.org
---
.../devicetree/bindings/dma/qcom_bam_dma.txt | 1 +
drivers/dma/qcom_bam_dma.c
Hi,
On 01/17/2015 03:26 AM, Stephen Boyd wrote:
On 01/16/2015 06:48 AM, Archit Taneja wrote:
The NAND controller within EBI2 requires EBI2_CLK and EBI2_ALWAYS_ON_CLK clocks.
Create structs for these clocks so that they can be used by the NAND controller
driver. Add an entry for EBI2_AON_CLK
Hi,
On 01/17/2015 03:26 AM, Stephen Boyd wrote:
On 01/16/2015 06:48 AM, Archit Taneja wrote:
The NAND controller within EBI2 requires EBI2_CLK and EBI2_ALWAYS_ON_CLK clocks.
Create structs for these clocks so that they can be used by the NAND controller
driver. Add an entry for EBI2_AON_CLK
The nand controller in IPQ806x is of the 'EBI2 type'. Use the corresponding
compatible string.
Cc: devicet...@vger.kernel.org
Signed-off-by: Archit Taneja
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/arch/arm
Cc: devicet...@vger.kernel.org
Signed-off-by: Archit Taneja
---
.../devicetree/bindings/mtd/qcom_nandc.txt | 48 ++
1 file changed, 48 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/qcom_nandc.txt
diff --git a/Documentation/devicetree
Enable the NAND controller node on the AP148 platform. Provide pinmux
information.
Cc: devicet...@vger.kernel.org
Signed-off-by: Archit Taneja
---
arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 32
1 file changed, 32 insertions(+)
diff --git a/arch/arm/boot/dts
-off-by: Archit Taneja
---
drivers/mtd/nand/Kconfig |7 +
drivers/mtd/nand/Makefile |1 +
drivers/mtd/nand/qcom_nandc.c | 1995 +
3 files changed, 2003 insertions(+)
create mode 100644 drivers/mtd/nand/qcom_nandc.c
diff --git a/drivers/mtd
The NAND controller within EBI2 requires EBI2_CLK and EBI2_ALWAYS_ON_CLK clocks.
Create structs for these clocks so that they can be used by the NAND controller
driver. Add an entry for EBI2_AON_CLK in the gcc-ipq806x DT binding document.
Cc: Stephen Boyd
Signed-off-by: Archit Taneja
Add support for the NAND controller driver for SoC's that contain EBI2. For now,
the only SoC upstream that has EBI2 is IPQ806x.
The patchset requires the ADM dmaengine patches posted by Andy:
http://thread.gmane.org/gmane.linux.ports.arm.msm/11136
Archit Taneja (5):
clk: qcom: Add EBI2
Add support for the NAND controller driver for SoC's that contain EBI2. For now,
the only SoC upstream that has EBI2 is IPQ806x.
The patchset requires the ADM dmaengine patches posted by Andy:
http://thread.gmane.org/gmane.linux.ports.arm.msm/11136
Archit Taneja (5):
clk: qcom: Add EBI2
-by: Archit Taneja arch...@codeaurora.org
---
drivers/clk/qcom/gcc-ipq806x.c | 34
include/dt-bindings/clock/qcom,gcc-ipq806x.h | 1 +
2 files changed, 35 insertions(+)
diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
index afed5eb
-off-by: Archit Taneja arch...@codeaurora.org
---
drivers/mtd/nand/Kconfig |7 +
drivers/mtd/nand/Makefile |1 +
drivers/mtd/nand/qcom_nandc.c | 1995 +
3 files changed, 2003 insertions(+)
create mode 100644 drivers/mtd/nand/qcom_nandc.c
diff
Enable the NAND controller node on the AP148 platform. Provide pinmux
information.
Cc: devicet...@vger.kernel.org
Signed-off-by: Archit Taneja arch...@codeaurora.org
---
arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 32
1 file changed, 32 insertions(+)
diff --git
Cc: devicet...@vger.kernel.org
Signed-off-by: Archit Taneja arch...@codeaurora.org
---
.../devicetree/bindings/mtd/qcom_nandc.txt | 48 ++
1 file changed, 48 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/qcom_nandc.txt
diff --git
The nand controller in IPQ806x is of the 'EBI2 type'. Use the corresponding
compatible string.
Cc: devicet...@vger.kernel.org
Signed-off-by: Archit Taneja arch...@codeaurora.org
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 19 ++-
1 file changed, 18 insertions(+), 1 deletion
Hi,
On 01/08/2015 08:56 AM, Andy Gross wrote:
Signed-off-by: Andy Gross
+static struct dma_async_tx_descriptor *adm_prep_slave_sg(struct dma_chan *chan,
+ struct scatterlist *sgl, unsigned int sg_len,
+ enum dma_transfer_direction direction, unsigned long flags,
+ void
Hi,
On 01/08/2015 08:56 AM, Andy Gross wrote:
Signed-off-by: Andy Gross agr...@codeaurora.org
snip
+static struct dma_async_tx_descriptor *adm_prep_slave_sg(struct dma_chan *chan,
+ struct scatterlist *sgl, unsigned int sg_len,
+ enum dma_transfer_direction direction, unsigned
specified in the compatible string.
Reviewed-by: Kumar Gala
Reviewed-by: Andy Gross
Signed-off-by: Archit Taneja
---
drivers/dma/qcom_bam_dma.c | 58 +++---
1 file changed, 50 insertions(+), 8 deletions(-)
diff --git a/drivers/dma/qcom_bam_dma.c b
Add compatible string for BAM v1.3.0 in the DT bindings documentation. Mentioned
a few more SoCs which have BAM v1.4.0 in them.
Reviewed-by: Kumar Gala
Reviewed-by: Andy Gross
Signed-off-by: Archit Taneja
---
Update in v2: Added IPQ8064 to the v1.3.0 list
Documentation/devicetree/bindings
Signed-off-by: Archit Taneja
---
drivers/dma/qcom_bam_dma.c | 176 +
1 file changed, 113 insertions(+), 63 deletions(-)
diff --git a/drivers/dma/qcom_bam_dma.c b/drivers/dma/qcom_bam_dma.c
index 7a4bbb0..b5a1662 100644
--- a/drivers/dma/qcom_bam_dma.c
Reviewed-by: Andy Gross agr...@codeaurora.org
Signed-off-by: Archit Taneja arch...@codeaurora.org
---
drivers/dma/qcom_bam_dma.c | 176 +
1 file changed, 113 insertions(+), 63 deletions(-)
diff --git a/drivers/dma/qcom_bam_dma.c b/drivers/dma/qcom_bam_dma.c
specified in the compatible string.
Reviewed-by: Kumar Gala ga...@codeaurora.org
Reviewed-by: Andy Gross agr...@codeaurora.org
Signed-off-by: Archit Taneja arch...@codeaurora.org
---
drivers/dma/qcom_bam_dma.c | 58 +++---
1 file changed, 50 insertions(+), 8
Add compatible string for BAM v1.3.0 in the DT bindings documentation. Mentioned
a few more SoCs which have BAM v1.4.0 in them.
Reviewed-by: Kumar Gala ga...@codeaurora.org
Reviewed-by: Andy Gross agr...@codeaurora.org
Signed-off-by: Archit Taneja arch...@codeaurora.org
---
Update in v2: Added
-by: Darren Etheridge
DMM doesn't get used by default since it's hwmod is missing in DRA7x's
hwmod data. I added the hwmod and tried using dmm with omapdrm, it works
fine.
So, for DSS and DMM:
Tested-by: Archit Taneja
arch/arm/boot/dts/dra7.dtsi | 109
to add:
Tested-by: Darren Etheridge detheri...@ti.com
DMM doesn't get used by default since it's hwmod is missing in DRA7x's
hwmod data. I added the hwmod and tried using dmm with omapdrm, it works
fine.
So, for DSS and DMM:
Tested-by: Archit Taneja arc...@ti.com
arch/arm/boot/dts/dra7
Hi,
On Tuesday 18 March 2014 04:11 PM, Bartlomiej Zolnierkiewicz wrote:
devm_ioremap_resource() returns a pointer to the remapped memory or
an ERR_PTR() encoded error code on failure. Fix the checks inside
csc_create() and sc_create() accordingly.
Cc: Archit Taneja
Cc: Hans Verkuil
Signed
Hi,
On Tuesday 18 March 2014 04:11 PM, Bartlomiej Zolnierkiewicz wrote:
devm_ioremap_resource() returns a pointer to the remapped memory or
an ERR_PTR() encoded error code on failure. Fix the checks inside
csc_create() and sc_create() accordingly.
Cc: Archit Taneja arc...@ti.com
Cc: Hans
Hi,
On Saturday 11 January 2014 06:12 PM, Ivaylo Dimitrov wrote:
From: Ivaylo Dimitrov
commit 7faa92339bbb1e6b9a80983b206642517327eb75 OMAPDSS: DISPC: Handle
synclost errors in OMAP3 introduces limits check to prevent SYNCLOST errors
on OMAP3. However, it misses the logic found in Nokia
Hi,
On Saturday 11 January 2014 06:12 PM, Ivaylo Dimitrov wrote:
From: Ivaylo Dimitrov freemangor...@abv.bg
commit 7faa92339bbb1e6b9a80983b206642517327eb75 OMAPDSS: DISPC: Handle
synclost errors in OMAP3 introduces limits check to prevent SYNCLOST errors
on OMAP3. However, it misses the logic
Hi,
On Tuesday 27 August 2013 01:44 PM, Tomasz Figa wrote:
Hi Laurent,
On Tuesday 27 of August 2013 10:02:39 Laurent Pinchart wrote:
Add DT bindings for the pcf857x-compatible chips and parse the device
tree node in the driver.
Signed-off-by: Laurent Pinchart
---
Hi,
On Tuesday 27 August 2013 01:44 PM, Tomasz Figa wrote:
Hi Laurent,
On Tuesday 27 of August 2013 10:02:39 Laurent Pinchart wrote:
Add DT bindings for the pcf857x-compatible chips and parse the device
tree node in the driver.
Signed-off-by: Laurent Pinchart
Hi,
On Wednesday 10 July 2013 06:38 PM, Pali Rohár wrote:
* On RX-51 probing for acx565akm driver is later then for omapfb which cause
that omapfb probe fail and framebuffer is not working
* EPROBE_DEFER causing that kernel try to probe for omapfb later again which
fixing this problem
*
Hi,
On Wednesday 10 July 2013 06:38 PM, Pali Rohár wrote:
* On RX-51 probing for acx565akm driver is later then for omapfb which cause
that omapfb probe fail and framebuffer is not working
* EPROBE_DEFER causing that kernel try to probe for omapfb later again which
fixing this problem
*
Hi,
On Monday 17 June 2013 02:35 PM, Linus Walleij wrote:
On Thu, Jun 6, 2013 at 4:05 PM, Archit Taneja wrote:
Add code to parse the GPIO expander Device Tree node and extract platform data
out of it, and populate the struct 'pcf857x_platform_data' maintained by the
driver. This enables
Hi,
On Monday 17 June 2013 02:35 PM, Linus Walleij wrote:
On Thu, Jun 6, 2013 at 4:05 PM, Archit Taneja arc...@ti.com wrote:
Add code to parse the GPIO expander Device Tree node and extract platform data
out of it, and populate the struct 'pcf857x_platform_data' maintained by the
driver
-off-by: Archit Taneja
---
.../devicetree/bindings/gpio/gpio-pcf857x.txt | 44 +
drivers/gpio/gpio-pcf857x.c| 57 --
2 files changed, 97 insertions(+), 4 deletions(-)
create mode 100644 Documentation/devicetree/bindings/gpio/gpio
Hi,
On Wednesday 05 June 2013 10:59 PM, Emil Goode wrote:
It's not necessary to free memory allocated with devm_kzalloc
in a remove function and using kfree leads to a double free.
Looks fine to me. Tomi, could you take this for 3.11?
Archit
Signed-off-by: Emil Goode
---
Hi,
On Wednesday 05 June 2013 10:59 PM, Emil Goode wrote:
It's not necessary to free memory allocated with devm_kzalloc
in a remove function and using kfree leads to a double free.
Looks fine to me. Tomi, could you take this for 3.11?
Archit
Signed-off-by: Emil Goode emilgo...@gmail.com
grant.lik...@secretlab.ca
Signed-off-by: Archit Taneja arc...@ti.com
---
.../devicetree/bindings/gpio/gpio-pcf857x.txt | 44 +
drivers/gpio/gpio-pcf857x.c| 57 --
2 files changed, 97 insertions(+), 4 deletions(-)
create mode 100644
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