On Sat, Apr 17, 2021 at 8:36 PM Atish Patra wrote:
>
> On Mon, Mar 29, 2021 at 10:04 AM Vitaly Wool wrote:
> >
> > On Sat, Mar 27, 2021 at 6:24 PM Alex Ghiti wrote:
> > >
> > > Hi Atish,
> > >
> > > Le 3/3/21 à 3:02 PM, Atish Patra a écri
On Mon, Mar 29, 2021 at 10:04 AM Vitaly Wool wrote:
>
> On Sat, Mar 27, 2021 at 6:24 PM Alex Ghiti wrote:
> >
> > Hi Atish,
> >
> > Le 3/3/21 à 3:02 PM, Atish Patra a écrit :
> > > Add initial DTS for Microchip ICICLE board having only
> > > es
On Mon, Mar 29, 2021 at 9:17 PM Palmer Dabbelt wrote:
>
> On Wed, 03 Mar 2021 12:02:48 PST (-0800), Atish Patra wrote:
> > This series adds minimal support for Microchip Polar Fire Soc Icicle kit.
> > It is rebased on v5.12-rc1 and depends on clock support.
> > Only
Signed-off-by: Atish Patra
---
arch/riscv/include/asm/csr.h | 58
1 file changed, 58 insertions(+)
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index caadfc1d7487..7ce8df8f1683 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch
in this core driver wile PMU specific driver can implement PMU
specific features. For example, the SBI specific functionality will be
implemented in the SBI specific driver.
Signed-off-by: Atish Patra
---
drivers/perf/Kconfig | 8 +
drivers/perf/Makefile | 1 +
drivers
, it provides an easy way out in future where we can remove the
legacy driver.
Signed-off-by: Atish Patra
---
drivers/perf/Kconfig| 9
drivers/perf/Makefile | 3 ++
drivers/perf/riscv_pmu.c| 2 +
drivers/perf/riscv_pmu_legacy.c | 88
This patch adds all the definitions defined by the SBI PMU extension.
Signed-off-by: Atish Patra
---
arch/riscv/include/asm/sbi.h | 80
1 file changed, 80 insertions(+)
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index
message/598
[2] https://github.com/atishp04/qemu/tree/riscv_pmu_v1
[3] https://github.com/atishp04/opensbi/tree/riscv_pmu_v1
[4] https://github.com/atishp04/linux/tree/riscv_pmu_v1
Atish Patra (6):
RISC-V: Remove the current perf implementation
RISC-V: Add CSR encodings for all HPMCOUNTERS
RISC-V: Ad
most of the missing functionality.
Signed-off-by: Atish Patra
---
arch/riscv/Kconfig | 13 -
arch/riscv/include/asm/perf_event.h | 72 -
arch/riscv/kernel/Makefile | 1 -
arch/riscv/kernel/perf_event.c | 485
4 files changed, 571
of firmware counters that can provide
insights into firmware activity during a performance analysis.
Signed-off-by: Atish Patra
---
drivers/perf/Kconfig | 8 +
drivers/perf/Makefile | 1 +
drivers/perf/riscv_pmu.c | 12 +-
drivers/perf/riscv_pmu_sbi.c | 464
> sizeof(*mem_res);
> mem_res = memblock_alloc(mem_res_sz, SMP_CACHE_BYTES);
> if (!mem_res)
> panic("%s: Failed to allocate %zu bytes\n", __func__,
> mem_res_sz);
> --
> 2.25.1
>
>
> _______
> linux-riscv mailing list
> linux-ri...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
Thanks for catching the bug & fixing it.
Reviewed-by: Atish Patra
--
Regards,
Atish
fo("SBI RFENCE extension detected\n");
> } else {
> __sbi_rfence= __sbi_rfence_v01;
> }
> --
> 2.25.1
>
>
> ___
> linux-riscv mailing list
> linux-ri...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
Reviewed-by: Atish Patra
--
Regards,
Atish
On Tue, 2021-03-09 at 13:30 +, lewis.ha...@microchip.com wrote:
>
>
> From: Ben Dooks
> Sent: Tuesday, March 9, 2021 10:56 AM
> To: Atish Patra ; linux-kernel@vger.kernel.org <
> linux-kernel@vger.kernel.org>
> Cc: Albert Ou ; Alistair Francis <
> alis
On Mon, Mar 8, 2021 at 2:55 AM Anup Patel wrote:
>
> On Mon, Mar 8, 2021 at 1:19 PM Atish Patra wrote:
> >
> > On Sat, Mar 6, 2021 at 4:12 AM Anup Patel wrote:
> > >
> > > On Sat, Mar 6, 2021 at 11:19 AM Heinrich Schuchardt
> > > wrote:
> > &
On Sun, Mar 7, 2021 at 11:49 PM Atish Patra wrote:
>
> On Sat, Mar 6, 2021 at 4:12 AM Anup Patel wrote:
> >
> > On Sat, Mar 6, 2021 at 11:19 AM Heinrich Schuchardt
> > wrote:
> > >
> > > The constants in enum sbi_ext_rfence_fid should match th
On Sat, Mar 6, 2021 at 4:12 AM Anup Patel wrote:
>
> On Sat, Mar 6, 2021 at 11:19 AM Heinrich Schuchardt
> wrote:
> >
> > The constants in enum sbi_ext_rfence_fid should match the SBI
> > specification. See
> >
From: Conor Dooley
Add Cyril Jean and Lewis Hanly as maintainers for the Microchip SoC
directory
Signed-off-by: Conor Dooley
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index d92f85ca831d..cf186eca1784 100644
--- a/MAINTAINERS
+++
Enable Microchip PolarFire ICICLE soc config in defconfig.
It allows the default upstream kernel to boot on PolarFire ICICLE board.
Signed-off-by: Atish Patra
Reviewed-by: Anup Patel
Reviewed-by: Bin Meng
---
arch/riscv/configs/defconfig | 4
1 file changed, 4 insertions(+)
diff --git
Add Microchip PolarFire kconfig option which selects SoC specific
and common drivers that is required for this SoC.
Signed-off-by: Atish Patra
Reviewed-by: Bin Meng
Reviewed-by: Anup Patel
---
arch/riscv/Kconfig.socs | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/riscv
Add initial DTS for Microchip ICICLE board having only
essential devices (clocks, sdhci, ethernet, serial, etc).
The device tree is based on the U-Boot patch.
https://patchwork.ozlabs.org/project/uboot/patch/20201110103414.10142-6-padmarao.beg...@microchip.com/
Signed-off-by: Atish Patra
Add YAML DT binding documentation for the Microchip PolarFire SoC.
It is documented at:
https://www.microsemi.com/products/fpga-soc/polarfire-soc-icicle-quick-start-guide
Signed-off-by: Atish Patra
---
.../devicetree/bindings/riscv/microchip.yaml | 27 +++
1 file changed, 27
ed the DT to match the device tree in U-Boot.
2. Added both eMMC & SDcard entries in DT. However, SD card is only enabled
as it allows larger storage option for linux distros.
Atish Patra (4):
RISC-V: Add Microchip PolarFire SoC kconfig option
dt-bindings: riscv: microchip: Add YAML
m_power_off = sbi_srst_power_off;
> + sbi_srst_reboot_nb.notifier_call = sbi_srst_reboot;
> + sbi_srst_reboot_nb.priority = 192;
> + register_restart_handler(_srst_reboot_nb);
> + }
> } else {
> __sbi_set_timer = __sbi_set_timer_v01;
> __sbi_send_ipi = __sbi_send_ipi_v01;
> --
> 2.25.1
>
>
> ___
> linux-riscv mailing list
> linux-ri...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
Reviewed-by: Atish Patra
--
Regards,
Atish
On Mon, Feb 22, 2021 at 5:52 PM Palmer Dabbelt wrote:
>
> On Mon, 22 Feb 2021 14:38:28 PST (-0800), ati...@atishpatra.org wrote:
> > On Mon, Feb 22, 2021 at 12:23 PM Guenter Roeck wrote:
> >>
> >> On Wed, Feb 03, 2021 at 09:26:43PM -0800, Atish Patra wrote:
> &
On Mon, Feb 22, 2021 at 12:23 PM Guenter Roeck wrote:
>
> On Wed, Feb 03, 2021 at 09:26:43PM -0800, Atish Patra wrote:
> > SBI v0.2 functions can return an error code from SBI implementation.
> > We are already processing the SBI error code and coverts it to the Li
On Sat, Feb 6, 2021 at 2:02 AM Heinrich Schuchardt wrote:
>
> * Mention RISC-V.
> * Update code references.
> * initrd= does not specify a path relative on the ESP but to the partition
> from which the EFI stub was loaded (as specified in the loaded image
> protocol).
> * Mention that ACPI
SBI RESET extension allows OS to initiate a system wide reboot or shutdown.
Implement the SBI RESET extension so that guests can issue shutdown/reset
requests as well.
Signed-off-by: Atish Patra
---
arch/riscv/include/asm/kvm_vcpu_sbi.h | 1 +
arch/riscv/kvm/vcpu_sbi.c | 17
. If the guest OS doesn't implement HSM
extension, only single vcpu will be available to OS.
Signed-off-by: Atish Patra
---
arch/riscv/include/asm/sbi.h | 1 +
arch/riscv/kvm/Makefile | 2 +-
arch/riscv/kvm/vcpu.c | 19 ++
arch/riscv/kvm/vcpu_sbi.c | 4 ++
arch/riscv/kvm
SBI v0.2 base extension defined to allow backward compatibility and
probing of future extensions. This is also the only mandatory SBI
extension that must be implemented by SBI implementors.
Signed-off-by: Atish Patra
---
arch/riscv/include/asm/kvm_vcpu_sbi.h | 2 +
arch/riscv/include/asm/sbi.h
.
Signed-off-by: Atish Patra
---
arch/riscv/include/asm/kvm_vcpu_sbi.h | 1 +
arch/riscv/kvm/Makefile | 2 +-
arch/riscv/kvm/vcpu_sbi.c | 126 +
arch/riscv/kvm/vcpu_sbi_legacy.c | 129 ++
4 files changed, 136
The SBI v0.2 contains some of the improved versions of required v0.1
extensions such as remote fence, timer and IPI.
This patch implements those extensions.
Signed-off-by: Atish Patra
---
arch/riscv/kvm/Makefile | 2 +-
arch/riscv/kvm/vcpu_sbi.c | 6 ++
arch/riscv/kvm
PGA with Rocket core design.
[1] https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.adoc
[2] http://lists.infradead.org/pipermail/linux-riscv/2021-January/004251.html
Atish Patra (6):
RISC-V: Mark the existing SBI v0.1 implementation as legacy
RISC-V: Reorganize SBI code by moving legacy
The existing SBI specification impelementation follows v0.1 or legacy
specification. The latest specification known as v0.2 allows more
scalability and performance improvements.
Rename the existing implementation as legacy and provide a way to allow
future extensions.
Signed-off-by: Atish Patra
SBI v0.2 functions can return an error code from SBI implementation.
We are already processing the SBI error code and coverts it to the Linux
error code.
Propagate to the error code to the caller as well. As of now, kvm is the
only user of these error codes.
Signed-off-by: Atish Patra
---
arch
CH_NUMA
> select OF_NUMA
> select ARCH_SUPPORTS_NUMA_BALANCING
> --
> 2.26.2
>
>
> ___
> linux-riscv mailing list
> linux-ri...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
Reviewed-by: Atish Patra
--
Regards,
Atish
gt; linux-riscv mailing list
> linux-ri...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
Reviewed-by: Atish Patra
--
Regards,
Atish
From: Sebastien Van Cauwenberghe
Allows the sections to be aligned on smaller boundaries and
therefore results in a smaller kernel image size.
Signed-off-by: Sebastien Van Cauwenberghe
Reviewed-by: Atish Patra
---
arch/riscv/include/asm/set_memory.h | 6 +++---
1 file changed, 3 insertions
64
2, MAXPHYSMEM_2GB & RV32
Fixes: e557793799c5 ("RISC-V: Fix maximum allowed phsyical memory for RV32")
Fix this by restricting MAXPHYSMEM_1GB for RV32 and MAXPHYSMEM_2GB only for
RV64.
Reported-by: Randy Dunlap
Acked-by: Randy Dunlap
Tested-by: Geert Uytterhoeven
Signed-off-by: Atis
Signed-off-by: Atish Patra
---
arch/riscv/kernel/setup.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c
index 3fa3f26dde85..c7c0655dd45b 100644
--- a/arch/riscv/kernel/setup.c
+++ b/arch/riscv/kernel/setup.c
@@ -29
info("Faking a node at [mem %#018Lx-%#018Lx]\n", start,
> end - 1);
>
> Fixes: ae3c107cd8be ("numa: Move numa implementation to common code")
> Signed-off-by: Randy Dunlap
> Reported-by: kernel test robot
> Cc: Atish Patra
> Cc: Palmer Dabbelt
> ---
>
On Wed, Jan 27, 2021 at 7:18 PM Randy Dunlap wrote:
>
> Hi,
>
> I took a riscv-32 .config from kernel test robot (it was for a clang build)
> and did a "make olddefconfig" (using gcc tools) and got build errors
> due to this config item from arch/riscv/Kconfig;
>
>
> config PAGE_OFFSET
>
On Thu, Jan 14, 2021 at 11:59 PM Geert Uytterhoeven
wrote:
>
> Hi Atish,
>
> On Thu, Jan 14, 2021 at 10:11 PM Atish Patra wrote:
> > On Thu, Jan 14, 2021 at 11:46 AM Palmer Dabbelt wrote:
> > > On Thu, 14 Jan 2021 10:33:01 PST (-0800), ati...@atishpatra.org wrote:
&
On Thu, Jan 14, 2021 at 11:46 AM Palmer Dabbelt wrote:
>
> On Thu, 14 Jan 2021 10:33:01 PST (-0800), ati...@atishpatra.org wrote:
> > On Wed, Jan 13, 2021 at 9:10 PM Palmer Dabbelt wrote:
> >>
> >> On Thu, 07 Jan 2021 01:26:51 PST (-0800), Atish Patra wrote:
> &g
On Wed, Jan 13, 2021 at 9:10 PM Palmer Dabbelt wrote:
>
> On Thu, 07 Jan 2021 01:26:51 PST (-0800), Atish Patra wrote:
> > SMP_CACHE_BYTES/L1_CACHE_BYTES should be defined as 32 instead of
> > 64 for RV32. Otherwise, there will be hole of 32 bytes with each membl
On Mon, Jan 11, 2021 at 6:38 PM wrote:
>
> From: Guo Ren
>
> PAGE_KERNEL_EXEC has been defined above.
>
> Signed-off-by: Guo Ren
> Cc: Palmer Dabbelt
> Cc: Pekka Enberg
> ---
> arch/riscv/include/asm/pgtable.h | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git
On Mon, 2021-01-11 at 15:13 -0800, Jakub Kicinski wrote:
> On Mon, 11 Jan 2021 11:55:53 -0800 Atish Patra wrote:
> > There is no usrio config defined for default gem config leading to
> > a kernel panic devices that don't define a data. This issue can be
> > reprdouced with
a generic kernel issue where kernel pointers can not use
last 4k of addressable memory. I am open to other better alternate
suggestions.
Changes from v1->v2:
1. Added Reviewed/Tested by tags.
2. Replaced PHYS_ADDR_MAX with explicit __pa(~(ulong)0).
Atish Patra (4):
RISC-V: Do not allocate membl
was technically valid.
Fix this issue by limiting the memblock if available memory spans the
entire address space.
Reviewed-by: Anup Patel
Signed-off-by: Atish Patra
---
arch/riscv/mm/init.c | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/mm/init.c
to allow 2GB physical address space.
Reviewed-by: Anup Patel
Signed-off-by: Atish Patra
---
arch/riscv/Kconfig | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 81b76d44725d..e9e2c1f0a690 100644
--- a/arch/riscv/Kconfig
+++ b
SMP_CACHE_BYTES/L1_CACHE_BYTES should be defined as 32 instead of
64 for RV32. Otherwise, there will be hole of 32 bytes with each memblock
allocation if it is requested to be aligned with SMP_CACHE_BYTES.
Reviewed-by: Anup Patel
Tested-by: Geert Uytterhoeven
(on vexriscv)
Signed-off-by: Atish
not going through memblock allocation code every time.
Fixes: 00ab027a3b82 ("RISC-V: Add kernel image sections to the resource tree")
Reviewed-by: Anup Patel
Tested-by: Geert Uytterhoeven
Signed-off-by: Atish Patra
---
arch/riscv/kernel/setup.c | 24 +---
1 file c
m configuration")
Signed-off-by: Atish Patra
---
drivers/net/ethernet/cadence/macb_main.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/net/ethernet/cadence/macb_main.c
b/drivers/net/ethernet/cadence/macb_main.c
index 814a5b10141d..47ee72ab7002 100644
--- a/drivers/net/ethernet/caden
On Sat, Jan 9, 2021 at 12:51 PM Palmer Dabbelt wrote:
>
> On Sun, 13 Dec 2020 17:02:19 PST (-0800), ati...@atishpatra.org wrote:
> > On Wed, Nov 18, 2020 at 4:39 PM Atish Patra wrote:
> >>
> >> This series attempts to move the ARM64 numa implementation to commo
On Sun, Jan 10, 2021 at 7:59 PM Anup Patel wrote:
>
> On Thu, Jan 7, 2021 at 2:57 PM Atish Patra wrote:
> >
> > Currently, linux kernel can not use last 4k bytes of addressable space
> > because
> > IS_ERR_VALUE macro treats those as an error. This will be an issu
On Thu, 2021-01-07 at 11:34 +, daire.mcnam...@microchip.com wrote:
> From: Daire McNamara
>
> This patchset adds support for the Microchip PolarFire clkcfg
> hardware block.
>
> Major changes since v1:
> * Dependency on SOC_MICROCHIP_POLARFIRE
Does the sdcard work for with latest kernel ?
On Thu, Jan 7, 2021 at 3:44 AM wrote:
>
> Hi Atish,
>
> On 12/4/20 8:58 AM, Atish Patra wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> > content is safe
> >
> > Add initial DTS for Microchip ICICLE board having only
On Thu, Jan 7, 2021 at 3:40 AM wrote:
>
> Hi Atish,
>
> On 12/4/20 8:58 AM, Atish Patra wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> > content is safe
> >
> > Add Microchip PolarFire kconfig option which selects
to allow 2GB physical address space.
Signed-off-by: Atish Patra
---
arch/riscv/Kconfig | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 81b76d44725d..e9e2c1f0a690 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
SMP_CACHE_BYTES/L1_CACHE_BYTES should be defined as 32 instead of
64 for RV32. Otherwise, there will be hole of 32 bytes with each memblock
allocation if it is requested to be aligned with SMP_CACHE_BYTES.
Signed-off-by: Atish Patra
---
arch/riscv/include/asm/cache.h | 4
1 file changed, 4
was technically
valid.
Fix this issue by limiting the memblock if available memory spans the entire
address space.
Signed-off-by: Atish Patra
---
arch/riscv/mm/init.c | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
a generic kernel issue where kernel pointers can not use
last 4k of addressable memory. I am open to other better alternate
suggestions.
Atish Patra (4):
RISC-V: Do not allocate memblock while iterating reserved memblocks
RISC-V: Set current memblock limit
RISC-V: Fix L1_CACHE_BYTES for RV32
RISC-V
not going through memblock allocation code every time.
Fixes: 00ab027a3b82 ("RISC-V: Add kernel image sections to the resource tree")
Signed-off-by: Atish Patra
---
arch/riscv/kernel/setup.c | 24 +---
1 file changed, 13 insertions(+), 11 deletions(-)
diff --git a/
t;+22>:addisp,sp,16
>0xffe0002081a2 <+24>:ret
>
> (gdb) frame 5
> (rec=0xffe01ae40c30, enable=3) at kernel/trace/ftrace.c:2503
> 2503return ftrace_make_call(rec, ftrace_addr);
> (gdb) p /x rec->ip
> $2 = 0xffe00020817a -&
On Mon, Dec 21, 2020 at 7:19 PM Palmer Dabbelt wrote:
>
> On Fri, 04 Dec 2020 00:58:30 PST (-0800), Atish Patra wrote:
> > This series adds minimal support for Microchip Polar Fire Soc Icicle kit.
> > It is rebased on v5.10-rc6 and depends on clock support.
> > Only
nable LOCKDEP_SUPPORT & fixup
TRACE_IRQFLAGS_SUPPORT")
Cc: sta...@vger.kernel.org
Signed-off-by: Atish Patra
---
arch/riscv/kernel/entry.S | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
index 524d918f3601..7dea5
: Bin Meng
Tested-by: Bin Meng
Acked-by: Mike Rapoport
Signed-off-by: Atish Patra
---
Changes from v1->v2:
1. Added stable-kernel in cc.
2. Added reported/tested by tag.
---
arch/riscv/mm/init.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/mm/init.c b/arch/ri
On Thu, Dec 17, 2020 at 12:33 AM Atish Patra wrote:
>
> On Wed, Dec 16, 2020 at 10:51 PM Palmer Dabbelt wrote:
> >
> > On Tue, 15 Dec 2020 22:02:54 PST (-0800), Palmer Dabbelt wrote:
> > > On Wed, 04 Nov 2020 16:04:37 PST (-0800), Atish Patra wrote:
> > &
On Thu, Dec 17, 2020 at 12:53 AM Bin Meng wrote:
>
> Hi Atish,
>
> On Thu, Dec 17, 2020 at 4:43 PM Atish Patra wrote:
> >
> > On Thu, Dec 17, 2020 at 12:12 AM Bin Meng wrote:
> > >
> > > Hi Atish,
> > >
>
On Thu, Dec 17, 2020 at 12:12 AM Bin Meng wrote:
>
> Hi Atish,
>
> On Thu, Dec 17, 2020 at 3:49 PM Atish Patra wrote:
> >
> > memblock_enforce_memory_limit accepts the maximum memory size not the last
> > address. Fix the function invocation correctly.
> &
On Wed, Dec 16, 2020 at 10:51 PM Palmer Dabbelt wrote:
>
> On Tue, 15 Dec 2020 22:02:54 PST (-0800), Palmer Dabbelt wrote:
> > On Wed, 04 Nov 2020 16:04:37 PST (-0800), Atish Patra wrote:
> >> In order to improve kernel text protection, we need separate .init.text/
memblock_enforce_memory_limit accepts the maximum memory size not the last
address. Fix the function invocation correctly.
Fixes: 1bd14a66ee52 ("RISC-V: Remove any memblock representing unusable memory
area")
Signed-off-by: Atish Patra
---
arch/riscv/mm/init.c | 2 +-
1 file
On Wed, Nov 18, 2020 at 4:39 PM Atish Patra wrote:
>
> This series attempts to move the ARM64 numa implementation to common
> code so that RISC-V can leverage that as well instead of reimplementing
> it again.
>
> RISC-V specific bits are based on initial work done
From: Conor Dooley
Add Cyril Jean and Lewis Hanly as maintainers for the Microchip SoC
directory
Signed-off-by: Conor Dooley
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 2daa6ee673f7..cccb7d6c58aa 100644
--- a/MAINTAINERS
+++
Add initial DTS for Microchip ICICLE board having only
essential devices (clocks, sdhci, ethernet, serial, etc).
The device tree is based on the U-Boot patch.
https://patchwork.ozlabs.org/project/uboot/patch/20201110103414.10142-6-padmarao.beg...@microchip.com/
Signed-off-by: Atish Patra
Enable Microchip PolarFire ICICLE soc config in defconfig.
It allows the default upstream kernel to boot on PolarFire ICICLE board.
Signed-off-by: Atish Patra
Reviewed-by: Anup Patel
Reviewed-by: Bin Meng
---
arch/riscv/configs/defconfig | 4
1 file changed, 4 insertions(+)
diff --git
Add YAML DT binding documentation for the Microchip PolarFire SoC.
It is documented at:
https://www.microsemi.com/products/fpga-soc/polarfire-soc-icicle-quick-start-guide
Signed-off-by: Atish Patra
---
.../devicetree/bindings/riscv/microchip.yaml | 28 +++
1 file changed, 28
Add Microchip PolarFire kconfig option which selects SoC specific
and common drivers that is required for this SoC.
Signed-off-by: Atish Patra
Reviewed-by: Bin Meng
Reviewed-by: Anup Patel
---
arch/riscv/Kconfig.socs | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/riscv
the DT to match the device tree in U-Boot.
2. Added both eMMC & SDcard entries in DT. However, SD card is only enabled
as it allows larger storage option for linux distros.
Atish Patra (4):
RISC-V: Add Microchip PolarFire SoC kconfig option
dt-bindings: riscv: microchip: Add YAML doc
On Wed, 2020-12-02 at 16:20 +, daire.mcnam...@microchip.com wrote:
>
>
> From: Atish Patra
> Sent: Friday 13 November 2020 20:25
> To: linux-kernel@vger.kernel.org
> Cc: Atish Patra ; Albert Ou <
> a...@eecs.berkeley.edu>; Alistair Francis ;
> Anup Pate
On Tue, Dec 1, 2020 at 1:01 AM wrote:
>
> From: Vitaly Wool
>
> Cuurently mmu_enabled flag is set to true way later than the actual
> MMU enablement takes place. This leads to hard-to-track races in
> e. g. SBI earlycon initialization taking wrong path configuring
> fixmap.
>
This code path is
;
> + }
> } else {
> __sbi_set_timer = __sbi_set_timer_v01;
> __sbi_send_ipi = __sbi_send_ipi_v01;
> --
> 2.25.1
>
>
> ___
> linux-riscv mailing list
> linux-ri...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
Apart from that, it looks good to me.
Reviewed-by: Atish Patra
--
Regards,
Atish
On Fri, 2020-11-27 at 13:44 +0530, Anup Patel wrote:
> On Mon, Aug 3, 2020 at 11:29 PM Atish Patra
> wrote:
> >
> > The Supervisor Binary Interface(SBI) specification[1] now defines a
> > base extension that provides extendability to add future extensions
> &
/
> -
> #define ARCH_HAS_READ_CURRENT_TIMER
> static inline int read_current_timer(unsigned long *timer_val)
> {
> --
> 2.29.2.454.gaff20da3a2-goog
>
>
> ___
> linux-riscv mailing list
> linux-ri...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
Reviewed-by: Atish Patra
--
Regards,
Atish
This is a preparatory patch for unifying numa implementation between
ARM64 & RISC-V. As the numa implementation will be moved to generic
code, rename the arm64 related functions to a generic one.
Signed-off-by: Atish Patra
Acked-by: Catalin Marinas
---
arch/arm64/include/asm/numa.h
function.
Signed-off-by: Atish Patra
Reviewed-by: Greentime Hu
Reviewed-by: Anup Patel
Reviewed-by: Palmer Dabbelt
---
arch/riscv/include/asm/pgtable.h | 1 +
arch/riscv/kernel/setup.c| 1 +
arch/riscv/mm/init.c | 6 +-
3 files changed, 7 insertions(+), 1 deletion(-)
diff
Use the generic numa implementation to add NUMA support for RISC-V.
This is based on Greentime's patch[1] but modified to use generic NUMA
implementation and few more fixes.
[1] https://lkml.org/lkml/2020/1/10/233
Co-developed-by: Greentime Hu
Signed-off-by: Greentime Hu
Signed-off-by: Atish
this. This doesn't introduce any function changes for ARM64.
Signed-off-by: Atish Patra
Acked-by: Jonathan Cameron
Tested-by: Jonathan Cameron
Acked-by: Catalin Marinas
---
arch/arm64/Kconfig| 1 +
arch/arm64/include/asm/numa.h | 48 +
arch
From: Greentime Hu
These two functions are used to distinguish between PROT_NONENUMA
protections and hinting fault protections.
Signed-off-by: Greentime Hu
Reviewed-by: Anup Patel
Reviewed-by: Palmer Dabbelt
---
arch/riscv/include/asm/pgtable.h | 20
1 file changed, 20
gt;v3:
1. Added Acked-by/Reviewed-by tags.
2. Replaced asm/acpi.h with linux/acpi.h
3. Defined arch_acpi_numa_init as static.
Changes from v1->v2:
1. Replaced ARM64 specific compile time protection with ACPI specific ones.
2. Dropped common pcibus_to_node changes. Added required changes in RISC-V.
3.
On Mon, Nov 16, 2020 at 6:15 PM Bin Meng wrote:
>
> On Sat, Nov 14, 2020 at 4:29 AM Atish Patra wrote:
> >
> > Add initial DTS for Microchip ICICLE board having only
> > essential devcies (clocks, sdhci, ethernet, serial, etc).
>
> typo: devices
>
Thanks.
On Mon, Nov 16, 2020 at 7:23 AM Rob Herring wrote:
>
> On Fri, 13 Nov 2020 12:25:48 -0800, Atish Patra wrote:
> > Add YAML DT binding documentation for the Microchip PolarFire SoC.
> > It is documented at:
> >
> > https://www.microsemi.com/products/fpga-soc/polarfir
Add YAML DT binding documentation for the Microchip PolarFire SoC.
It is documented at:
https://www.microsemi.com/products/fpga-soc/polarfire-soc-icicle-quick-start-guide
Signed-off-by: Atish Patra
---
.../devicetree/bindings/riscv/microchip.yaml | 27 +++
1 file changed, 27
Add Microchip PolarFire kconfig option which selects SoC specific
and common drivers that is required for this SoC.
Signed-off-by: Atish Patra
Reviewed-by: Bin Meng
Reviewed-by: Anup Patel
---
arch/riscv/Kconfig.socs | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/riscv
Add initial DTS for Microchip ICICLE board having only
essential devcies (clocks, sdhci, ethernet, serial, etc).
The device tree is based on the U-Boot patch.
https://patchwork.ozlabs.org/project/uboot/patch/20201110103414.10142-6-padmarao.beg...@microchip.com/
Signed-off-by: Atish Patra
:
1. Modified the DT to match the device tree in U-Boot.
2. Added both eMMC & SDcard entries in DT. However, SD card is only enabled
as it allows larger storage option for linux distros.
Atish Patra (4):
RISC-V: Add Microchip PolarFire SoC kconfig option
dt-bindings: riscv: microchip: A
Enable Microchip PolarFire ICICLE soc config in defconfig.
It allows the default upstream kernel to boot on PolarFire ICICLE board.
Signed-off-by: Atish Patra
Reviewed-by: Anup Patel
Reviewed-by: Bin Meng
---
arch/riscv/configs/defconfig | 4
1 file changed, 4 insertions(+)
diff --git
On Fri, Nov 6, 2020 at 11:08 AM Catalin Marinas wrote:
>
> On Fri, Nov 06, 2020 at 09:33:14AM -0800, Atish Patra wrote:
> > On Fri, Nov 6, 2020 at 9:14 AM Catalin Marinas
> > wrote:
> > > On Mon, Oct 05, 2020 at 05:17:49PM -0700, Atish Patra wrote:
> > &
On Fri, Nov 6, 2020 at 9:14 AM Catalin Marinas wrote:
>
> On Mon, Oct 05, 2020 at 05:17:49PM -0700, Atish Patra wrote:
> > diff --git a/arch/arm64/kernel/acpi_numa.c b/arch/arm64/kernel/acpi_numa.c
> > index 7ff800045434..96502ff92af5 100644
> > --- a/arch/arm64/kernel/ac
On Thu, Nov 5, 2020 at 11:14 PM Palmer Dabbelt wrote:
>
> On Wed, 28 Oct 2020 16:27:56 PDT (-0700), Atish Patra wrote:
> > This series adds minimal support for Microchip Polar Fire Soc Icicle kit.
> > It is rebased on v5.10-rc1 and depends on clock support.
> > Only
Signed-off-by: Atish Patra
---
arch/riscv/kernel/head.S | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index 11e2a4fe66e0..45dbdae930bf 100644
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -177,7 +177,6 @@ setup_trap_vect
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