The following commit has been merged into the irq/irqchip-next branch of
irqchip:
Commit-ID: 9f3a0f34b84ad1b9a8f2bdae44b66f16685b2143
Gitweb:
https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/9f3a0f34b84ad1b9a8f2bdae44b66f16685b2143
Author:Bert Vermeulen
The following commit has been merged into the irq/irqchip-next branch of
irqchip:
Commit-ID: 4a2b92a5d3519fc2c1edda4d4aa0e05bff41e8de
Gitweb:
https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/4a2b92a5d3519fc2c1edda4d4aa0e05bff41e8de
Author:Bert Vermeulen
On 2/1/21 12:17 PM, Bhaskar Chowdhury wrote:
> s/debugees/debuge's/
Definitely not.
--
Bert Vermeulen
b...@biot.com
routing symbols to device tree interrupt-map. Parsing
is done similar to the renesas,rza1-irqc driver.
Bert Vermeulen (2):
dt-bindings: interrupt-controller: Add Realtek RTL838x/RTL839x support
irqchip: Add support for Realtek RTL838x/RTL839x interrupt controller
.../realtek,rtl-intc.yaml
Reviewed-by: Rob Herring
Signed-off-by: Bert Vermeulen
---
.../realtek,rtl-intc.yaml | 57 +++
1 file changed, 57 insertions(+)
create mode 100644
Documentation/devicetree/bindings/interrupt-controller/realtek,rtl-intc.yaml
diff --git
a/Documentation
This is a standard IRQ driver with only status and mask registers.
The mapping from SoC interrupts (18-31) to MIPS core interrupts is
done via an interrupt-map in device tree.
Signed-off-by: Bert Vermeulen
Signed-off-by: Birger Koblitz
---
drivers/irqchip/Makefile | 1 +
drivers
Python 2.x has been officially EOL'ed for some time, and in any case
the git module for it is hard to come by.
Signed-off-by: Bert Vermeulen
---
scripts/spdxcheck.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/scripts/spdxcheck.py b/scripts/spdxcheck.py
index
Signed-off-by: Bert Vermeulen
---
.../bindings/spi/realtek,rtl-spi.yaml | 41 +++
1 file changed, 41 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/realtek,rtl-spi.yaml
diff --git a/Documentation/devicetree/bindings/spi/realtek,rtl-spi.yaml
b
to build the
driver, since there's no point booting without the SPI-connected flash.
v2:
- Rewrote from spi-nor driver to regular spi driver, implementing only
set_cs() and transfer_one(). (Thanks Chuanhong Guo!)
Bert Vermeulen (2):
dt-bindings: spi: Realtek RTL838x/RTL839x SPI controller
spi
controller.
The hardware appears to have a vestigial second chip-select control, but
it hasn't been seen in the wild and is thus not supported.
Signed-off-by: Bert Vermeulen
---
drivers/spi/Makefile | 1 +
drivers/spi/spi-realtek-rtl.c | 209 ++
2 files changed
Signed-off-by: Bert Vermeulen
---
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-realtek-rtl.c | 180 ++
2 files changed, 181 insertions(+)
create mode 100644 drivers/irqchip/irq-realtek-rtl.c
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip
Signed-off-by: Bert Vermeulen
---
.../realtek,rtl-intc.yaml | 57 +++
1 file changed, 57 insertions(+)
create mode 100644
Documentation/devicetree/bindings/interrupt-controller/realtek,rtl-intc.yaml
diff --git
a/Documentation/devicetree/bindings/interrupt
v3:
- Fixed syntax and maxItems problems in DT bindings.
v2:
- Addressed all comments by Marc Zyngier.
- Moved interrupt routing symbols to device tree interrupt-map. Parsing
is done similar to the renesas,rza1-irqc driver.
Bert Vermeulen (2):
dt-bindings: interrupt-controller: Add Realtek
Signed-off-by: Bert Vermeulen
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml
b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 041ae90b0d8f..e6e3a51fc2e3 100644
are already written and functional, and work to
get them upstream is already in progress.
Signed-off-by: Birger Koblitz
Signed-off-by: Bert Vermeulen
Signed-off-by: John Crispin
Signed-off-by: Sander Vanheule
---
arch/mips/boot/dts/Makefile | 1 +
arch/mips/boot/dts/realtek
Signed-off-by: Bert Vermeulen
---
.../devicetree/bindings/mips/realtek-rtl.yaml | 24 +++
1 file changed, 24 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mips/realtek-rtl.yaml
diff --git a/Documentation/devicetree/bindings/mips/realtek-rtl.yaml
b
. This will be further
filled out, and bindings documented, as drivers get merged.
Bert Vermeulen (5):
dt-bindings: mips: Add support for RTL83xx SoC series
Add support for Realtek RTL838x/RTL839x switch SoCs
MIPS: Add Realtek RTL838x/RTL839x support as generic MIPS system
dt-bindings: Add Cisco
Signed-off-by: Bert Vermeulen
---
arch/mips/Kconfig | 10
arch/mips/boot/dts/realtek/Makefile | 2 ++
arch/mips/boot/dts/realtek/cisco_sg220-26.dts | 25 +++
3 files changed, 37 insertions(+)
create mode 100644 arch/mips/boot/dts
This is just enough system to boot the kernel with earlycon working.
Signed-off-by: Bert Vermeulen
Signed-off-by: Sander Vanheule
---
arch/mips/Kconfig | 21 +
1 file changed, 21 insertions(+)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 0a17bedf4f0d
On 1/5/21 6:04 PM, Rob Herring wrote:
On Mon, 04 Jan 2021 14:17:54 +0100, Bert Vermeulen wrote:
Signed-off-by: Bert Vermeulen
---
.../realtek,rtl-intc.yaml | 57 +++
1 file changed, 57 insertions(+)
create mode 100644
Documentation/devicetree/bindings
Signed-off-by: Bert Vermeulen
---
.../bindings/spi/realtek,rtl-spi.yaml | 38 +++
1 file changed, 38 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/realtek,rtl-spi.yaml
diff --git a/Documentation/devicetree/bindings/spi/realtek,rtl-spi.yaml
b
controller.
The hardware appears to have a vestigial second chip-select control, but
it hasn't been seen in the wild and is thus not supported.
Signed-off-by: Bert Vermeulen
---
MAINTAINERS | 6 +
drivers/spi/Makefile | 1 +
drivers/spi/spi-realtek-rtl.c | 206
without the SPI-connected flash.
v2:
- Rewrote from spi-nor driver to regular spi driver, implementing only
set_cs() and transfer_one(). (Thanks Chuanhong Guo!)
Bert Vermeulen (2):
dt-bindings: spi: Realtek RTL838x/RTL839x SPI controller
spi: realtek-rtl: Add support for Realtek RTL838x
On 1/4/21 10:31 PM, Mark Brown wrote:
On Fri, Jan 01, 2021 at 02:24:31PM +0100, Bert Vermeulen wrote:
+ compatible:
+const: realtek,rtl-spi
This is still just using rtl-spi as the compatible string, please
address the feedback on the previous version.
Mark,
The rtl prefix really
This is a standard IRQ driver with only status and mask registers.
The mapping from SoC interrupts (18-31) to MIPS core interrupts is
done via an interrupt-map in device tree.
Signed-off-by: Bert Vermeulen
---
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-realtek-rtl.c | 180
Signed-off-by: Bert Vermeulen
---
.../realtek,rtl-intc.yaml | 57 +++
1 file changed, 57 insertions(+)
create mode 100644
Documentation/devicetree/bindings/interrupt-controller/realtek,rtl-intc.yaml
diff --git
a/Documentation/devicetree/bindings/interrupt
v2:
- Addressed all comments by Marc Zyngier.
- Moved interrupt routing symbols to device tree interrupt-map. Parsing
is done similar to the renesas,rza1-irqc driver.
Bert Vermeulen (2):
dt-bindings: interrupt-controller: Add Realtek RTL838x/RTL839x support
irqchip: Add support for Realtek
Signed-off-by: Bert Vermeulen
---
.../bindings/spi/realtek,rtl-spi.yaml | 36 +++
1 file changed, 36 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/realtek,rtl-spi.yaml
diff --git a/Documentation/devicetree/bindings/spi/realtek,rtl-spi.yaml
b
controller.
The hardware appears to have a vestigial second chip-select control, but
it hasn't been seen in the wild and is thus not supported.
Signed-off-by: Bert Vermeulen
---
MAINTAINERS | 6 +
drivers/spi/Makefile | 1 +
drivers/spi/spi-realtek-rtl.c | 205
-nor driver to regular spi driver, implementing only
set_cs() and transfer_one(). (Thanks Chuanhong Guo!)
Bert Vermeulen (2):
dt-bindings: spi: Realtek RTL838x/RTL839x SPI controller
spi: realtek-rtl: Add support for Realtek RTL838x/RTL839x SoC SPI
controllers
.../bindings/spi/realtek
On 12/31/20 3:23 PM, Lukas Wunner wrote:
On Wed, Dec 30, 2020 at 12:19:04AM +0100, Bert Vermeulen wrote:
+static inline void wait_ready(struct rtspi *rtspi)
+{
+ while (!(readl(REG(RTL8380_SPI_SFCSR)) & RTL8380_SPI_SFCSR_RDY))
+ ;
+}
I'd suggest calling cpu_r
On 12/30/20 2:51 PM, Mark Brown wrote:
> On Wed, Dec 30, 2020 at 12:19:03AM +0100, Bert Vermeulen wrote:
>
>> +properties:
>> + compatible:
>> +const: realtek,spi
>
> It is possibled Realtek might make other SPI controllers, there should
> be some more s
On 12/30/20 10:22 PM, Bert Vermeulen wrote:
The RTL838x/839x family of SoCs are Realtek switches with an embedded
MIPS core.
Oops, forgot patch version note:
v3:
- all code removed, the base system is now only device tree files and docs
and some build config.
- ioremap.h restored to the v1
are already written and functional, and work to
get them upstream is already in progress.
Signed-off-by: Birger Koblitz
Signed-off-by: Bert Vermeulen
Signed-off-by: John Crispin
Signed-off-by: Sander Vanheule
---
.../devicetree/bindings/mips/realtek-rtl.yaml | 24 ++
arch/mips/boot/dts
This is just enough system to boot the kernel with earlycon working.
Signed-off-by: Bert Vermeulen
Signed-off-by: Sander Vanheule
---
arch/mips/Kconfig | 21 ++
arch/mips/generic/Platform | 1 +
arch/mips/include/asm/realtek/ioremap.h | 29
Signed-off-by: Bert Vermeulen
Signed-off-by: Sander Vanheule
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml
b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index
Signed-off-by: Bert Vermeulen
Signed-off-by: Sander Vanheule
---
arch/mips/Kconfig | 10 +++
arch/mips/boot/dts/realtek/Makefile | 2 +
arch/mips/boot/dts/realtek/cisco_sg220-26.dts | 81 +++
3 files changed, 93 insertions(+)
create mode
controller.
The hardware appears to have a vestigial second chip-select control, but
it hasn't been seen in the wild and is thus not supported.
Signed-off-by: Bert Vermeulen
---
(resent due to mail trouble)
Notes:
v2: rewrote from spi-nor driver to regular spi driver, implementing only
set_cs
Signed-off-by: Bert Vermeulen
---
(resent due to mail trouble)
.../devicetree/bindings/spi/realtek,spi.yaml | 36 +++
1 file changed, 36 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/realtek,spi.yaml
diff --git a/Documentation/devicetree/bindings/spi
On 12/23/20 5:18 PM, Marc Zyngier wrote:
Marc,
Thanks for reviewing. We will rework as needed, however:
On Wed, 23 Dec 2020 15:06:24 +,
Bert Vermeulen wrote:
[...]
+/* Interrupt numbers/bits */
+#define RTL8380_IRQ_UART0 31
+#define RTL8380_IRQ_UART1 30
Board support depends on MACH_INGENIC, not BOARD_INGENIC.
Signed-off-by: Bert Vermeulen
---
arch/mips/generic/Kconfig | 6 --
1 file changed, 6 deletions(-)
diff --git a/arch/mips/generic/Kconfig b/arch/mips/generic/Kconfig
index 55d9aed7ced9..5216c850b7e2 100644
--- a/arch/mips/generic
On 12/20/20 9:51 AM, Chuanhong Guo wrote:
Hi!
On Sun, Dec 20, 2020 at 7:01 AM Bert Vermeulen wrote:
On 12/16/20 9:30 AM, tudor.amba...@microchip.com wrote:
> On 12/15/20 11:46 PM, Bert Vermeulen wrote:
>> This driver supports the spiflash core in all RTL838x/RTL839x SoCs,
>>
On 12/16/20 9:30 AM, tudor.amba...@microchip.com wrote:
On 12/15/20 11:46 PM, Bert Vermeulen wrote:
This driver supports the spiflash core in all RTL838x/RTL839x SoCs,
and likely some older models as well (RTL8196C).
Can we use SPIMEM and move this under drivers/spi/ instead?
I wasn't aware
:)
I wish! Unfortunately I need somewhere to put the early printk init call,
and the SoC family ID checks -- as they are heavily used in various drivers.
--
Bert Vermeulen
b...@biot.com
This driver supports the spiflash core in all RTL838x/RTL839x SoCs,
and likely some older models as well (RTL8196C).
Signed-off-by: Bert Vermeulen
---
drivers/mtd/spi-nor/controllers/Kconfig | 7 +
drivers/mtd/spi-nor/controllers/Makefile | 1 +
.../spi-nor/controllers/rtl8380
Signed-off-by: Bert Vermeulen
---
arch/mips/Kbuild.platforms| 1 +
arch/mips/Kconfig | 20 +++
arch/mips/include/asm/mach-realtek/ioremap.h | 29
arch/mips/include/asm/mach-realtek/irq.h | 69
.../include/asm/mach-realtek
fault to addr_width of 3 for
configurable widths")
Signed-off-by: Bert Vermeulen
Reviewed-by: Tudor Ambarus
---
drivers/mtd/spi-nor/core.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index 03
If a flash chip has more than 16MB capacity but its BFPT reports
BFPT_DWORD1_ADDRESS_BYTES_3_OR_4, the spi-nor framework defaults to 3.
The check in spi_nor_set_addr_width() doesn't catch it because addr_width
did get set. This fixes that check.
Signed-off-by: Bert Vermeulen
---
drivers/mtd
On 10/2/20 9:50 AM, David Laight wrote:
> From: Bert Vermeulen
>> The SoCs I'm dealing with have an SPI_ADDR_SEL pin, indicating whether it
>> should be in 3 or 4-byte mode. The vendor's hacked-up U-Boot sets the mode
>> accordingly, as does their BSP. It seems to me like a m
000) {
+ /* enable 4-byte addressing if the device exceeds 16MiB */
+ nor->addr_width = 4;
+ }
+
Still fixes the general case, but I'm not sure what the SMPT parsing problem
is -- would this still trigger it?
--
Bert Vermeulen
b...@biot.com
hen BFPT_DWORD1_ADDRESS_BYTES_3_OR_4 is found fixes the
problem for all such cases.
Signed-off-by: Bert Vermeulen
---
drivers/mtd/spi-nor/sfdp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c
index e2a43d39eb5f..6fedc425bcf7 100
This platform is based on a Marvell 88E6282 SoC and 88E6171 switch.
Signed-off-by: Bert Vermeulen <b...@biot.com>
---
Changes from v3:
- added comment noting eth1 is connected to switch as well
Changes from v2:
- added linksys to filename
- added make rule
Changes from v1:
- changed c
This platform is based on a Marvell 88E6282 SoC and 88E6171 switch.
Signed-off-by: Bert Vermeulen
---
Changes from v3:
- added comment noting eth1 is connected to switch as well
Changes from v2:
- added linksys to filename
- added make rule
Changes from v1:
- changed console to stdout-path
This platform is based on a Marvell 88E6282 SoC and 88E6171 switch.
---
Changes from v2:
- added linksys to filename
- added make rule
Changes from v1:
- changed console to stdout-path
- removed unnecesarry @0 from dsa node, and fixed dsa/switch node
- fixed partitions according to the official
This platform is based on a Marvell 88E6282 SoC and 88E6171 switch.
---
Changes from v2:
- added linksys to filename
- added make rule
Changes from v1:
- changed console to stdout-path
- removed unnecesarry @0 from dsa node, and fixed dsa/switch node
- fixed partitions according to the official
On 04/02/2016 06:16 PM, Andrew Lunn wrote:
On Sat, Apr 02, 2016 at 02:55:52PM +0200, Bert Vermeulen wrote:
+ * (c) 2013 Jonas Gorski <j...@openwrt.org>
+ * (c) 2013 Deutsche Telekom Innovation Laboratories
+ * (c) 2014 Luka Perkov <l...@openwrt.org>
+ * (c) 2014 Randy C. Wil
On 04/02/2016 06:16 PM, Andrew Lunn wrote:
On Sat, Apr 02, 2016 at 02:55:52PM +0200, Bert Vermeulen wrote:
+ * (c) 2013 Jonas Gorski
+ * (c) 2013 Deutsche Telekom Innovation Laboratories
+ * (c) 2014 Luka Perkov
+ * (c) 2014 Randy C. Will
+ *
+ * This file is licensed under the terms
This platform is based on a Marvell 88E6282 SoC and 88E6171 switch.
---
arch/arm/boot/dts/kirkwood-viper.dts | 236 +++
1 file changed, 236 insertions(+)
create mode 100644 arch/arm/boot/dts/kirkwood-viper.dts
diff --git a/arch/arm/boot/dts/kirkwood-viper.dts
This platform is based on a Marvell 88E6282 SoC and 88E6171 switch.
---
arch/arm/boot/dts/kirkwood-viper.dts | 236 +++
1 file changed, 236 insertions(+)
create mode 100644 arch/arm/boot/dts/kirkwood-viper.dts
diff --git a/arch/arm/boot/dts/kirkwood-viper.dts
This platform is based on a Marvell 88E6282 SoC and 88E6171 switch.
The DSA port labels follow the switchdev convention.
Signed-off-by: Bert Vermeulen <b...@biot.com>
---
arch/arm/boot/dts/kirkwood-candyhouse.dts | 228 ++
1 file changed, 228 insertions(+)
This platform is based on a Marvell 88E6282 SoC and 88E6171 switch.
The DSA port labels follow the switchdev convention.
Signed-off-by: Bert Vermeulen
---
arch/arm/boot/dts/kirkwood-candyhouse.dts | 228 ++
1 file changed, 228 insertions(+)
create mode 100644 arch
On 05/08/2015 05:48 PM, Andrew Lunn wrote:
> On Fri, May 08, 2015 at 04:18:49PM +0200, Bert Vermeulen wrote:
>> When the bus id was supplied via a struct platform_device, the driver wasn't
>> handling -1 to mean an unspecified id of the only instance of this driver,
>>
On 05/08/2015 12:14 PM, Frans Klaver wrote:
> On Thu, May 7, 2015 at 2:31 PM, Bert Vermeulen wrote:
>> +
>> + info->chip.priv = info;
>> + info->mtd.priv = >chip;
>> + info->mtd.owner = THIS_MODULE;
>
> If you should respin, c
When the bus id was supplied via a struct platform_device, the driver wasn't
handling -1 to mean an unspecified id of the only instance of this driver,
as the platform spec requires.
Signed-off-by: Bert Vermeulen
---
drivers/net/phy/mdio-gpio.c | 5 -
1 file changed, 4 insertions(+), 1
On 05/08/2015 12:14 PM, Frans Klaver wrote:
On Thu, May 7, 2015 at 2:31 PM, Bert Vermeulen b...@biot.com wrote:
+
+ info-chip.priv = info;
+ info-mtd.priv = info-chip;
+ info-mtd.owner = THIS_MODULE;
If you should respin, could you add
info-mtd.dev.parent = pdev-dev
When the bus id was supplied via a struct platform_device, the driver wasn't
handling -1 to mean an unspecified id of the only instance of this driver,
as the platform spec requires.
Signed-off-by: Bert Vermeulen b...@biot.com
---
drivers/net/phy/mdio-gpio.c | 5 -
1 file changed, 4
On 05/08/2015 05:48 PM, Andrew Lunn wrote:
On Fri, May 08, 2015 at 04:18:49PM +0200, Bert Vermeulen wrote:
When the bus id was supplied via a struct platform_device, the driver wasn't
handling -1 to mean an unspecified id of the only instance of this driver,
as the platform spec requires
-by: Bert Vermeulen
---
Changes in v2:
- Fix Kconfig dependencies and description
- Move NAND partitions into platform data
- Use gpiod API with lookup table, and devm_ as needed
- Code cleanup
arch/mips/include/asm/mach-ath79/rb4xx.h | 44 +++
drivers/mtd/nand/Kconfig | 7
-by: Bert Vermeulen b...@biot.com
---
Changes in v2:
- Fix Kconfig dependencies and description
- Move NAND partitions into platform data
- Use gpiod API with lookup table, and devm_ as needed
- Code cleanup
arch/mips/include/asm/mach-ath79/rb4xx.h | 44 +++
drivers/mtd/nand/Kconfig
>> +{
>> + struct rb4xx_cpld *cpld;
>> + struct rb4xx_cpld_platform_data *pdata;
>> + int ret;
>> +
>> + pdata = dev_get_platdata(>dev);
>
> Hmm... do we have helper in SPI framework to do that?
Not that I can see.
I'll fix thing
;
+
+ pdata = dev_get_platdata(spi-dev);
Hmm... do we have helper in SPI framework to do that?
Not that I can see.
I'll fix things according to your other comments.
--
Bert Vermeulenb...@biot.com email/xmpp
--
To unsubscribe from this list: send the line unsubscribe linux-kernel
On 21/04/15 16:02, Bert Vermeulen wrote:
The NAND chip containing the root filesystem is behind an SPI-connected
CPLD. This driver uses the spi-rb4xx driver to communicate with the CPLD.
The CPLD also acts as a GPIO expander: the ALE/CLE/NCE pins are set via
CPLD commands. Some LEDs
-by: Bert Vermeulen
---
arch/mips/include/asm/mach-ath79/rb4xx.h | 41 +++
drivers/mtd/nand/Kconfig | 4 +
drivers/mtd/nand/Makefile| 1 +
drivers/mtd/nand/rb4xx_nand.c| 536 +++
4 files changed, 582 insertions(+)
create
On 04/21/2015 11:46 AM, Geert Uytterhoeven wrote:
> On Mon, Apr 20, 2015 at 10:37 PM, Mark Brown wrote:
>> On Mon, Apr 20, 2015 at 03:53:25PM +0200, Bert Vermeulen wrote:
>>> As it turns out, the set_cs() enable parameter refers to the logic level
>>> on the CS
On 04/21/2015 11:46 AM, Geert Uytterhoeven wrote:
On Mon, Apr 20, 2015 at 10:37 PM, Mark Brown broo...@kernel.org wrote:
On Mon, Apr 20, 2015 at 03:53:25PM +0200, Bert Vermeulen wrote:
As it turns out, the set_cs() enable parameter refers to the logic level
on the CS pin, not the state of chip
On 21/04/15 16:02, Bert Vermeulen wrote:
The NAND chip containing the root filesystem is behind an SPI-connected
CPLD. This driver uses the spi-rb4xx driver to communicate with the CPLD.
The CPLD also acts as a GPIO expander: the ALE/CLE/NCE pins are set via
CPLD commands. Some LEDs
-by: Bert Vermeulen b...@biot.com
---
arch/mips/include/asm/mach-ath79/rb4xx.h | 41 +++
drivers/mtd/nand/Kconfig | 4 +
drivers/mtd/nand/Makefile| 1 +
drivers/mtd/nand/rb4xx_nand.c| 536 +++
4 files changed, 582 insertions
As it turns out, the set_cs() enable parameter refers to the logic level
on the CS pin, not the state of chip selection.
This broke functionality of the LEDs behind the CPLD, or at least delayed
the commands until another one came in to toggle CS.
Signed-off-by: Bert Vermeulen
---
drivers/spi
As it turns out, the set_cs() enable parameter refers to the logic level
on the CS pin, not the state of chip selection.
This broke functionality of the LEDs behind the CPLD, or at least delayed
the commands until another one came in to toggle CS.
Signed-off-by: Bert Vermeulen b...@biot.com
. The second bit is transmitted with the SoC's CS2 pin.
Signed-off-by: Bert Vermeulen
---
Changes in v7:
- use SPI_TX_DUAL/tx_nbits to signal two-wire mode
- use SPI_MASTER_MUST_TX for dummy writes
- use bits_per_word_mask to restrict word size
- properly disable/unprepare clock on module removal
. The second bit is transmitted with the SoC's CS2 pin.
Signed-off-by: Bert Vermeulen b...@biot.com
---
Changes in v7:
- use SPI_TX_DUAL/tx_nbits to signal two-wire mode
- use SPI_MASTER_MUST_TX for dummy writes
- use bits_per_word_mask to restrict word size
- properly disable/unprepare clock
On 04/06/2015 06:39 PM, Mark Brown wrote:> On Mon, Apr 06, 2015 at
03:54:23AM +0200, Bert Vermeulen wrote:
>> +if (spi->chip_select == 1 && t->cs_change) {
>> +/* CPLD in bulk write mode gets two bits per clock */
>> +
On 04/06/2015 06:39 PM, Mark Brown wrote: On Mon, Apr 06, 2015 at
03:54:23AM +0200, Bert Vermeulen wrote:
+if (spi-chip_select == 1 t-cs_change) {
+/* CPLD in bulk write mode gets two bits per clock */
+do_spi_byte_fast(rbspi, spi_ioc, out
On 07/04/15 08:52, Lee Jones wrote:
> On Mon, 06 Apr 2015, Bert Vermeulen wrote:
>
>> The SPI-connected CPLD chip controls access to the main NAND flash
>> chip and five LEDs.
>>
>> Signed-off-by: Bert Vermeulen
>> ---
>> arch/mips/include/asm/mach-a
On 07/04/15 08:52, Lee Jones wrote:
On Mon, 06 Apr 2015, Bert Vermeulen wrote:
The SPI-connected CPLD chip controls access to the main NAND flash
chip and five LEDs.
Signed-off-by: Bert Vermeulen b...@biot.com
---
arch/mips/include/asm/mach-ath79/rb4xx_cpld.h | 49 +
drivers/mfd
ly. It's only the module_platform_driver() macro that
automatically fills in the owner field. All SPI protocol drivers do this
(except one, video/backlight/hx8357.c). Having said that, I don't really get
what that field is used for.
--
Bert Vermeulenb...@biot.com email/xmpp
SPI protocol drivers do this
(except one, video/backlight/hx8357.c). Having said that, I don't really get
what that field is used for.
--
Bert Vermeulenb...@biot.com email/xmpp
--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message
SPI clock
cycle. The second bit is transmitted with the SoC's CS2 pin.
Protocol drivers using this fast write facility signal this by setting
the cs_change flag on transfers.
Signed-off-by: Bert Vermeulen
---
Changes in v6:
- removed unnecessary SPI mode check
- whitespace fixes
drivers/s
The SPI-connected CPLD chip controls access to the main NAND flash
chip and five LEDs.
Signed-off-by: Bert Vermeulen
---
arch/mips/include/asm/mach-ath79/rb4xx_cpld.h | 49 +
drivers/mfd/Kconfig | 7 +
drivers/mfd/Makefile | 1
The SPI-connected CPLD chip controls access to the main NAND flash
chip and five LEDs.
Signed-off-by: Bert Vermeulen b...@biot.com
---
arch/mips/include/asm/mach-ath79/rb4xx_cpld.h | 49 +
drivers/mfd/Kconfig | 7 +
drivers/mfd/Makefile
. The second bit is transmitted with the SoC's CS2 pin.
Protocol drivers using this fast write facility signal this by setting
the cs_change flag on transfers.
Signed-off-by: Bert Vermeulen b...@biot.com
---
Changes in v6:
- removed unnecessary SPI mode check
- whitespace fixes
drivers/spi
SPI clock
cycle. The second bit is transmitted with the SoC's CS2 pin.
Protocol drivers using this fast write facility signal this by setting
the cs_change flag on transfers.
Signed-off-by: Bert Vermeulen
---
drivers/spi/Kconfig | 6 ++
drivers/spi/Makefile| 1 +
drivers/spi/spi-rb4
SPI clock
cycle. The second bit is transmitted with the SoC's CS2 pin.
Protocol drivers using this fast write facility signal this by setting
the cs_change flag on transfers.
Signed-off-by: Bert Vermeulen
---
drivers/spi/Kconfig | 6 ++
drivers/spi/Makefile| 1 +
drivers/spi/spi-rb4
SPI clock
cycle. The second bit is transmitted with the SoC's CS2 pin.
Protocol drivers using this fast write facility signal this by setting
the cs_change flag on transfers.
Signed-off-by: Bert Vermeulen
---
drivers/spi/Kconfig | 6 ++
drivers/spi/Makefile| 1 +
drivers/spi/spi-rb4
. The second bit is transmitted with the SoC's CS2 pin.
Protocol drivers using this fast write facility signal this by setting
the cs_change flag on transfers.
Signed-off-by: Bert Vermeulen b...@biot.com
---
drivers/spi/Kconfig | 6 ++
drivers/spi/Makefile| 1 +
drivers/spi/spi
. The second bit is transmitted with the SoC's CS2 pin.
Protocol drivers using this fast write facility signal this by setting
the cs_change flag on transfers.
Signed-off-by: Bert Vermeulen b...@biot.com
---
drivers/spi/Kconfig | 6 ++
drivers/spi/Makefile| 1 +
drivers/spi/spi
. The second bit is transmitted with the SoC's CS2 pin.
Protocol drivers using this fast write facility signal this by setting
the cs_change flag on transfers.
Signed-off-by: Bert Vermeulen b...@biot.com
---
drivers/spi/Kconfig | 6 ++
drivers/spi/Makefile| 1 +
drivers/spi/spi
SPI clock
cycle. The second bit is transmitted with the SoC's CS2 pin.
Protocol drivers using this fast write facility signal this by setting
the cs_change flag on transfers.
Signed-off-by: Bert Vermeulen
---
drivers/spi/Kconfig | 6 ++
drivers/spi/Makefile| 1 +
drivers/spi/spi-rb4
driver, as suggested.
Bert Vermeulen (1):
spi: Add SPI driver for Mikrotik RB4xx series boards
drivers/spi/Kconfig | 6 ++
drivers/spi/Makefile| 1 +
drivers/spi/spi-rb4xx.c | 241
3 files changed, 248 insertions(+)
create mode 100644
. The second bit is transmitted with the SoC's CS2 pin.
Protocol drivers using this fast write facility signal this by setting
the cs_change flag on transfers.
Signed-off-by: Bert Vermeulen b...@biot.com
---
drivers/spi/Kconfig | 6 ++
drivers/spi/Makefile| 1 +
drivers/spi/spi
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