On Wed, May 2, 2018 at 12:17 AM, Rob Herring wrote:
> On Mon, Apr 30, 2018 at 05:10:41PM +0530, Jagan Teki wrote:
>> Allwinner A64 has DE2 pipeline similar to other Allwinner
>> SOC's like A83T, H3/H5.
>
> 'dt-bindings: ' for the subject prefix.
>
>>
>> Signed-off-by: Jagan Teki
On Wed, May 2, 2018 at 12:17 AM, Rob Herring wrote:
> On Mon, Apr 30, 2018 at 05:10:41PM +0530, Jagan Teki wrote:
>> Allwinner A64 has DE2 pipeline similar to other Allwinner
>> SOC's like A83T, H3/H5.
>
> 'dt-bindings: ' for the subject prefix.
>
>>
>> Signed-off-by: Jagan Teki
>> ---
>>
On Mon, Apr 30, 2018 at 7:40 PM, Jagan Teki wrote:
> Allwinner 64-bit SoC like H5/A64 has DE2 CCU so enable them
> as default.
>
> Signed-off-by: Jagan Teki
> ---
> drivers/clk/sunxi-ng/Kconfig | 2 ++
> 1 file changed, 2 insertions(+)
>
>
On Mon, Apr 30, 2018 at 7:40 PM, Jagan Teki wrote:
> Allwinner 64-bit SoC like H5/A64 has DE2 CCU so enable them
> as default.
>
> Signed-off-by: Jagan Teki
> ---
> drivers/clk/sunxi-ng/Kconfig | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/clk/sunxi-ng/Kconfig
On Mon, Apr 30, 2018 at 7:40 PM, Jagan Teki wrote:
> Allwinner 64-bit SoC like H5/A64 has DesignWare HDMI so
> enable them as default.
Should we not also enable it by default for SUN8I (A83T, H3, R40?, etc.)
> Signed-off-by: Jagan Teki
>
On Mon, Apr 30, 2018 at 7:40 PM, Jagan Teki wrote:
> Allwinner 64-bit SoC like H5/A64 has DesignWare HDMI so
> enable them as default.
Should we not also enable it by default for SUN8I (A83T, H3, R40?, etc.)
> Signed-off-by: Jagan Teki
> ---
> drivers/gpu/drm/sun4i/Kconfig | 1 +
> 1 file
On Wed, May 2, 2018 at 12:16 AM, Rob Herring wrote:
> On Mon, Apr 30, 2018 at 05:10:38PM +0530, Jagan Teki wrote:
>> Allwinner A64 has DE2 CCU which is similar to H3/H5 SoC.
>>
>> Signed-off-by: Jagan Teki
>> ---
>>
On Wed, May 2, 2018 at 12:16 AM, Rob Herring wrote:
> On Mon, Apr 30, 2018 at 05:10:38PM +0530, Jagan Teki wrote:
>> Allwinner A64 has DE2 CCU which is similar to H3/H5 SoC.
>>
>> Signed-off-by: Jagan Teki
>> ---
>> Documentation/devicetree/bindings/clock/sun8i-de2.txt | 1 +
>> 1 file changed,
On Mon, Apr 30, 2018 at 6:44 PM, Andre Przywara wrote:
> Hi,
>
> On 30/04/18 10:51, Icenowy Zheng wrote:
>>
>>
>> 于 2018年4月30日 GMT+08:00 下午5:47:35, Andre Przywara 写到:
>>> Hi Icenowy,
>>>
>>> On 27/04/18 08:12, Icenowy Zheng wrote:
于
On Mon, Apr 30, 2018 at 6:44 PM, Andre Przywara wrote:
> Hi,
>
> On 30/04/18 10:51, Icenowy Zheng wrote:
>>
>>
>> 于 2018年4月30日 GMT+08:00 下午5:47:35, Andre Przywara 写到:
>>> Hi Icenowy,
>>>
>>> On 27/04/18 08:12, Icenowy Zheng wrote:
于 2018年4月27日 GMT+08:00 上午12:46:26, Andre Przywara
On Mon, Apr 30, 2018 at 5:47 PM, Andre Przywara wrote:
> Hi Icenowy,
>
> On 27/04/18 08:12, Icenowy Zheng wrote:
>>
>>
>> 于 2018年4月27日 GMT+08:00 上午12:46:26, Andre Przywara
>> 写到:
>>> Hi,
>>>
>>> On 26/04/18 15:07, Icenowy Zheng wrote:
The
On Mon, Apr 30, 2018 at 5:47 PM, Andre Przywara wrote:
> Hi Icenowy,
>
> On 27/04/18 08:12, Icenowy Zheng wrote:
>>
>>
>> 于 2018年4月27日 GMT+08:00 上午12:46:26, Andre Przywara
>> 写到:
>>> Hi,
>>>
>>> On 26/04/18 15:07, Icenowy Zheng wrote:
The Pine H64 board have a MicroSD slot connected to
Hi Rob,
On Tue, Apr 17, 2018 at 7:17 AM, Icenowy Zheng wrote:
>
>
> 于 2018年4月17日 GMT+08:00 上午2:47:45, Rob Herring 写到:
>>On Wed, Apr 11, 2018 at 10:16:37PM +0800, Icenowy Zheng wrote:
>>> On some Allwinner SoCs the EMAC clock register needed by dwmac-sun8i
>>is
Hi Rob,
On Tue, Apr 17, 2018 at 7:17 AM, Icenowy Zheng wrote:
>
>
> 于 2018年4月17日 GMT+08:00 上午2:47:45, Rob Herring 写到:
>>On Wed, Apr 11, 2018 at 10:16:37PM +0800, Icenowy Zheng wrote:
>>> On some Allwinner SoCs the EMAC clock register needed by dwmac-sun8i
>>is
>>> in another device's memory
On Wed, Apr 25, 2018 at 8:39 PM, Maxime Ripard
<maxime.rip...@bootlin.com> wrote:
> On Wed, Apr 25, 2018 at 11:19:20AM +0800, Chen-Yu Tsai wrote:
>> On Wed, Apr 25, 2018 at 3:37 AM, Maxime Ripard
>> <maxime.rip...@bootlin.com> wrote:
>> > On Tue, Apr 24, 20
On Wed, Apr 25, 2018 at 8:39 PM, Maxime Ripard
wrote:
> On Wed, Apr 25, 2018 at 11:19:20AM +0800, Chen-Yu Tsai wrote:
>> On Wed, Apr 25, 2018 at 3:37 AM, Maxime Ripard
>> wrote:
>> > On Tue, Apr 24, 2018 at 08:17:11PM +0800, Chen-Yu Tsai wrote:
>> >> On
On Wed, Apr 25, 2018 at 3:37 AM, Maxime Ripard
<maxime.rip...@bootlin.com> wrote:
> On Tue, Apr 24, 2018 at 08:17:11PM +0800, Chen-Yu Tsai wrote:
>> On Tue, Apr 24, 2018 at 8:13 PM, Maxime Ripard
>> <maxime.rip...@bootlin.com> wrote:
>> > On Tue, Apr 24, 20
On Wed, Apr 25, 2018 at 3:37 AM, Maxime Ripard
wrote:
> On Tue, Apr 24, 2018 at 08:17:11PM +0800, Chen-Yu Tsai wrote:
>> On Tue, Apr 24, 2018 at 8:13 PM, Maxime Ripard
>> wrote:
>> > On Tue, Apr 24, 2018 at 07:34:19PM +0800, Chen-Yu Tsai wrote:
>> >> The
On Tue, Apr 24, 2018 at 9:34 PM, Jagan Teki wrote:
> Allwinner A64 has DE2 pipeline similar to other Allwinner
> SOC's like A83T, H3/H5.
>
> Signed-off-by: Jagan Teki
> ---
> Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt |
On Tue, Apr 24, 2018 at 9:34 PM, Jagan Teki wrote:
> Allwinner A64 has DE2 pipeline similar to other Allwinner
> SOC's like A83T, H3/H5.
>
> Signed-off-by: Jagan Teki
> ---
> Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 1 +
All the device tree binding patches can be merged
On Mon, Apr 23, 2018 at 2:32 PM, Jagan Teki <ja...@amarulasolutions.com> wrote:
> Add usb otg support for bananapi-m64 board,
> - USB-ID connected with PH9
> - USB-DRVVBUS controlled by N_VBUSEN pin from PMIC
>
> Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
>
On Mon, Apr 23, 2018 at 2:32 PM, Jagan Teki wrote:
> Add usb otg support for bananapi-m64 board,
> - USB-ID connected with PH9
> - USB-DRVVBUS controlled by N_VBUSEN pin from PMIC
>
> Signed-off-by: Jagan Teki
> Reviewed-by: Chen-Yu Tsai
Applied with subject prefix chan
On Mon, Apr 23, 2018 at 2:32 PM, Jagan Teki <ja...@amarulasolutions.com> wrote:
> Add reg_drivevbus regualtor for boards which are using
> external regulator to drive the OTG VBus through N_VBUSEN
> PMIC pin.
>
> Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
>
On Mon, Apr 23, 2018 at 2:32 PM, Jagan Teki wrote:
> Add reg_drivevbus regualtor for boards which are using
> external regulator to drive the OTG VBus through N_VBUSEN
> PMIC pin.
>
> Signed-off-by: Jagan Teki
> Reviewed-by: Chen-Yu Tsai
Applied with subject prefix chan
On Tue, Apr 24, 2018 at 8:14 PM, Maxime Ripard
wrote:
> On Tue, Apr 24, 2018 at 01:47:14PM +0200, Neil Armstrong wrote:
>> The Libre Computer Board ALL-H3-CC from Libre Technology is a Raspberry
>> Pi B+ form factor single board computer based on the Allwinner H2+, H3,
On Tue, Apr 24, 2018 at 8:14 PM, Maxime Ripard
wrote:
> On Tue, Apr 24, 2018 at 01:47:14PM +0200, Neil Armstrong wrote:
>> The Libre Computer Board ALL-H3-CC from Libre Technology is a Raspberry
>> Pi B+ form factor single board computer based on the Allwinner H2+, H3,
>> or H5 SoCs with the same
On Tue, Apr 24, 2018 at 8:13 PM, Maxime Ripard
<maxime.rip...@bootlin.com> wrote:
> On Tue, Apr 24, 2018 at 07:34:19PM +0800, Chen-Yu Tsai wrote:
>> The Libre Computer Project ALL-H3-CC has three models, all using the
>> same board design, but with different pin compa
On Tue, Apr 24, 2018 at 8:13 PM, Maxime Ripard
wrote:
> On Tue, Apr 24, 2018 at 07:34:19PM +0800, Chen-Yu Tsai wrote:
>> The Libre Computer Project ALL-H3-CC has three models, all using the
>> same board design, but with different pin compatible SoCs and amount of
>> DRAM.
design part and an SoC specific part.
The SoC part only defines which SoC is used and model name, and includes
the SoC specific dtsi file and the common design dtsi file.
Also fix up the SPDX identifier line to use the correct comment style,
and place it on the first line.
Signed-off-by: Chen-Yu Tsai
design part and an SoC specific part.
The SoC part only defines which SoC is used and model name, and includes
the SoC specific dtsi file and the common design dtsi file.
Also fix up the SPDX identifier line to use the correct comment style,
and place it on the first line.
Signed-off-by: Chen-Yu Tsai
s 4Gb DDR3 chips instead of 2Gb ones.
The device tree utilizes the common board design file for ALL-H3-CC,
providing just the model strings and SoC specifics.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm64/boot/dts/allwinner/Makefile | 1 +
.../allwinner/sun50i-h5-
s 4Gb DDR3 chips instead of 2Gb ones.
The device tree utilizes the common board design file for ALL-H3-CC,
providing just the model strings and SoC specifics.
Signed-off-by: Chen-Yu Tsai
---
arch/arm64/boot/dts/allwinner/Makefile | 1 +
.../allwinner/sun50i-h5-libretech-all-h3-cc.d
At the board level, we want to be able to specify what regulator
supplies power to the cpu domain.
Add a label to the first cpu node so we can reference it later.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 2 +-
1 file changed, 1 ins
The dtb entries for NanoPi boards in the device tree makefile somehow
ended up after the Orange Pi boards.
Move them so the list is properly sorted.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm64/boot/dts/allwinner/Makefile | 4 ++--
1 file changed, 2 insertions(+), 2 del
The dtb entries for NanoPi boards in the device tree makefile somehow
ended up after the Orange Pi boards.
Move them so the list is properly sorted.
Signed-off-by: Chen-Yu Tsai
---
arch/arm64/boot/dts/allwinner/Makefile | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
At the board level, we want to be able to specify what regulator
supplies power to the cpu domain.
Add a label to the first cpu node so we can reference it later.
Signed-off-by: Chen-Yu Tsai
---
arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion
The dtb entry for the Banana Pi M2 Zero in the device tree makefile
somehow ended up in between two Orange Pi boards.
Move it so the list is properly sorted.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm/boot/dts/Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
, which
already has DVFS enabled and fixed regulator set for the CPU domain.
Patch 6 cleans up the H5 section of the arm64 allwinner dts Makefile.
Patch 7 adds a device tree for the H5 variant of ALL-H3-CC.
Please have a look.
ChenYu
Chen-Yu Tsai (7):
ARM: dts: sun8i: h3: fix ALL-H3-CC H3 ver VCC
The dtb entry for the Banana Pi M2 Zero in the device tree makefile
somehow ended up in between two Orange Pi boards.
Move it so the list is properly sorted.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm
, which
already has DVFS enabled and fixed regulator set for the CPU domain.
Patch 6 cleans up the H5 section of the arm64 allwinner dts Makefile.
Patch 7 adds a device tree for the H5 variant of ALL-H3-CC.
Please have a look.
ChenYu
Chen-Yu Tsai (7):
ARM: dts: sun8i: h3: fix ALL-H3-CC H3 ver VCC
)
Cc: <sta...@vger.kernel.org> # 4.16.x
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm/boot/dts/sun8i-h3-libretech-all-h3-cc.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-h3-libretech-all-h3-cc.dts
b/arch/arm/boot/dts/sun
s only two 2Gb DDR3 chips instead of four.
The device tree utilizes the common board design file for ALL-H3-CC,
providing just the model strings and SoC specifics.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm/boot/dts/Makefile | 1 +
.../boot/dts/sun8i-h
")
Cc: # 4.16.x
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-h3-libretech-all-h3-cc.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-h3-libretech-all-h3-cc.dts
b/arch/arm/boot/dts/sun8i-h3-libretech-all-h3-cc.dts
index 5971b8b0b768..db
s only two 2Gb DDR3 chips instead of four.
The device tree utilizes the common board design file for ALL-H3-CC,
providing just the model strings and SoC specifics.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/Makefile | 1 +
.../boot/dts/sun8i-h2-plus-libretech-all
On Mon, Apr 16, 2018 at 12:41 PM, Chen-Yu Tsai <w...@csie.org> wrote:
> Hi,
>
> On Tue, Feb 6, 2018 at 12:48 PM, Icenowy Zheng <icen...@aosc.io> wrote:
>> This patchset tries to add DVFS support for Allwinner H3 SoC,
>> considering two kinds of adjustable regulat
On Mon, Apr 16, 2018 at 12:41 PM, Chen-Yu Tsai wrote:
> Hi,
>
> On Tue, Feb 6, 2018 at 12:48 PM, Icenowy Zheng wrote:
>> This patchset tries to add DVFS support for Allwinner H3 SoC,
>> considering two kinds of adjustable regulators used on H3 boards:
>> SY810
On Thu, Apr 19, 2018 at 9:34 PM, Ondřej Jirman
wrote:
> Hello Giulio,
>
> this patch breaks LVDS output on A83T. Without it, modesetting works,
> with it there's no output.
>
> Some more info below...
>
> On Tue, Mar 13, 2018 at 12:20:19PM +0100, Giulio Benetti wrote:
On Thu, Apr 19, 2018 at 9:34 PM, Ondřej Jirman
wrote:
> Hello Giulio,
>
> this patch breaks LVDS output on A83T. Without it, modesetting works,
> with it there's no output.
>
> Some more info below...
>
> On Tue, Mar 13, 2018 at 12:20:19PM +0100, Giulio Benetti wrote:
>> mode_valid function is
On Thu, Apr 19, 2018 at 8:31 PM, Giulio Benetti
<giulio.bene...@micronovasrl.com> wrote:
> Hi,
>
> Il 19/04/2018 11:32, Chen-Yu Tsai ha scritto:
>>
>> This panel is marketed as Banana Pi 7" LCD display. On the back is
>> a sticker denoting the model name S070
On Thu, Apr 19, 2018 at 8:31 PM, Giulio Benetti
wrote:
> Hi,
>
> Il 19/04/2018 11:32, Chen-Yu Tsai ha scritto:
>>
>> This panel is marketed as Banana Pi 7" LCD display. On the back is
>> a sticker denoting the model name S070WV20-CT16.
>
>
> Judging from t
be dithering support that will be added in a
later patch, which looks at properties tied to the connector to
determine whether dithering should be enabled or not.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
drivers/gpu/drm/sun4i/sun4i_tcon.c | 15 ++-
1 file changed, 6 inse
be dithering support that will be added in a
later patch, which looks at properties tied to the connector to
determine whether dithering should be enabled or not.
Signed-off-by: Chen-Yu Tsai
---
drivers/gpu/drm/sun4i/sun4i_tcon.c | 15 ++-
1 file changed, 6 insertions(+), 9 deletions
seems pwm-backlight hardware is unusable at the moment. I'm not
sure whether the pwm-backlight or sun4i-pwm driver is to blame. I had to
manually poke the pwm registers so the LCD backlight wouldn't be
completely black.
Regards
ChenYu
Chen-Yu Tsai (5):
drm/sun4i: tcon: Pass d
irst; handle LVDS and MIPI DSI]
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
Hi Maxime,
The dithering parameters used here are different from the ones you used
in your MIPI DSI series. You might want to check if it still works for
you.
---
drivers/gpu/drm/sun4i
seems pwm-backlight hardware is unusable at the moment. I'm not
sure whether the pwm-backlight or sun4i-pwm driver is to blame. I had to
manually poke the pwm registers so the LCD backlight wouldn't be
completely black.
Regards
ChenYu
Chen-Yu Tsai (5):
drm/sun4i: tcon: Pass d
-by: Chen-Yu Tsai
---
Hi Maxime,
The dithering parameters used here are different from the ones you used
in your MIPI DSI series. You might want to check if it still works for
you.
---
drivers/gpu/drm/sun4i/sun4i_tcon.c | 63 +-
1 file changed, 62 insertions(+), 1 deletion
Dithering is only supported for TCON channel 0. Throughout the datasheet
all the names associated with these register are prefixed "TCON0",
instead of "TCON". The only exception is the control register
"TCON_FRM_CTL_REG".
Rename the macros to reflect this.
Dithering is only supported for TCON channel 0. Throughout the datasheet
all the names associated with these register are prefixed "TCON0",
instead of "TCON". The only exception is the control register
"TCON_FRM_CTL_REG".
Rename the macros to reflect this
This panel is marketed as Banana Pi 7" LCD display. On the back is
a sticker denoting the model name S070WV20-CT16.
This is a 7" 800x480 panel connected through a 24-bit RGB interface.
However the panel only does 262k colors.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
.
This panel is marketed as Banana Pi 7" LCD display. On the back is
a sticker denoting the model name S070WV20-CT16.
This is a 7" 800x480 panel connected through a 24-bit RGB interface.
However the panel only does 262k colors.
Signed-off-by: Chen-Yu Tsai
---
.../display/panel/bananap
thing, but it is nevertheless included for completeness. There
is also a FT5306 capacitive touchscreen controller.
This should not be confused with the other 7" LCD that is LVDS based
and has a resolution of 1024x600.
This patch enables all of the above for the BPI-M1+.
Signed-off-by: Chen-
thing, but it is nevertheless included for completeness. There
is also a FT5306 capacitive touchscreen controller.
This should not be confused with the other 7" LCD that is LVDS based
and has a resolution of 1024x600.
This patch enables all of the above for the BPI-M1+.
Signed-off-by: Ch
On the A20, as well as many other Allwinner SoCs, the PD pingroup has
the LCD0 RGB output functions.
Add a pinmux setting for RGB888 output from LCD0, so boards and tablets
with parallel RGB LCD panels may reference it.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm/boot/dts/sun
On the A20, as well as many other Allwinner SoCs, the PD pingroup has
the LCD0 RGB output functions.
Add a pinmux setting for RGB888 output from LCD0, so boards and tablets
with parallel RGB LCD panels may reference it.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun7i-a20.dtsi | 11
On Wed, Apr 18, 2018 at 4:45 PM, Maxime Ripard
<maxime.rip...@bootlin.com> wrote:
> On Tue, Apr 17, 2018 at 07:25:15PM +0800, Chen-Yu Tsai wrote:
>> On Tue, Apr 17, 2018 at 7:17 PM, Maxime Ripard
>> <maxime.rip...@bootlin.com> wrote:
>> > On Tue, Apr 17, 20
On Wed, Apr 18, 2018 at 4:45 PM, Maxime Ripard
wrote:
> On Tue, Apr 17, 2018 at 07:25:15PM +0800, Chen-Yu Tsai wrote:
>> On Tue, Apr 17, 2018 at 7:17 PM, Maxime Ripard
>> wrote:
>> > On Tue, Apr 17, 2018 at 11:12:41AM +0800, Chen-Yu Tsai wrote:
>> >> On
On Tue, Apr 17, 2018 at 7:52 PM, Maxime Ripard
<maxime.rip...@bootlin.com> wrote:
> On Mon, Apr 16, 2018 at 10:51:55PM +0800, Chen-Yu Tsai wrote:
>> On Mon, Apr 16, 2018 at 10:31 PM, Maxime Ripard
>> <maxime.rip...@bootlin.com> wrote:
>> > On Thu, Apr 12, 20
On Tue, Apr 17, 2018 at 7:52 PM, Maxime Ripard
wrote:
> On Mon, Apr 16, 2018 at 10:51:55PM +0800, Chen-Yu Tsai wrote:
>> On Mon, Apr 16, 2018 at 10:31 PM, Maxime Ripard
>> wrote:
>> > On Thu, Apr 12, 2018 at 11:23:30PM +0800, Chen-Yu Tsai wrote:
>> >> On Th
On Tue, Apr 17, 2018 at 7:17 PM, Maxime Ripard
<maxime.rip...@bootlin.com> wrote:
> On Tue, Apr 17, 2018 at 11:12:41AM +0800, Chen-Yu Tsai wrote:
>> On Tue, Apr 17, 2018 at 5:50 AM, Mylène Josserand
>> <mylene.josser...@bootlin.com> wrote:
>> > Move the asse
On Tue, Apr 17, 2018 at 7:17 PM, Maxime Ripard
wrote:
> On Tue, Apr 17, 2018 at 11:12:41AM +0800, Chen-Yu Tsai wrote:
>> On Tue, Apr 17, 2018 at 5:50 AM, Mylène Josserand
>> wrote:
>> > Move the assembly code for cluster cache enabling and resuming
>> > into a
On Tue, Apr 17, 2018 at 3:52 PM, Maxime Ripard
wrote:
> Hi,
>
> On Mon, Apr 16, 2018 at 11:50:29PM +0200, Mylène Josserand wrote:
>> To prepare the support of sun8i-a83t, add a field in the smp_data
>> structure to know if we are on sun9i-a80 or sun8i-a83t.
>>
>> Add
On Tue, Apr 17, 2018 at 3:52 PM, Maxime Ripard
wrote:
> Hi,
>
> On Mon, Apr 16, 2018 at 11:50:29PM +0200, Mylène Josserand wrote:
>> To prepare the support of sun8i-a83t, add a field in the smp_data
>> structure to know if we are on sun9i-a80 or sun8i-a83t.
>>
>> Add also a global variable to
ly.
>
> Signed-off-by: Mylène Josserand <mylene.josser...@bootlin.com>
Reviewed-by: Chen-Yu Tsai <w...@csie.org>
sserand
Reviewed-by: Chen-Yu Tsai
On Tue, Apr 17, 2018 at 5:50 AM, Mylène Josserand
wrote:
> Move the assembly code for cluster cache enabling and resuming
> into an assembly file instead of having it directly in C code.
>
> Remove the CFLAGS because we are using the ARM directive "arch"
> instead.
>
On Tue, Apr 17, 2018 at 5:50 AM, Mylène Josserand
wrote:
> Move the assembly code for cluster cache enabling and resuming
> into an assembly file instead of having it directly in C code.
>
> Remove the CFLAGS because we are using the ARM directive "arch"
> instead.
>
> Signed-off-by: Mylène
On Mon, Apr 16, 2018 at 10:31 PM, Maxime Ripard
<maxime.rip...@bootlin.com> wrote:
> On Thu, Apr 12, 2018 at 11:23:30PM +0800, Chen-Yu Tsai wrote:
>> On Thu, Apr 12, 2018 at 11:11 PM, Icenowy Zheng <icen...@aosc.io> wrote:
>> > 于 2018年4月12日 GMT+08:00 下午10:56:28, M
On Mon, Apr 16, 2018 at 10:31 PM, Maxime Ripard
wrote:
> On Thu, Apr 12, 2018 at 11:23:30PM +0800, Chen-Yu Tsai wrote:
>> On Thu, Apr 12, 2018 at 11:11 PM, Icenowy Zheng wrote:
>> > 于 2018年4月12日 GMT+08:00 下午10:56:28, Maxime Ripard
>> > 写到:
>> >>On Wed, Ap
On Mon, Apr 16, 2018 at 12:41 PM, Chen-Yu Tsai <w...@csie.org> wrote:
> Hi,
>
> On Tue, Feb 6, 2018 at 12:48 PM, Icenowy Zheng <icen...@aosc.io> wrote:
>> This patchset tries to add DVFS support for Allwinner H3 SoC,
>> considering two kinds of adjustable regulat
On Mon, Apr 16, 2018 at 12:41 PM, Chen-Yu Tsai wrote:
> Hi,
>
> On Tue, Feb 6, 2018 at 12:48 PM, Icenowy Zheng wrote:
>> This patchset tries to add DVFS support for Allwinner H3 SoC,
>> considering two kinds of adjustable regulators used on H3 boards:
>> SY810
Hi,
On Tue, Feb 6, 2018 at 12:48 PM, Icenowy Zheng wrote:
> This patchset tries to add DVFS support for Allwinner H3 SoC,
> considering two kinds of adjustable regulators used on H3 boards:
> SY8106A I2C-controlled regulator and SY8113B regulator (controllable
> by GPIO with
Hi,
On Tue, Feb 6, 2018 at 12:48 PM, Icenowy Zheng wrote:
> This patchset tries to add DVFS support for Allwinner H3 SoC,
> considering two kinds of adjustable regulators used on H3 boards:
> SY8106A I2C-controlled regulator and SY8113B regulator (controllable
> by GPIO with some special designs
axp813 the axp803 is also supporting external
>> > regulator to drive the OTG VBus through N_VBUSEN PMIC pin.
>> >
>> > Add support for it.
>> >
>> > Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
>> > Reviewed-by: Rob Herri
or to drive the OTG VBus through N_VBUSEN PMIC pin.
>> >
>> > Add support for it.
>> >
>> > Signed-off-by: Jagan Teki
>> > Reviewed-by: Rob Herring
>> > Reviewed-by: Chen-Yu Tsai
>> > ---
>> > Changes for v5:
>> >
On Sat, Apr 14, 2018 at 6:25 PM, Jagan Teki wrote:
> On Fri, Mar 16, 2018 at 11:23 PM, Icenowy Zheng wrote:
>> The "Display Engine 2.0" (usually called DE2) on the Allwinner A64 SoC
>> is different from the ones on other Allwinner SoCs. It requires a
On Sat, Apr 14, 2018 at 6:25 PM, Jagan Teki wrote:
> On Fri, Mar 16, 2018 at 11:23 PM, Icenowy Zheng wrote:
>> The "Display Engine 2.0" (usually called DE2) on the Allwinner A64 SoC
>> is different from the ones on other Allwinner SoCs. It requires a SRAM
>> region to be claimed, otherwise all
On Thu, Apr 12, 2018 at 11:11 PM, Icenowy Zheng <icen...@aosc.io> wrote:
>
>
> 于 2018年4月12日 GMT+08:00 下午10:56:28, Maxime Ripard <maxime.rip...@bootlin.com>
> 写到:
>>On Wed, Apr 11, 2018 at 10:16:39PM +0800, Icenowy Zheng wrote:
>>> From: Chen-Yu Tsai <w
On Thu, Apr 12, 2018 at 11:11 PM, Icenowy Zheng wrote:
>
>
> 于 2018年4月12日 GMT+08:00 下午10:56:28, Maxime Ripard
> 写到:
>>On Wed, Apr 11, 2018 at 10:16:39PM +0800, Icenowy Zheng wrote:
>>> From: Chen-Yu Tsai
>>>
>>> On the Allwinner R40 SoC, the &q
o>
Verified against public schematics.
Reviewed-by: Chen-Yu Tsai <w...@csie.org>
On Fri, Apr 6, 2018 at 10:03 PM, Icenowy Zheng wrote:
> Banana Pi M2 Berry has an on-board USB Hub that provides 4 USB Type-A
> ports, and it's connected to the USB1 port of the SoC.
>
> Enable it.
>
> Signed-off-by: Icenowy Zheng
Verified against public schematics.
Reviewed-by: Chen-Yu Tsai
On Tue, Apr 3, 2018 at 2:18 PM, Mylène Josserand
wrote:
> The R_CPUCFG is a collection of registers needed for SMP bringup
> on clusters and cluster's reset.
> For the moment, documentation about this register is found in
> Allwinner's code only.
>
> Signed-off-by:
On Tue, Apr 3, 2018 at 2:18 PM, Mylène Josserand
wrote:
> The R_CPUCFG is a collection of registers needed for SMP bringup
> on clusters and cluster's reset.
> For the moment, documentation about this register is found in
> Allwinner's code only.
>
> Signed-off-by: Mylène Josserand
> ---
>
register for clusters are different from a80 and a83t.
>
> Signed-off-by: Mylène Josserand <mylene.josser...@bootlin.com>
> Acked-by: Maxime Ripard <maxime.rip...@bootlin.com>
Reviewed-by: Chen-Yu Tsai <w...@csie.org>
om a80 and a83t.
>
> Signed-off-by: Mylène Josserand
> Acked-by: Maxime Ripard
Reviewed-by: Chen-Yu Tsai
On Tue, Apr 3, 2018 at 4:47 PM, Maxime Ripard wrote:
> On Tue, Apr 03, 2018 at 08:18:33AM +0200, Mylène Josserand wrote:
>> To prepare the support for sun8i-a83t, move some structures
>> at the beginning of the file.
>>
>> Signed-off-by: Mylène Josserand
On Tue, Apr 3, 2018 at 4:47 PM, Maxime Ripard wrote:
> On Tue, Apr 03, 2018 at 08:18:33AM +0200, Mylène Josserand wrote:
>> To prepare the support for sun8i-a83t, move some structures
>> at the beginning of the file.
>>
>> Signed-off-by: Mylène Josserand
>
> I'm not quite sure what would be the
On Tue, Apr 3, 2018 at 4:46 PM, Maxime Ripard wrote:
> On Tue, Apr 03, 2018 at 08:18:34AM +0200, Mylène Josserand wrote:
>> To prepare the support of sun8i-a83t, add a field in the smp_data
>> structure to enable the case of sun9i.
>>
>> Start to handle the differences
On Tue, Apr 3, 2018 at 4:46 PM, Maxime Ripard wrote:
> On Tue, Apr 03, 2018 at 08:18:34AM +0200, Mylène Josserand wrote:
>> To prepare the support of sun8i-a83t, add a field in the smp_data
>> structure to enable the case of sun9i.
>>
>> Start to handle the differences between sun9i-a80 and
down(unsigned int cluster)
> reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
> if (sunxi_mc_smp_data[index].is_sun9i)
> reg |= PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I;
> + else
> + reg |= PRCM_PWROFF_GATING_REG_CLUSTER_SUN8I;
>
ROFF_GATING_REG(cluster));
> if (sunxi_mc_smp_data[index].is_sun9i)
> reg |= PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I;
> + else
> + reg |= PRCM_PWROFF_GATING_REG_CLUSTER_SUN8I;
> writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
>
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